Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22781

1

T3

20

T4

16

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3312

1

T1

1

T2

7

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19767

1

T3

20

T5

20

T6

133

auto[1]

6326

1

T1

1

T2

7

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	612	1			T6	5		T7	4		T37	1
values[0]	48	1			T14	7		T239	15		T223	18
values[1]	666	1			T8	5		T180	22		T139	24
values[2]	2856	1			T1	1		T4	16		T11	1
values[3]	875	1			T6	3		T49	12		T149	30
values[4]	656	1			T8	13		T46	23		T48	12
values[5]	715	1			T8	16		T11	8		T49	7
values[6]	809	1			T2	7		T9	15		T10	1
values[7]	845	1			T38	1		T45	24		T48	11
values[8]	591	1			T10	20		T47	11		T61	17
values[9]	840	1			T9	38		T158	1		T148	17
minimum	16580	1			T3	20		T5	20		T6	130

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	674	1			T1	1		T8	5		T11	1
values[1]	2817	1			T4	16		T12	17		T45	22
values[2]	909	1			T6	3		T46	23		T49	12
values[3]	647	1			T8	13		T48	12		T60	29
values[4]	815	1			T8	16		T9	15		T11	8
values[5]	693	1			T2	7		T10	1		T45	24
values[6]	927	1			T38	1		T48	11		T158	1
values[7]	502	1			T10	20		T47	11		T158	1
values[8]	891	1			T9	38		T147	7		T148	17
values[9]	59	1			T193	9		T188	1		T251	7
minimum	17159	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	5		T48	13		T143	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T11	1		T147	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T4	16		T12	2		T45	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T263	1		T152	3		T193	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T149	16		T151	13		T146	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T6	2		T46	12		T49	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	13		T158	1		T148	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T48	12		T60	11		T166	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T9	4		T11	1		T49	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	16		T154	1		T182	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T45	12		T142	16		T140	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	7		T10	1		T60	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T266	1		T154	1		T144	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T38	1		T48	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	10		T47	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T167	5		T24	1		T271	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T9	17		T150	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T147	7		T148	10		T282	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T251	5		T373	1		T171	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T193	9		T188	1		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16908	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T191	1		T14	5		T239	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T143	6		T144	3		T265	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T294	6		T331	10		T290	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	895	1			T12	15		T45	3		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T263	15		T152	11		T160	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T149	14		T151	15		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	1		T46	11		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T148	11		T181	9		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T60	18		T151	13		T160	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	11		T11	7		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T154	11		T182	10		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T45	12		T140	16		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T60	8		T270	8		T169	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T154	16		T144	11		T279	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T61	13		T269	8		T278	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	10		T183	4		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T271	7		T305	3		T329	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	21		T154	7		T279	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	7		T282	14		T238	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T251	2		T171	5		T22	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T304	2		T258	3		T343	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T60	1		T180	10		T74	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T14	2		T239	14		T242	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	445	1			T6	5		T7	4		T37	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T147	7		T193	9		T188	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T223	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T14	5		T239	1		T375	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	5		T180	12		T139	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T191	1		T315	1		T331	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T4	16		T12	2		T45	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T11	1		T147	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T149	16		T151	13		T146	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	2		T49	12		T144	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	13		T158	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T46	12		T48	12		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	1		T49	7		T148	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	16		T60	10		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	4		T141	11		T142	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	7		T10	1		T60	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T45	12		T266	1		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T38	1		T48	11		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	10		T47	11		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T61	4		T24	1		T271	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	17		T158	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T148	10		T167	5		T282	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16472	1			T3	20		T5	20		T6	130
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T154	7		T279	1		T305	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T376	12		T246	13		T320	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T223	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T14	2		T239	14		T375	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T180	10		T139	9		T152	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T331	10		T290	14		T339	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T12	15		T45	3		T173	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T263	15		T152	11		T160	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	14		T151	15		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T144	12		T183	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T181	9		T155	9		T208	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	11		T60	7		T208	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	7		T148	11		T290	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T60	11		T154	11		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	11		T141	7		T140	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T60	8		T270	8		T182	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	12		T143	11		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T269	8		T282	11		T317	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	10		T154	16		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T61	13		T271	7		T237	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	21		T183	4		T303	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T148	7		T282	14		T238	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	1		T48	1		T143	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T11	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T4	1		T12	17		T45	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T263	16		T152	12		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T149	15		T151	16		T146	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T6	3		T46	12		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	1		T158	1		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T48	1		T60	20		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T9	12		T11	8		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T154	12		T182	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T45	13		T142	2		T140	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	1		T10	1		T60	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T266	1		T154	17		T144	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T38	1		T48	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	11		T47	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T167	1		T24	1		T271	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T9	23		T150	1		T154	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T147	1		T148	8		T282	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T251	3		T373	1		T171	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T193	1		T188	1		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17017	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T191	1		T14	5		T239	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	4		T48	12		T143	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T147	14		T294	4		T331	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T4	15		T45	18		T49	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T152	2		T193	11		T160	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T149	15		T151	12		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T46	11		T49	11		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	12		T148	12		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T48	11		T60	9		T166	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	3		T49	6		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	15		T182	12		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	11		T142	14		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	6		T60	4		T270	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T144	15		T279	10		T299	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	10		T263	2		T61	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	9		T47	10		T159	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T167	4		T305	9		T313	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	15		T151	11		T303	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	6		T148	9		T282	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T251	4		T171	5		T22	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T193	8		T343	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T180	11		T139	13		T152	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T14	2		T242	6		T170	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	434	1			T6	5		T7	4		T37	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T147	1		T193	1		T188	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T223	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T14	5		T239	15		T375	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	1		T180	11		T139	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T191	1		T315	1		T331	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T4	1		T12	17		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T11	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T149	15		T151	16		T146	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	3		T49	1		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	1		T158	1		T181	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	12		T48	1		T60	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T11	8		T49	1		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T60	12		T154	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T9	12		T141	8		T142	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	1		T10	1		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T45	13		T266	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T38	1		T48	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	11		T47	1		T154	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T61	14		T24	1		T271	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T9	23		T158	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T148	8		T167	1		T282	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16580	1			T3	20		T5	20		T6	130
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T305	14		T251	4		T281	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T147	6		T193	8		T246	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T223	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T14	2		T353	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	4		T180	11		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T331	11		T290	14		T339	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T4	15		T45	18		T48	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T147	14		T152	2		T160	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T149	15		T151	12		T146	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	11		T144	13		T193	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	12		T155	10		T208	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T46	11		T48	11		T166	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	6		T148	12		T157	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	15		T60	9		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	3		T141	10		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	6		T60	4		T270	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T45	11		T143	14		T144	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	10		T263	2		T183	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T10	9		T47	10		T159	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T61	3		T305	9		T313	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	15		T151	11		T183	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T148	9		T167	4		T282	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31