Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T9	11		T158	2		T61	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T49	1		T149	15		T270	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	8		T150	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1270	1			T4	1		T9	12		T12	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T263	16		T142	2		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T60	12		T263	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T152	3		T159	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	1		T147	1		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T8	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	1		T48	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T273	11		T290	4		T291	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	8		T141	8		T139	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T46	12		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T49	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	1		T48	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	1		T181	10		T155	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	12		T10	11		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T6	3		T8	1		T45	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T38	1		T60	8		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T191	1		T250	1		T194	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16965	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T292	3		T293	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	4		T61	3		T140	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T49	6		T149	15		T270	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T151	11		T208	10		T160	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1244	1			T4	15		T9	3		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T142	14		T159	7		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T60	9		T263	2		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T152	4		T159	2		T183	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T47	10		T147	14		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	4		T166	8		T144	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	12		T167	4		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T273	2		T290	2		T295	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T148	9		T141	10		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	6		T46	11		T193	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	11		T147	6		T180	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	12		T48	10		T282	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	11		T155	10		T296	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	11		T10	9		T49	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	15		T45	18		T148	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T301	2		T302	11		T214	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T194	4		T298	2		T198	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T292	6		T293	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T287	1		T288	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T289	1		T268	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T156	1		T24	1		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	11		T158	1		T152	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T45	13		T149	15		T270	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	8		T158	1		T61	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	12		T49	1		T144	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T263	16		T142	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T60	21		T263	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T142	1		T152	3		T159	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T47	1		T265	4		T35	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T181	1		T265	10		T35	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	1		T48	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T8	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T148	8		T139	10		T269	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	1		T46	12		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T147	1		T141	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T8	1		T10	11		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T49	1		T180	11		T155	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T9	12		T38	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1489	1			T4	1		T6	3		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T289	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T17	1		T276	7		T292	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	4		T152	2		T182	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	11		T149	15		T270	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T61	3		T140	13		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	3		T49	6		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T142	3		T208	10		T160	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T60	13		T263	2		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T142	11		T152	4		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T47	10		T265	10		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T265	10		T187	3		T281	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	12		T147	14		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	4		T166	8		T144	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T148	9		T139	13		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	6		T46	11		T193	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T147	6		T141	10		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T8	12		T10	9		T185	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T49	11		T180	11		T155	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	11		T48	10		T49	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1460	1			T4	15		T8	15		T45	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31