Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22222

1

T1

1

T3

20

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3871

1

T2

7

T6

3

T8

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20238

1

T3

20

T5

20

T6

135

auto[1]

5855

1

T1

1

T2

7

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T22	1		-	-		-	-
values[0]	61	1			T1	1		T141	18		T239	15
values[1]	675	1			T6	3		T9	15		T10	1
values[2]	657	1			T11	8		T38	1		T60	13
values[3]	721	1			T8	16		T10	20		T48	13
values[4]	2851	1			T4	16		T12	17		T153	3
values[5]	996	1			T2	7		T9	38		T45	24
values[6]	639	1			T8	5		T11	1		T48	11
values[7]	656	1			T180	22		T266	1		T269	9
values[8]	540	1			T45	22		T147	22		T158	1
values[9]	1332	1			T8	13		T46	23		T48	12
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	834	1			T1	1		T6	3		T9	15
values[1]	774	1			T8	16		T48	13		T49	7
values[2]	673	1			T10	20		T148	24		T140	30
values[3]	2933	1			T2	7		T4	16		T9	15
values[4]	914	1			T9	23		T45	24		T60	21
values[5]	606	1			T8	5		T11	1		T48	11
values[6]	670	1			T180	22		T158	1		T266	1
values[7]	677	1			T45	22		T147	22		T148	17
values[8]	844	1			T46	23		T48	12		T49	10
values[9]	189	1			T8	13		T142	16		T150	2
minimum	16979	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T9	5		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	2		T49	12		T141	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	13		T49	7		T60	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	16		T61	4		T151	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T155	11		T187	4		T303	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	10		T148	13		T140	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T4	16		T9	4		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	7		T158	1		T263	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	12		T60	10		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T45	12		T166	9		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	5		T48	11		T269	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T191	1		T152	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T266	1		T282	10		T299	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T180	12		T158	1		T152	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T45	19		T193	9		T167	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T147	22		T148	10		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T49	10		T261	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T46	12		T48	12		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T8	13		T142	12		T159	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T142	4		T150	2		T304	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T261	8		T268	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	10		T11	7		T271	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	1		T141	7		T146	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T60	8		T35	13		T305	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T61	13		T151	15		T144	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T155	9		T303	7		T305	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	10		T148	11		T140	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T9	11		T12	15		T60	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T151	13		T144	11		T183	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	11		T60	11		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	12		T272	12		T279	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T269	8		T270	8		T143	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T152	2		T155	8		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T282	14		T299	7		T237	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T180	10		T152	11		T265	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T45	3		T146	13		T290	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T148	7		T263	15		T154	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T261	10		T154	7		T35	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T46	11		T181	9		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T160	1		T294	6		T251	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T304	1		T276	10		T306	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T261	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T22	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T1	1		T239	1		T307	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T141	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	5		T10	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	2		T49	12		T261	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T38	1		T60	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T61	4		T151	13		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	13		T49	7		T183	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	16		T10	10		T148	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T4	16		T12	2		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T263	3		T151	15		T144	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	16		T60	10		T139	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	7		T45	12		T166	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	5		T48	11		T149	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T152	5		T155	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T266	1		T269	1		T151	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T180	12		T191	1		T152	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	19		T308	17		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T147	22		T158	1		T148	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T8	13		T49	10		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T46	12		T48	12		T142	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T239	14		T307	9		T309	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T141	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	10		T271	7		T284	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	1		T261	6		T299	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	7		T60	8		T35	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T61	13		T151	15		T183	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T303	7		T305	15		T246	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	10		T148	11		T140	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	882	1			T12	15		T60	7		T173	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T151	13		T144	12		T208	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	22		T60	11		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	12		T183	4		T279	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T149	14		T143	6		T290	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T152	2		T155	8		T272	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T269	8		T282	14		T283	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T180	10		T152	11		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T45	3		T187	1		T237	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T148	7		T263	15		T154	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T261	10		T154	7		T160	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T46	11		T154	11		T181	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	1		T9	11		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	3		T49	1		T141	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	1		T49	1		T60	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	1		T61	14		T151	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T155	10		T187	1		T303	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T10	11		T148	12		T140	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T4	1		T9	12		T12	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T158	1		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T9	12		T60	12		T139	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	13		T166	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	1		T48	1		T269	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T191	1		T152	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T266	1		T282	15		T299	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T180	11		T158	1		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T45	4		T193	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T147	2		T148	8		T263	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T49	1		T261	11		T154	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T46	12		T48	1		T181	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T8	1		T142	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T142	1		T150	2		T304	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	7		T268	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	4		T284	13		T310	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T49	11		T141	10		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	12		T49	6		T60	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	15		T61	3		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T155	10		T187	3		T303	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	9		T148	12		T140	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T4	15		T9	3		T47	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	6		T263	2		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	11		T60	9		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T45	11		T166	8		T157	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	4		T48	10		T270	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T152	4		T155	10		T208	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T282	9		T299	5		T242	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T180	11		T152	2		T265	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	18		T193	8		T167	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T147	20		T148	9		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	9		T261	9		T35	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T46	11		T48	11		T143	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T8	12		T142	11		T159	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T142	3		T304	1		T276	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T261	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T22	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T1	1		T239	15		T307	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T141	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	11		T10	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	3		T49	1		T261	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	8		T38	1		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T61	14		T151	16		T183	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T48	1		T49	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T8	1		T10	11		T148	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T4	1		T12	17		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T263	1		T151	14		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T9	24		T60	12		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T45	13		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T48	1		T149	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T152	3		T155	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T266	1		T269	9		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T180	11		T191	1		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T45	4		T308	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T147	2		T158	1		T148	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T8	1		T49	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T46	12		T48	1		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T307	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T141	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	4		T311	2		T284	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T49	11		T261	7		T299	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T60	4		T312	9		T313	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T61	3		T151	12		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	12		T49	6		T183	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	15		T10	9		T148	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T4	15		T47	10		T314	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T263	2		T151	14		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	14		T60	9		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	6		T45	11		T166	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	4		T48	10		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T152	4		T155	10		T157	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T151	11		T167	16		T282	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T180	11		T152	2		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T45	18		T308	16		T281	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T147	20		T148	9		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T8	12		T49	9		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T46	11		T48	11		T142	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31