Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22342

1

T1

1

T3

20

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3751

1

T2

7

T6

3

T8

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20067

1

T2

7

T3

20

T5

20

auto[1]

6026

1

T1

1

T4

16

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T146	27		-	-		-	-
values[0]	22	1			T168	18		T250	1		T172	1
values[1]	781	1			T1	1		T10	1		T49	10
values[2]	808	1			T8	29		T158	1		T148	17
values[3]	593	1			T48	12		T60	13		T266	1
values[4]	871	1			T2	7		T9	23		T11	8
values[5]	550	1			T8	5		T10	20		T45	22
values[6]	701	1			T6	3		T9	15		T45	24
values[7]	697	1			T47	11		T147	15		T154	8
values[8]	676	1			T38	1		T49	12		T180	22
values[9]	3403	1			T4	16		T9	15		T11	1
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	968	1			T1	1		T10	1		T49	10
values[1]	701	1			T8	13		T158	1		T148	17
values[2]	694	1			T8	16		T166	9		T61	17
values[3]	652	1			T2	7		T11	8		T48	12
values[4]	685	1			T6	3		T8	5		T9	38
values[5]	721	1			T45	24		T154	8		T155	19
values[6]	2976	1			T4	16		T12	17		T38	1
values[7]	539	1			T48	11		T147	7		T180	22
values[8]	933	1			T9	15		T46	23		T49	7
values[9]	204	1			T11	1		T148	24		T139	1
minimum	17020	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	1		T10	1		T142	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T49	10		T151	12		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T148	10		T261	10		T146	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	13		T158	1		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T166	9		T61	4		T152	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	16		T266	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	1		T48	12		T60	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	7		T150	1		T191	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	5		T9	16		T10	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	2		T48	13		T142	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	12		T154	1		T156	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T155	11		T145	1		T157	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T4	16		T12	2		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T143	15		T315	1		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T48	11		T147	7		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T180	12		T151	13		T144	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	5		T49	7		T141	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T46	12		T60	10		T263	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T148	13		T265	11		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T11	1		T139	1		T159	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16876	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T313	6		T316	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T269	8		T154	16		T208	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	1		T273	12		T40	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T148	7		T261	10		T146	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T263	15		T154	11		T160	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T61	13		T152	11		T183	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T35	13		T28	1		T317	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	7		T60	15		T265	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T251	2		T242	11		T318	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	22		T10	10		T45	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	1		T155	9		T209	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T45	12		T154	7		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T155	8		T145	11		T319	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T12	15		T173	4		T280	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T143	11		T283	2		T237	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T149	14		T320	16		T321	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T180	10		T151	15		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	10		T141	7		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T46	11		T60	11		T261	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T148	11		T265	3		T320	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T317	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T313	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T146	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T250	1		T172	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T168	10		T322	1		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T10	1		T142	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T49	10		T151	12		T35	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T148	10		T269	1		T261	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	29		T158	1		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	12		T60	5		T152	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T266	1		T154	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	12		T11	1		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	7		T150	1		T155	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	5		T10	10		T45	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T48	13		T191	2		T193	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	4		T45	12		T270	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T6	2		T142	4		T155	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T47	11		T147	15		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T144	14		T315	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	1		T49	12		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T180	12		T143	15		T208	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1708	1			T4	16		T9	5		T12	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T11	1		T46	12		T60	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T146	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T168	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T154	16		T208	9		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	1		T273	12		T290	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T148	7		T269	8		T261	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T263	15		T40	2		T290	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T60	8		T152	11		T183	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T154	11		T160	1		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	11		T11	7		T60	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T155	9		T35	13		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	10		T45	3		T181	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T187	1		T44	4		T171	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T9	11		T45	12		T270	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	1		T155	8		T209	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T154	7		T39	2		T29	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T144	12		T145	11		T194	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T139	9		T149	14		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T180	10		T143	11		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T9	10		T12	15		T173	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T46	11		T60	11		T261	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T1	1		T10	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	1		T151	1		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T148	8		T261	11		T146	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	1		T158	1		T263	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T166	1		T61	14		T152	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	1		T266	1		T35	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	8		T48	1		T60	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	1		T150	1		T191	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T9	24		T10	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	3		T48	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T45	13		T154	8		T156	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T155	9		T145	12		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T4	1		T12	17		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T143	12		T315	1		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T48	1		T147	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T180	11		T151	16		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	11		T49	1		T141	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T46	12		T60	12		T263	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T148	12		T265	4		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T11	1		T139	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16985	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T313	7		T316	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T142	11		T208	10		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T49	9		T151	11		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T148	9		T261	9		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	12		T36	1		T290	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T166	8		T61	3		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	15		T28	1		T317	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	11		T60	4		T265	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T2	6		T251	4		T242	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	4		T9	14		T10	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	12		T142	3		T193	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T45	11		T156	2		T29	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T155	10		T157	15		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T4	15		T47	10		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	14		T324	10		T212	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T48	10		T147	6		T149	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T180	11		T151	12		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	4		T49	6		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T46	11		T60	9		T263	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T148	12		T265	10		T320	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T159	7		T317	4		T325	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T326	6		T327	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T313	5		T316	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T146	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T250	1		T172	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T168	9		T322	1		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T10	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	1		T151	1		T35	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T148	8		T269	9		T261	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	2		T158	1		T263	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	1		T60	9		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T266	1		T154	12		T160	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T9	12		T11	8		T60	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	1		T150	1		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	1		T10	11		T45	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T48	1		T191	2		T193	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	12		T45	13		T270	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	3		T142	1		T155	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	1		T147	1		T154	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	13		T315	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	1		T49	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T180	11		T143	12		T208	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T4	1		T9	11		T12	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T11	1		T46	12		T60	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T146	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T168	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T142	11		T208	10		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T49	9		T151	11		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T148	9		T261	9		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	27		T40	1		T290	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T48	11		T60	4		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T36	1		T242	6		T110	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	11		T166	8		T61	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	6		T155	10		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	4		T10	9		T45	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T48	12		T193	11		T171	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T9	3		T45	11		T270	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T142	3		T155	10		T279	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T47	10		T147	14		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T144	13		T194	7		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	11		T139	13		T149	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T180	11		T143	14		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T4	15		T9	4		T48	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T46	11		T60	9		T263	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31