Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22377

1

T2

7

T3

20

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3716

1

T1

1

T8

13

T9

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20071

1

T2

7

T3

20

T5

20

auto[1]

6022

1

T1

1

T4

16

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T327	20		-	-		-	-
values[0]	29	1			T242	1		T304	3		T328	7
values[1]	596	1			T1	1		T45	46		T60	21
values[2]	2865	1			T4	16		T9	15		T11	1
values[3]	702	1			T6	3		T48	25		T140	30
values[4]	620	1			T10	20		T49	10		T60	8
values[5]	600	1			T8	5		T9	15		T61	17
values[6]	824	1			T2	7		T8	29		T11	8
values[7]	726	1			T10	1		T148	24		T142	4
values[8]	812	1			T38	1		T47	11		T49	7
values[9]	1335	1			T9	23		T46	23		T49	12
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	806	1			T1	1		T11	1		T45	24
values[1]	2835	1			T4	16		T9	15		T12	17
values[2]	723	1			T6	3		T10	20		T48	25
values[3]	583	1			T60	8		T158	1		T142	12
values[4]	697	1			T8	21		T9	15		T11	8
values[5]	760	1			T2	7		T8	13		T48	11
values[6]	816	1			T10	1		T49	7		T148	41
values[7]	788	1			T38	1		T47	11		T60	13
values[8]	885	1			T9	23		T46	23		T49	12
values[9]	214	1			T166	9		T158	1		T151	28
minimum	16986	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T11	1		T60	10		T151	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T45	12		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T4	16		T12	2		T153	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	5		T139	1		T140	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	2		T10	10		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T48	13		T49	10		T29	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T61	4		T183	13		T273	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T60	1		T158	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	21		T9	4		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T150	1		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	7		T48	11		T147	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	13		T156	3		T301	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T141	11		T151	12		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	1		T49	7		T148	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T60	5		T142	4		T193	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T38	1		T47	11		T147	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	12		T158	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	12		T46	12		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T158	1		T151	15		T90	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T166	9		T35	1		T88	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T45	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T60	11		T151	15		T208	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	12		T263	15		T261	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T12	15		T173	4		T280	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	10		T140	16		T183	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	1		T10	10		T144	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T29	2		T299	7		T284	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T61	13		T183	4		T273	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T60	7		T152	2		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	11		T155	9		T271	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	7		T181	9		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T144	11		T155	8		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T156	2		T281	9		T329	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T141	7		T187	1		T168	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T148	18		T139	9		T270	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T60	8		T35	1		T283	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T180	10		T149	14		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T282	11		T238	1		T305	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	11		T46	11		T269	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T151	13		T90	12		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T35	13		T307	9		T327	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T45	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T327	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T304	2		T328	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T242	1		T330	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T60	10		T151	13		T208	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	1		T45	31		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T4	16		T11	1		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	5		T139	1		T167	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	2		T48	12		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	13		T140	14		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	10		T144	6		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T49	10		T60	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	5		T9	4		T61	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T181	1		T265	11		T272	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	7		T8	16		T48	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	13		T11	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T142	4		T151	12		T193	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	1		T148	13		T270	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	5		T141	11		T159	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T38	1		T47	11		T49	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T49	12		T158	2		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T9	12		T46	12		T166	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T327	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T304	1		T328	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T60	11		T151	15		T208	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T45	15		T263	15		T261	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T12	15		T173	4		T280	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	10		T183	1		T146	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T146	13		T278	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T140	16		T29	2		T299	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	10		T144	3		T331	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T60	7		T152	2		T208	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	11		T61	13		T183	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T181	9		T265	9		T272	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T144	11		T155	9		T35	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	7		T152	11		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	8		T168	8		T242	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T148	11		T270	8		T154	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T60	8		T141	7		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T148	7		T139	9		T154	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T151	13		T282	11		T305	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	11		T46	11		T180	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	1		T60	12		T151	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T45	13		T263	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T4	1		T12	17		T153	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	11		T139	1		T140	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	3		T10	11		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	1		T49	1		T29	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T61	14		T183	5		T273	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T60	8		T158	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	2		T9	12		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	8		T150	1		T181	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	1		T48	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T156	3		T301	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T141	8		T151	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T10	1		T49	1		T148	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T60	9		T142	1		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T38	1		T47	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T49	1		T158	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	12		T46	12		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T158	1		T151	14		T90	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T166	1		T35	14		T88	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T45	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T60	9		T151	12		T208	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	11		T261	16		T279	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T4	15		T263	2		T314	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	4		T140	13		T167	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	9		T48	11		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	12		T49	9		T29	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T61	3		T183	12		T273	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T142	11		T152	4		T208	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	19		T9	3		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T152	2		T265	10		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	6		T48	10		T147	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	12		T156	2		T301	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T141	10		T151	11		T311	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T49	6		T148	21		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T60	4		T142	3		T193	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T47	10		T147	6		T180	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	11		T282	9		T305	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	11		T46	11		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T151	14		T90	20		T286	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T166	8		T90	6		T307	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T45	18		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T327	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T304	2		T328	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T242	1		T330	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T60	12		T151	16		T208	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	1		T45	17		T263	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T4	1		T11	1		T12	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	11		T139	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	3		T48	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	1		T140	17		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	11		T144	4		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T49	1		T60	8		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	1		T9	12		T61	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T181	10		T265	10		T272	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	1		T8	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	1		T11	8		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T142	1		T151	1		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	1		T148	12		T270	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T60	9		T141	8		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T38	1		T47	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	436	1			T49	1		T158	2		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T9	12		T46	12		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T327	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T304	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T330	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T60	9		T151	12		T208	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T45	29		T261	16		T279	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T4	15		T263	2		T314	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	4		T167	16		T146	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	11		T193	8		T146	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	12		T140	13		T29	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	9		T144	5		T331	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	9		T142	11		T152	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T8	4		T9	3		T61	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T265	10		T28	1		T303	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	6		T8	15		T48	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	12		T152	2		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T142	3		T151	11		T193	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T148	12		T270	9		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T60	4		T141	10		T159	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T47	10		T49	6		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T49	11		T151	14		T282	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T9	11		T46	11		T166	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31