Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22225

1

T1

1

T2

7

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3868

1

T8

18

T9

53

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20006

1

T2

7

T3

20

T5

20

auto[1]

6087

1

T1

1

T4

16

T8

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T332	25		T333	10		T334	1
values[0]	89	1			T193	12		T210	1		T239	15
values[1]	628	1			T60	13		T154	20		T167	5
values[2]	746	1			T8	5		T60	21		T166	9
values[3]	687	1			T2	7		T263	3		T150	1
values[4]	587	1			T49	7		T60	8		T158	1
values[5]	570	1			T8	16		T11	8		T45	22
values[6]	828	1			T38	1		T48	12		T49	22
values[7]	772	1			T9	15		T48	13		T269	9
values[8]	2868	1			T4	16		T9	23		T10	21
values[9]	1318	1			T1	1		T6	3		T8	13
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	924	1			T60	21		T154	20		T191	1
values[1]	689	1			T8	5		T60	13		T166	9
values[2]	702	1			T2	7		T263	3		T150	1
values[3]	521	1			T47	11		T49	7		T60	8
values[4]	642	1			T8	16		T11	8		T45	22
values[5]	756	1			T9	15		T38	1		T48	25
values[6]	3015	1			T4	16		T9	23		T10	20
values[7]	596	1			T10	1		T261	14		T144	27
values[8]	1083	1			T1	1		T6	3		T8	13
values[9]	185	1			T181	1		T152	14		T143	26
minimum	16980	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T60	10		T154	1		T159	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T154	1		T191	1		T151	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T60	5		T147	15		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	5		T166	9		T180	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	7		T188	1		T301	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T263	3		T150	1		T265	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T60	1		T158	1		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T47	11		T49	7		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	16		T45	19		T46	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T49	12		T167	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T38	1		T49	10		T148	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	4		T48	25		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T4	16		T10	10		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	12		T269	1		T270	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T261	8		T156	4		T294	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	1		T144	16		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T6	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T8	13		T9	5		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T181	1		T24	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T152	3		T143	15		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T335	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	11		T154	11		T239	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T154	7		T151	13		T183	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T60	8		T61	13		T208	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T180	10		T143	6		T265	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T305	3		T242	11		T336	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T265	9		T160	14		T279	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T60	7		T144	3		T183	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T263	15		T141	7		T261	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T45	3		T46	11		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	7		T35	13		T273	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T148	11		T151	15		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	11		T154	16		T279	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T10	10		T12	15		T45	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	11		T269	8		T270	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T261	6		T156	2		T294	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T144	11		T35	1		T246	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T139	9		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	10		T148	7		T160	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T299	9		T170	3		T333	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T152	11		T143	11		T294	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T335	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T332	12		T333	1		T334	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T239	1		T337	5		T338	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T193	12		T210	1		T339	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T60	5		T154	1		T159	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T154	1		T167	5		T183	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T60	10		T147	15		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	5		T166	9		T180	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	7		T208	8		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T263	3		T150	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T60	1		T158	1		T28	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T49	7		T263	1		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	16		T45	19		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	1		T47	11		T167	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T38	1		T49	10		T148	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T48	12		T49	12		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	14		T144	14		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T9	4		T48	13		T269	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T4	16		T10	10		T12	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	12		T10	1		T144	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T1	1		T6	2		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	426	1			T8	13		T9	5		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T332	13		T333	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T239	14		T338	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T339	13		T213	2		T323	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T60	8		T154	11		T251	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T154	7		T183	4		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T60	11		T61	13		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T180	10		T151	13		T143	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T208	7		T303	21		T305	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T181	9		T265	9		T272	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T60	7		T28	1		T290	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T263	15		T141	7		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T45	3		T46	11		T144	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	7		T35	13		T273	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T148	11		T149	14		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T154	16		T279	10		T29	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T140	16		T144	12		T282	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	11		T269	8		T270	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T10	10		T12	15		T45	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	11		T144	11		T182	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	1		T139	9		T261	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T9	10		T148	7		T152	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T60	12		T154	12		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T154	8		T191	1		T151	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T60	9		T147	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	1		T166	1		T180	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T188	1		T301	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T263	1		T150	1		T265	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T60	8		T158	1		T144	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T47	1		T49	1		T263	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T45	4		T46	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	8		T49	1		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	1		T49	1		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	12		T48	2		T154	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T4	1		T10	11		T12	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	12		T269	9		T270	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T261	7		T156	4		T294	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	1		T144	12		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T6	3		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T8	1		T9	11		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T181	1		T24	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T152	12		T143	12		T294	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T335	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T60	9		T159	2		T251	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T151	14		T193	11		T167	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T60	4		T147	14		T61	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	4		T166	8		T180	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	6		T301	7		T305	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T263	2		T265	10		T160	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T144	5		T28	1		T290	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T47	10		T49	6		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	15		T45	18		T46	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T49	11		T167	16		T273	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T49	9		T148	12		T151	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	3		T48	23		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T4	15		T10	9		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	11		T270	9		T182	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T261	7		T156	2		T294	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T144	15		T35	1		T308	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T139	13		T146	13		T278	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T8	12		T9	4		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T299	8		T170	7		T199	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T152	2		T143	14		T307	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T335	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T332	14		T333	10		T334	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T239	15		T337	1		T338	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T193	1		T210	1		T339	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T60	9		T154	12		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T154	8		T167	1		T183	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T60	12		T147	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T166	1		T180	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T208	8		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T263	1		T150	1		T181	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T60	8		T158	1		T28	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	1		T263	16		T141	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	1		T45	4		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	8		T47	1		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	1		T49	1		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T48	1		T49	1		T154	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T140	17		T144	13		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	12		T48	1		T269	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T4	1		T10	11		T12	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	12		T10	1		T144	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T1	1		T6	3		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T8	1		T9	11		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T332	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T337	4		T216	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T193	11		T339	11		T213	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T60	4		T159	2		T251	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T167	4		T183	12		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T60	9		T147	14		T61	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	4		T166	8		T180	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	6		T208	7		T303	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T263	2		T265	10		T311	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T28	1		T290	16		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T49	6		T141	10		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	15		T45	18		T46	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T47	10		T167	16		T273	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	9		T148	12		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T48	11		T49	11		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T140	13		T144	13		T282	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	3		T48	12		T270	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T4	15		T10	9		T45	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	11		T144	15		T182	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T139	13		T261	7		T146	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T8	12		T9	4		T148	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31