Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22453

1

T1

1

T2

7

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3640

1

T8

34

T9

23

T10

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20249

1

T1

1

T2

7

T3

20

auto[1]

5844

1

T4

16

T9

38

T11

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	325	1			T45	22		T142	4		T61	17
values[0]	68	1			T188	1		T302	24		T18	1
values[1]	802	1			T6	3		T9	30		T10	20
values[2]	509	1			T8	29		T11	1		T154	12
values[3]	730	1			T8	5		T46	23		T47	11
values[4]	652	1			T48	13		T261	20		T151	28
values[5]	2944	1			T1	1		T4	16		T10	1
values[6]	688	1			T2	7		T9	23		T11	8
values[7]	826	1			T48	11		T60	8		T147	7
values[8]	641	1			T48	12		T49	7		T142	12
values[9]	944	1			T45	24		T49	22		T158	1
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	674	1			T147	15		T148	17		T181	1
values[1]	541	1			T8	29		T11	1		T47	11
values[2]	718	1			T8	5		T46	23		T158	1
values[3]	2923	1			T4	16		T10	1		T12	17
values[4]	593	1			T1	1		T9	23		T60	13
values[5]	889	1			T2	7		T11	8		T60	21
values[6]	610	1			T48	11		T60	8		T139	1
values[7]	716	1			T48	12		T49	17		T158	1
values[8]	1045	1			T45	46		T49	12		T142	4
values[9]	64	1			T160	2		T340	1		T341	5
minimum	17320	1			T3	20		T5	20		T6	138

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T147	15		T148	10		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T208	11		T183	1		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T150	1		T154	1		T152	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T8	29		T11	1		T47	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T261	10		T143	15		T272	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	5		T46	12		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T4	16		T12	2		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	1		T48	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	1		T263	4		T183	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	12		T60	5		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	7		T11	1		T149	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T60	10		T147	7		T180	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T269	1		T193	12		T208	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	11		T60	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T49	10		T158	1		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	12		T49	7		T142	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T45	19		T49	12		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T45	12		T142	4		T61	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T160	1		T340	1		T341	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16923	1			T3	20		T5	20		T6	137
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T10	10		T38	1		T166	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T148	7		T182	10		T290	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T208	9		T183	1		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T154	11		T152	2		T155	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T281	9		T342	7		T194	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T261	10		T143	11		T272	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	11		T144	3		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T12	15		T173	4		T280	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T152	11		T143	6		T209	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T263	15		T283	2		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	11		T60	8		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	7		T149	14		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T60	11		T180	10		T148	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T269	8		T208	7		T251	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	7		T185	11		T296	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T181	9		T187	16		T317	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T144	11		T273	12		T271	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	3		T265	9		T146	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	12		T61	13		T140	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T160	1		T341	4		T343	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	1		T9	21		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	10		T141	7		T294	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T45	19		T32	16		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T142	4		T61	4		T301	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T188	1		T18	1		T199	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T302	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	2		T9	9		T147	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	10		T38	1		T166	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T154	1		T315	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	29		T11	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T150	1		T152	5		T143	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	5		T46	12		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T261	10		T151	15		T315	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T48	13		T152	3		T143	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T1	1		T4	16		T12	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T10	1		T60	5		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	7		T11	1		T263	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	12		T60	10		T180	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T149	16		T269	1		T193	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T48	11		T60	1		T147	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T181	1		T191	1		T167	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	12		T49	7		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T49	22		T158	1		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T45	12		T140	14		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T45	3		T344	9		T212	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T61	13		T345	4		T316	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T286	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T302	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T9	21		T148	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	10		T141	7		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	11		T246	1		T346	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T183	1		T278	10		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T152	2		T143	11		T155	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T46	11		T144	3		T145	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T261	10		T151	13		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T152	11		T143	6		T209	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T12	15		T173	4		T263	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T60	8		T139	9		T265	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	7		T144	12		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	11		T60	11		T180	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T149	14		T269	8		T146	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T60	7		T261	6		T160	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T181	9		T208	7		T317	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T273	12		T185	11		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T265	9		T160	1		T146	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	12		T140	16		T154	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T147	1		T148	8		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T208	10		T183	2		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T150	1		T154	12		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	2		T11	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T261	11		T143	12		T272	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	1		T46	12		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T4	1		T12	17		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	1		T48	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	1		T263	17		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	12		T60	9		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T11	8		T149	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T60	12		T147	1		T180	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T269	9		T193	1		T208	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	1		T60	8		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	1		T158	1		T181	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	1		T49	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T45	4		T49	1		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T45	13		T142	1		T61	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T160	2		T340	1		T341	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17035	1			T3	20		T5	20		T6	138
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	11		T38	1		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T147	14		T148	9		T182	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T208	10		T35	1		T278	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T152	4		T155	10		T346	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T8	27		T47	10		T281	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T261	9		T143	14		T282	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	4		T46	11		T151	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T4	15		T314	14		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	12		T152	2		T143	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T263	2		T183	2		T289	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	11		T60	4		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	6		T149	15		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T60	9		T147	6		T180	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T193	11		T208	7		T251	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T48	10		T185	13		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	9		T167	4		T279	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	11		T49	6		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T45	18		T49	11		T265	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	11		T142	3		T61	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T343	2		T347	10		T348	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T9	7		T199	6		T200	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T10	9		T166	8		T141	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T45	4		T32	1		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T142	1		T61	14		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T188	1		T18	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T302	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	3		T9	23		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	11		T38	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T154	12		T315	1		T246	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	2		T11	1		T183	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T150	1		T152	3		T143	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	1		T46	12		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T261	11		T151	14		T315	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	1		T152	12		T143	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T1	1		T4	1		T12	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	1		T60	9		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	1		T11	8		T263	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	12		T60	12		T180	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T149	15		T269	9		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T48	1		T60	8		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T181	10		T191	1		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	1		T49	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T49	2		T158	1		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T45	13		T140	17		T154	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T45	18		T32	15		T344	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T142	3		T61	3		T301	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T199	6		T286	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T302	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	7		T147	14		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	9		T166	8		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T346	6		T90	6		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	27		T278	7		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	4		T143	14		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	4		T46	11		T47	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T261	9		T151	14		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	12		T152	2		T143	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T4	15		T314	14		T349	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T60	4		T139	13		T193	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	6		T263	2		T144	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	11		T60	9		T180	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T149	15		T193	11		T146	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	10		T147	6		T261	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T167	4		T208	7		T317	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	11		T49	6		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T49	20		T265	10		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T45	11		T140	13		T144	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31