Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22496

1

T1

1

T3

20

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3597

1

T2

7

T6

3

T8

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20061

1

T2

7

T3

20

T5

20

auto[1]

6032

1

T1

1

T4

16

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	313	1			T60	21		T151	28		T152	7
values[0]	4	1			T172	1		T322	1		T302	1
values[1]	809	1			T1	1		T10	1		T49	10
values[2]	787	1			T8	29		T158	1		T148	17
values[3]	630	1			T48	12		T266	1		T152	14
values[4]	825	1			T2	7		T11	8		T60	21
values[5]	555	1			T6	3		T8	5		T9	23
values[6]	730	1			T9	15		T45	24		T142	4
values[7]	719	1			T47	11		T147	15		T143	26
values[8]	611	1			T38	1		T48	11		T49	12
values[9]	3146	1			T4	16		T9	15		T11	1
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	714	1			T10	1		T49	10		T263	16
values[1]	714	1			T8	29		T158	1		T148	17
values[2]	625	1			T48	12		T60	8		T166	9
values[3]	717	1			T2	7		T9	23		T11	8
values[4]	663	1			T6	3		T8	5		T10	20
values[5]	732	1			T9	15		T45	24		T270	18
values[6]	2984	1			T4	16		T12	17		T38	1
values[7]	489	1			T48	11		T147	7		T180	22
values[8]	973	1			T9	15		T46	23		T49	7
values[9]	183	1			T11	1		T148	24		T265	14
minimum	17299	1			T1	1		T3	20		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T142	12		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T49	10		T263	1		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T148	10		T261	10		T146	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	29		T158	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	12		T60	1		T61	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T166	9		T266	1		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	12		T11	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	7		T60	5		T191	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	5		T10	10		T45	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	2		T48	13		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	4		T45	12		T270	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T155	11		T145	1		T157	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T4	16		T12	2		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T143	15		T144	14		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	11		T147	7		T180	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T151	13		T182	13		T208	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T9	5		T49	7		T141	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T46	12		T60	10		T263	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T148	13		T265	11		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T11	1		T159	8		T317	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T1	1		T3	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T151	12		T273	11		T299	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T269	8		T208	9		T278	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T263	15		T35	1		T40	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T148	7		T261	10		T146	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T154	11		T160	1		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T60	7		T61	13		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T28	1		T317	12		T242	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	11		T11	7		T265	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T60	8		T35	13		T251	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	10		T45	3		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	1		T181	9		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	11		T45	12		T270	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T155	8		T145	11		T319	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T12	15		T173	4		T280	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T143	11		T144	12		T183	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T180	10		T149	14		T170	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T151	15		T182	10		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	10		T141	7		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	11		T60	11		T261	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T148	11		T265	3		T274	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T317	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T273	12		T299	9		T168	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T246	7		T320	13		T258	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T60	10		T151	15		T152	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T322	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T172	1		T302	1		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T10	1		T142	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T49	10		T151	12		T35	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T148	10		T269	1		T261	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	29		T158	1		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	12		T152	3		T167	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T266	1		T160	1		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T60	1		T61	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	7		T60	5		T166	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	5		T9	12		T10	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	2		T48	13		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	4		T45	12		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T155	11		T315	1		T279	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T47	11		T147	15		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T143	15		T144	14		T315	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T38	1		T48	11		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T208	8		T183	1		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T4	16		T9	5		T12	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T11	1		T46	12		T263	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T246	13		T320	2		T258	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T60	11		T151	13		T152	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T154	16		T208	9		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	1		T273	12		T299	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T148	7		T269	8		T261	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T263	15		T154	11		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	11		T183	4		T278	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T160	1		T36	1		T317	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	7		T60	7		T61	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T60	8		T155	9		T35	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	11		T10	10		T45	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	1		T181	9		T209	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	11		T45	12		T270	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T155	8		T319	10		T350	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	2		T29	2		T282	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T143	11		T144	12		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T180	10		T149	14		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T208	7		T183	1		T273	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T9	10		T12	15		T173	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	11		T261	6		T151	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T10	1		T142	1		T269	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	1		T263	16		T35	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T148	8		T261	11		T146	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	2		T158	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	1		T60	8		T61	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T166	1		T266	1		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	12		T11	8		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	1		T60	9		T191	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	1		T10	11		T45	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	3		T48	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	12		T45	13		T270	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T155	9		T145	12		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T4	1		T12	17		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T143	12		T144	13		T183	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	1		T147	1		T180	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T151	16		T182	11		T208	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	11		T49	1		T141	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T46	12		T60	12		T263	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T148	12		T265	4		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T11	1		T159	1		T317	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17056	1			T1	1		T3	20		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T151	1		T273	13		T299	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T142	11		T208	10		T278	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T49	9		T35	1		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T148	9		T261	9		T146	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	27		T36	1		T290	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T48	11		T61	3		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T166	8		T28	1		T317	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T9	11		T265	10		T311	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	6		T60	4		T251	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	4		T10	9		T45	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	12		T193	11		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	3		T45	11		T270	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T155	10		T157	15		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T4	15		T47	10		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T143	14		T144	13		T194	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T48	10		T147	6		T180	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T151	12		T182	12		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	4		T49	6		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T46	11		T60	9		T263	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T148	12		T265	10		T274	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T159	7		T317	4		T351	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T35	3		T352	7		T326	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T151	11		T273	10		T299	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T246	14		T320	3		T258	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T60	12		T151	14		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T322	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T172	1		T302	1		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	1		T10	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T49	1		T151	1		T35	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T148	8		T269	9		T261	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	2		T158	1		T263	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	1		T152	12		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T266	1		T160	2		T36	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	8		T60	8		T61	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	1		T60	9		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	1		T9	12		T10	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	3		T48	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	12		T45	13		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T155	9		T315	1		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T47	1		T147	1		T39	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T143	12		T144	13		T315	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	1		T48	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T208	8		T183	2		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T4	1		T9	11		T12	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	1		T46	12		T263	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T246	6		T320	12		T353	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T60	9		T151	14		T152	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T142	11		T208	10		T35	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	9		T151	11		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T148	9		T261	9		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	27		T40	1		T290	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	11		T152	2		T167	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T36	1		T317	12		T242	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T61	3		T265	10		T282	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	6		T60	4		T166	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	4		T9	11		T10	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	12		T193	11		T171	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	3		T45	11		T142	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T155	10		T279	11		T157	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	10		T147	14		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	14		T144	13		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	10		T49	11		T180	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T208	7		T273	2		T301	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T4	15		T9	4		T49	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	11		T263	2		T261	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31