Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22195

1

T1

1

T2

7

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3898

1

T8

13

T9

53

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19941

1

T2

7

T3

20

T5

20

auto[1]

6152

1

T1

1

T4

16

T8

34

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	356	1			T1	1		T8	13		T9	15
values[0]	28	1			T239	15		T338	3		T216	10
values[1]	660	1			T154	20		T193	12		T167	5
values[2]	797	1			T8	5		T60	34		T166	9
values[3]	603	1			T2	7		T263	3		T150	1
values[4]	658	1			T49	7		T60	8		T158	1
values[5]	555	1			T8	16		T11	8		T45	22
values[6]	845	1			T9	15		T38	1		T48	12
values[7]	722	1			T48	13		T269	9		T140	30
values[8]	2874	1			T4	16		T9	23		T10	21
values[9]	1031	1			T6	3		T158	1		T148	17
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	787	1			T60	21		T154	20		T191	1
values[1]	711	1			T8	5		T60	13		T166	9
values[2]	650	1			T2	7		T263	3		T150	1
values[3]	584	1			T47	11		T49	7		T60	8
values[4]	611	1			T8	16		T11	8		T45	22
values[5]	784	1			T9	15		T38	1		T48	25
values[6]	3029	1			T4	16		T9	23		T10	20
values[7]	561	1			T10	1		T144	27		T156	6
values[8]	1126	1			T1	1		T6	3		T8	13
values[9]	154	1			T181	1		T152	14		T294	2
minimum	17096	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T60	10		T154	1		T159	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T154	1		T191	1		T151	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	5		T60	5		T147	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T166	9		T180	12		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	7		T188	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T263	3		T150	1		T193	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T60	1		T158	1		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	11		T49	7		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	16		T45	19		T46	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T167	17		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	1		T49	10		T148	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	4		T48	25		T49	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1624	1			T4	16		T10	10		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	12		T270	10		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T156	4		T294	5		T296	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	1		T144	16		T308	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	1		T6	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T8	13		T9	5		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T181	1		T299	9		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T152	3		T294	1		T221	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16865	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T193	12		T167	5		T146	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T60	11		T154	11		T339	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T154	7		T151	13		T183	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T60	8		T61	13		T208	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T180	10		T143	6		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T305	3		T242	11		T336	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T265	9		T160	14		T279	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T60	7		T144	3		T183	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T263	15		T141	7		T261	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T45	3		T46	11		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	7		T35	13		T271	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T148	11		T151	15		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	11		T269	8		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T10	10		T12	15		T45	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	11		T270	8		T182	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T156	2		T294	6		T296	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T144	11		T94	6		T194	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T139	9		T261	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T9	10		T148	7		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T299	9		T17	1		T333	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T152	11		T294	1		T221	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T146	13		T329	7		T336	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T1	1		T139	14		T181	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T8	13		T9	5		T11	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T239	1		T338	1		T216	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T154	1		T159	3		T339	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T154	1		T193	12		T167	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	5		T60	15		T147	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T166	9		T180	12		T191	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	7		T208	8		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T263	3		T150	1		T193	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T60	1		T158	1		T28	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T49	7		T263	1		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	16		T45	19		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	1		T47	11		T167	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	1		T49	10		T148	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T9	4		T48	12		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	14		T144	14		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T48	13		T269	1		T270	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T4	16		T10	10		T12	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	12		T10	1		T144	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	2		T158	1		T261	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T148	10		T142	4		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T139	9		T312	9		T17	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T9	10		T152	11		T160	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T239	14		T338	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T154	11		T339	13		T251	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T154	7		T183	4		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T60	19		T61	13		T185	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T180	10		T151	13		T143	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T208	7		T303	21		T305	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T237	4		T238	5		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T60	7		T28	1		T290	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T263	15		T141	7		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T45	3		T46	11		T144	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	7		T35	13		T299	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T148	11		T149	14		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	11		T154	16		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T140	16		T144	12		T282	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T269	8		T270	8		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T10	10		T12	15		T45	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	11		T144	11		T182	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T261	6		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T148	7		T143	11		T273	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T60	12		T154	12		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T154	8		T191	1		T151	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	1		T60	9		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T166	1		T180	11		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	1		T188	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T263	1		T150	1		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T60	8		T158	1		T144	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T47	1		T49	1		T263	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T8	1		T45	4		T46	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	8		T167	1		T35	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	1		T49	1		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T9	12		T48	2		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T4	1		T10	11		T12	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	12		T270	9		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T156	4		T294	7		T296	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T144	12		T308	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	1		T6	3		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T8	1		T9	11		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T181	1		T299	10		T291	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T152	12		T294	2		T221	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16994	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T193	1		T167	1		T146	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T60	9		T159	2		T339	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	14		T183	12		T281	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	4		T60	4		T147	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T166	8		T180	11		T143	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	6		T301	7		T305	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T263	2		T193	8		T265	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T144	5		T28	1		T290	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	10		T49	6		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	15		T45	18		T46	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T167	16		T299	5		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	9		T148	12		T151	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	3		T48	23		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T4	15		T10	9		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	11		T270	9		T182	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T156	2		T294	4		T296	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T144	15		T308	16		T94	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T139	13		T261	7		T146	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	12		T9	4		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T299	8		T17	1		T347	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T152	2		T221	12		T307	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T354	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T193	11		T167	4		T146	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T1	1		T139	10		T181	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T9	11		T11	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T239	15		T338	3		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T154	12		T159	1		T339	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T154	8		T193	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	1		T60	21		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T166	1		T180	11		T191	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T208	8		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T263	1		T150	1		T193	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T60	8		T158	1		T28	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T49	1		T263	16		T141	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T8	1		T45	4		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	8		T47	1		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	1		T49	1		T148	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	12		T48	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	17		T144	13		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	1		T269	9		T270	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T4	1		T10	11		T12	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	12		T10	1		T144	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	3		T158	1		T261	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T148	8		T142	1		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T139	13		T312	9		T17	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T8	12		T9	4		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T216	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T159	2		T339	11		T251	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T193	11		T167	4		T183	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	4		T60	13		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T166	8		T180	11		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T2	6		T208	7		T303	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T263	2		T193	8		T311	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T28	1		T290	16		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T49	6		T141	10		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	15		T45	18		T46	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T47	10		T167	16		T299	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	9		T148	12		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	3		T48	11		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T140	13		T144	13		T282	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	12		T270	9		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T4	15		T10	9		T45	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	11		T144	15		T182	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T261	7		T146	13		T278	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T148	9		T142	3		T143	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31