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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.24


Total test records in report: 920
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T795 /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4148035558 Jul 11 05:52:04 PM PDT 24 Jul 11 06:11:54 PM PDT 24 495557255166 ps
T796 /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3573952011 Jul 11 05:49:04 PM PDT 24 Jul 11 05:50:43 PM PDT 24 39416857020 ps
T23 /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2164246153 Jul 11 05:52:28 PM PDT 24 Jul 11 05:54:45 PM PDT 24 65066017197 ps
T797 /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1828314401 Jul 11 05:50:11 PM PDT 24 Jul 11 05:51:26 PM PDT 24 154940869958 ps
T798 /workspace/coverage/default/34.adc_ctrl_fsm_reset.4155074987 Jul 11 05:50:32 PM PDT 24 Jul 11 05:56:49 PM PDT 24 114125609237 ps
T799 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2192847519 Jul 11 05:47:58 PM PDT 24 Jul 11 05:48:05 PM PDT 24 291429228 ps
T98 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.590434736 Jul 11 05:47:29 PM PDT 24 Jul 11 05:47:33 PM PDT 24 446503631 ps
T66 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2562501491 Jul 11 05:47:49 PM PDT 24 Jul 11 05:47:53 PM PDT 24 455810406 ps
T120 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.271016997 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:36 PM PDT 24 508195464 ps
T57 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4140090833 Jul 11 05:47:30 PM PDT 24 Jul 11 05:48:03 PM PDT 24 26348693967 ps
T58 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3153833170 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:37 PM PDT 24 4495027297 ps
T121 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1875252631 Jul 11 05:47:40 PM PDT 24 Jul 11 05:47:44 PM PDT 24 552236358 ps
T137 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2878400918 Jul 11 05:47:27 PM PDT 24 Jul 11 05:47:31 PM PDT 24 1286566080 ps
T800 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.404344628 Jul 11 05:47:47 PM PDT 24 Jul 11 05:47:51 PM PDT 24 413294039 ps
T122 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2235611332 Jul 11 05:47:36 PM PDT 24 Jul 11 05:47:42 PM PDT 24 1150032201 ps
T59 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.462898143 Jul 11 05:47:30 PM PDT 24 Jul 11 05:47:45 PM PDT 24 4939877256 ps
T62 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2520418889 Jul 11 05:48:07 PM PDT 24 Jul 11 05:48:24 PM PDT 24 8723525854 ps
T801 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2718744807 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 531402743 ps
T138 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2576664040 Jul 11 05:47:31 PM PDT 24 Jul 11 05:49:44 PM PDT 24 27000907597 ps
T99 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.109896107 Jul 11 05:47:49 PM PDT 24 Jul 11 05:47:53 PM PDT 24 773133270 ps
T132 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.824719753 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:40 PM PDT 24 2648943894 ps
T133 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2206106138 Jul 11 05:47:35 PM PDT 24 Jul 11 05:47:45 PM PDT 24 4369749342 ps
T63 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.32453726 Jul 11 05:47:54 PM PDT 24 Jul 11 05:48:11 PM PDT 24 8268288524 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.795459089 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:36 PM PDT 24 624287386 ps
T802 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2029869546 Jul 11 05:48:10 PM PDT 24 Jul 11 05:48:17 PM PDT 24 615395004 ps
T77 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3672042321 Jul 11 05:47:33 PM PDT 24 Jul 11 05:47:38 PM PDT 24 679142416 ps
T803 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2065389683 Jul 11 05:47:54 PM PDT 24 Jul 11 05:48:01 PM PDT 24 305788017 ps
T804 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.11080004 Jul 11 05:47:47 PM PDT 24 Jul 11 05:47:51 PM PDT 24 424771743 ps
T805 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3594779970 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:54 PM PDT 24 354160442 ps
T64 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.561919483 Jul 11 05:47:34 PM PDT 24 Jul 11 05:47:42 PM PDT 24 4236542559 ps
T67 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1394218553 Jul 11 05:47:49 PM PDT 24 Jul 11 05:48:00 PM PDT 24 8573228369 ps
T71 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3616897387 Jul 11 05:47:38 PM PDT 24 Jul 11 05:47:44 PM PDT 24 502843934 ps
T806 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1931849907 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 501487964 ps
T100 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4233514386 Jul 11 05:47:45 PM PDT 24 Jul 11 05:47:49 PM PDT 24 513592990 ps
T807 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4125584176 Jul 11 05:48:11 PM PDT 24 Jul 11 05:48:18 PM PDT 24 465100387 ps
T808 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.871121415 Jul 11 05:47:46 PM PDT 24 Jul 11 05:47:50 PM PDT 24 417779319 ps
T81 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.837574025 Jul 11 05:47:47 PM PDT 24 Jul 11 05:47:51 PM PDT 24 425546458 ps
T73 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1140948560 Jul 11 05:47:21 PM PDT 24 Jul 11 05:47:25 PM PDT 24 412374846 ps
T809 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3884350245 Jul 11 05:47:54 PM PDT 24 Jul 11 05:48:01 PM PDT 24 444767132 ps
T810 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1255221948 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 327165143 ps
T134 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.450321771 Jul 11 05:47:29 PM PDT 24 Jul 11 05:47:40 PM PDT 24 3044782809 ps
T75 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2665717144 Jul 11 05:47:34 PM PDT 24 Jul 11 05:48:00 PM PDT 24 8356008309 ps
T76 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3748401195 Jul 11 05:47:45 PM PDT 24 Jul 11 05:47:51 PM PDT 24 4087374494 ps
T811 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.236270768 Jul 11 05:47:40 PM PDT 24 Jul 11 05:47:44 PM PDT 24 486341195 ps
T72 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1157262495 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:58 PM PDT 24 684350162 ps
T82 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1887775984 Jul 11 05:47:32 PM PDT 24 Jul 11 05:47:37 PM PDT 24 440694107 ps
T124 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2379748795 Jul 11 05:47:29 PM PDT 24 Jul 11 05:47:48 PM PDT 24 26417724777 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2884629894 Jul 11 05:47:23 PM PDT 24 Jul 11 05:47:26 PM PDT 24 304473343 ps
T125 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2316827363 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:58 PM PDT 24 467180288 ps
T813 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3640166439 Jul 11 05:47:47 PM PDT 24 Jul 11 05:47:55 PM PDT 24 4386288846 ps
T814 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3481317041 Jul 11 05:47:40 PM PDT 24 Jul 11 05:47:45 PM PDT 24 325130554 ps
T135 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.989716825 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:51 PM PDT 24 4694250690 ps
T83 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1567305786 Jul 11 05:47:34 PM PDT 24 Jul 11 05:47:56 PM PDT 24 7530192340 ps
T815 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3569733701 Jul 11 05:48:13 PM PDT 24 Jul 11 05:48:19 PM PDT 24 346018145 ps
T78 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2822755498 Jul 11 05:47:32 PM PDT 24 Jul 11 05:47:39 PM PDT 24 796773294 ps
T816 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.734743635 Jul 11 05:48:00 PM PDT 24 Jul 11 05:48:06 PM PDT 24 459402187 ps
T79 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2454353588 Jul 11 05:47:34 PM PDT 24 Jul 11 05:47:40 PM PDT 24 622533924 ps
T817 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.174934485 Jul 11 05:47:55 PM PDT 24 Jul 11 05:48:03 PM PDT 24 431947763 ps
T818 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1068343814 Jul 11 05:48:05 PM PDT 24 Jul 11 05:48:13 PM PDT 24 529066138 ps
T126 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1165897600 Jul 11 05:47:30 PM PDT 24 Jul 11 05:47:38 PM PDT 24 920213900 ps
T819 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.916510422 Jul 11 05:47:55 PM PDT 24 Jul 11 05:48:02 PM PDT 24 324590397 ps
T820 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3139832173 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 288163678 ps
T821 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2012904749 Jul 11 05:48:14 PM PDT 24 Jul 11 05:48:20 PM PDT 24 310652977 ps
T136 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.893276037 Jul 11 05:47:38 PM PDT 24 Jul 11 05:47:45 PM PDT 24 2479370102 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4219448919 Jul 11 05:47:30 PM PDT 24 Jul 11 05:47:36 PM PDT 24 466107467 ps
T823 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.415066910 Jul 11 05:47:49 PM PDT 24 Jul 11 05:47:58 PM PDT 24 4878020757 ps
T824 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1494235308 Jul 11 05:47:32 PM PDT 24 Jul 11 05:47:37 PM PDT 24 411727429 ps
T825 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.841238512 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 360576148 ps
T826 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.313872072 Jul 11 05:47:33 PM PDT 24 Jul 11 05:47:39 PM PDT 24 456116925 ps
T827 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3839816724 Jul 11 05:47:53 PM PDT 24 Jul 11 05:48:10 PM PDT 24 4292020764 ps
T828 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.334280083 Jul 11 05:48:14 PM PDT 24 Jul 11 05:48:22 PM PDT 24 434423865 ps
T829 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3423308159 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:46 PM PDT 24 475262499 ps
T830 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1108391956 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 543554470 ps
T831 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1563891795 Jul 11 05:47:42 PM PDT 24 Jul 11 05:47:47 PM PDT 24 375215644 ps
T80 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2012105497 Jul 11 05:47:41 PM PDT 24 Jul 11 05:47:47 PM PDT 24 457416391 ps
T832 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.207138758 Jul 11 05:47:33 PM PDT 24 Jul 11 05:47:39 PM PDT 24 565531856 ps
T833 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4116863077 Jul 11 05:47:44 PM PDT 24 Jul 11 05:47:56 PM PDT 24 2320893742 ps
T834 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2354979850 Jul 11 05:47:28 PM PDT 24 Jul 11 05:47:39 PM PDT 24 4009135750 ps
T835 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1828640658 Jul 11 05:47:38 PM PDT 24 Jul 11 05:47:52 PM PDT 24 4509661560 ps
T836 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2157557929 Jul 11 05:47:30 PM PDT 24 Jul 11 05:47:35 PM PDT 24 495734174 ps
T837 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.463982211 Jul 11 05:48:00 PM PDT 24 Jul 11 05:48:06 PM PDT 24 569086048 ps
T838 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.694179707 Jul 11 05:47:54 PM PDT 24 Jul 11 05:48:01 PM PDT 24 310024802 ps
T839 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2851027354 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:56 PM PDT 24 344804686 ps
T840 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4007903091 Jul 11 05:47:36 PM PDT 24 Jul 11 05:47:41 PM PDT 24 323398984 ps
T84 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3287964671 Jul 11 05:47:43 PM PDT 24 Jul 11 05:48:10 PM PDT 24 8899004680 ps
T841 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3080045606 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 347344641 ps
T842 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3087559613 Jul 11 05:47:46 PM PDT 24 Jul 11 05:47:51 PM PDT 24 429432451 ps
T843 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1543394563 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:55 PM PDT 24 352294838 ps
T844 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3246958695 Jul 11 05:59:19 PM PDT 24 Jul 11 05:59:35 PM PDT 24 4636019234 ps
T845 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2355176820 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:57 PM PDT 24 387447225 ps
T127 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2789666606 Jul 11 05:47:49 PM PDT 24 Jul 11 05:47:53 PM PDT 24 529603703 ps
T128 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1117524086 Jul 11 05:47:30 PM PDT 24 Jul 11 05:49:07 PM PDT 24 45983413407 ps
T129 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1183906577 Jul 11 05:47:47 PM PDT 24 Jul 11 05:47:52 PM PDT 24 445680636 ps
T846 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1311238110 Jul 11 05:48:07 PM PDT 24 Jul 11 05:48:36 PM PDT 24 4493243219 ps
T847 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.39960803 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:54 PM PDT 24 290118557 ps
T848 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2092622956 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:58 PM PDT 24 444977093 ps
T849 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1252097127 Jul 11 05:47:45 PM PDT 24 Jul 11 05:47:49 PM PDT 24 319386913 ps
T130 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3967852143 Jul 11 05:47:20 PM PDT 24 Jul 11 05:48:47 PM PDT 24 21523194487 ps
T850 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1794641778 Jul 11 05:47:35 PM PDT 24 Jul 11 05:47:41 PM PDT 24 582445585 ps
T851 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.720643323 Jul 11 05:47:45 PM PDT 24 Jul 11 05:47:49 PM PDT 24 348528950 ps
T852 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1265384125 Jul 11 05:47:52 PM PDT 24 Jul 11 05:48:02 PM PDT 24 2418540877 ps
T853 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1164639221 Jul 11 05:47:29 PM PDT 24 Jul 11 05:47:53 PM PDT 24 8331451834 ps
T854 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3405082477 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:56 PM PDT 24 451411579 ps
T855 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3362807927 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:56 PM PDT 24 633762759 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4252431659 Jul 11 05:47:37 PM PDT 24 Jul 11 05:47:42 PM PDT 24 741212040 ps
T857 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.264803100 Jul 11 05:47:44 PM PDT 24 Jul 11 05:47:52 PM PDT 24 8259689906 ps
T858 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1617233179 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:58 PM PDT 24 293366505 ps
T131 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.529516374 Jul 11 05:47:22 PM PDT 24 Jul 11 05:47:26 PM PDT 24 560187865 ps
T859 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2895192317 Jul 11 05:47:41 PM PDT 24 Jul 11 05:47:45 PM PDT 24 533471420 ps
T860 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4084730678 Jul 11 05:47:39 PM PDT 24 Jul 11 05:47:48 PM PDT 24 4099132955 ps
T861 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.72380143 Jul 11 05:47:39 PM PDT 24 Jul 11 05:47:43 PM PDT 24 336145940 ps
T862 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2350360157 Jul 11 05:47:48 PM PDT 24 Jul 11 05:47:52 PM PDT 24 597302813 ps
T863 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2623514106 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:55 PM PDT 24 399225129 ps
T864 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2775728836 Jul 11 05:47:37 PM PDT 24 Jul 11 05:47:42 PM PDT 24 444164960 ps
T865 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1012625531 Jul 11 05:47:21 PM PDT 24 Jul 11 05:47:27 PM PDT 24 839767858 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.606223117 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:56 PM PDT 24 301447423 ps
T867 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.74459999 Jul 11 05:48:10 PM PDT 24 Jul 11 05:48:18 PM PDT 24 456657960 ps
T868 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1299424745 Jul 11 05:48:00 PM PDT 24 Jul 11 05:48:07 PM PDT 24 416493691 ps
T869 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.427052369 Jul 11 05:48:10 PM PDT 24 Jul 11 05:48:18 PM PDT 24 519156569 ps
T870 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2408618677 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 435204089 ps
T871 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1369089248 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 420629987 ps
T872 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.71096065 Jul 11 05:47:34 PM PDT 24 Jul 11 05:47:42 PM PDT 24 5030293096 ps
T873 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1066341097 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:47 PM PDT 24 721021818 ps
T874 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1225879512 Jul 11 05:47:22 PM PDT 24 Jul 11 05:47:27 PM PDT 24 603953301 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4037498418 Jul 11 05:47:23 PM PDT 24 Jul 11 05:47:28 PM PDT 24 503301740 ps
T876 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1154922835 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 375442066 ps
T877 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2211829096 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:57 PM PDT 24 417435326 ps
T878 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.606233213 Jul 11 05:47:36 PM PDT 24 Jul 11 05:47:51 PM PDT 24 4474375495 ps
T879 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1369255988 Jul 11 05:47:44 PM PDT 24 Jul 11 05:47:51 PM PDT 24 1957037016 ps
T880 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.726004622 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 390762511 ps
T881 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.441943873 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 572432937 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1184527144 Jul 11 05:47:29 PM PDT 24 Jul 11 05:47:33 PM PDT 24 410973375 ps
T883 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3105322001 Jul 11 05:48:14 PM PDT 24 Jul 11 05:48:21 PM PDT 24 375216830 ps
T884 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1165394033 Jul 11 05:47:39 PM PDT 24 Jul 11 05:47:49 PM PDT 24 2458694759 ps
T885 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2142951059 Jul 11 05:47:23 PM PDT 24 Jul 11 05:47:26 PM PDT 24 422844082 ps
T886 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2451786228 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:55 PM PDT 24 400388535 ps
T887 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1910741557 Jul 11 05:47:49 PM PDT 24 Jul 11 05:47:53 PM PDT 24 377696526 ps
T888 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4287549769 Jul 11 05:47:56 PM PDT 24 Jul 11 05:48:02 PM PDT 24 310116147 ps
T889 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1853788835 Jul 11 05:47:34 PM PDT 24 Jul 11 05:47:41 PM PDT 24 3157963864 ps
T890 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1789730590 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:57 PM PDT 24 525333717 ps
T891 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.930524872 Jul 11 05:47:44 PM PDT 24 Jul 11 05:47:49 PM PDT 24 5072222888 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3754331588 Jul 11 05:47:53 PM PDT 24 Jul 11 05:48:00 PM PDT 24 499882633 ps
T893 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2005135470 Jul 11 05:47:52 PM PDT 24 Jul 11 05:48:00 PM PDT 24 1760154337 ps
T894 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.614716652 Jul 11 05:48:07 PM PDT 24 Jul 11 05:48:16 PM PDT 24 378843033 ps
T895 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4042122221 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:48 PM PDT 24 444075874 ps
T896 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3970861769 Jul 11 05:47:35 PM PDT 24 Jul 11 05:47:50 PM PDT 24 4223595780 ps
T897 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2388414204 Jul 11 05:47:35 PM PDT 24 Jul 11 05:47:45 PM PDT 24 8776954545 ps
T898 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1146023949 Jul 11 05:47:55 PM PDT 24 Jul 11 05:48:03 PM PDT 24 441908132 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3168195236 Jul 11 05:47:38 PM PDT 24 Jul 11 05:47:46 PM PDT 24 1199276351 ps
T900 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2874011952 Jul 11 05:47:37 PM PDT 24 Jul 11 05:47:42 PM PDT 24 732654410 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1902892319 Jul 11 05:47:30 PM PDT 24 Jul 11 05:47:35 PM PDT 24 542546562 ps
T902 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.908100497 Jul 11 05:47:49 PM PDT 24 Jul 11 05:47:54 PM PDT 24 316554539 ps
T903 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4151748549 Jul 11 05:47:30 PM PDT 24 Jul 11 05:47:41 PM PDT 24 2512667478 ps
T904 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.832586794 Jul 11 05:47:32 PM PDT 24 Jul 11 05:47:39 PM PDT 24 502891841 ps
T905 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.286082754 Jul 11 05:47:21 PM PDT 24 Jul 11 05:47:26 PM PDT 24 428275245 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2916531129 Jul 11 05:47:35 PM PDT 24 Jul 11 05:47:40 PM PDT 24 882602328 ps
T907 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1111475635 Jul 11 05:47:58 PM PDT 24 Jul 11 05:48:05 PM PDT 24 309376678 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1471956936 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:29 PM PDT 24 989396971 ps
T909 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4287192228 Jul 11 05:47:42 PM PDT 24 Jul 11 05:47:47 PM PDT 24 589162200 ps
T910 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4124503 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:57 PM PDT 24 2373615426 ps
T911 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3805488704 Jul 11 05:47:32 PM PDT 24 Jul 11 05:47:37 PM PDT 24 1097934193 ps
T912 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2461996899 Jul 11 05:47:52 PM PDT 24 Jul 11 05:48:04 PM PDT 24 5000389652 ps
T913 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3142697286 Jul 11 05:47:51 PM PDT 24 Jul 11 05:47:59 PM PDT 24 4518416441 ps
T914 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4040413090 Jul 11 05:47:28 PM PDT 24 Jul 11 05:47:31 PM PDT 24 479422042 ps
T915 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1418179774 Jul 11 05:47:53 PM PDT 24 Jul 11 05:48:01 PM PDT 24 740612050 ps
T916 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.468254673 Jul 11 05:47:50 PM PDT 24 Jul 11 05:47:55 PM PDT 24 299921395 ps
T917 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.101399867 Jul 11 05:47:38 PM PDT 24 Jul 11 05:47:45 PM PDT 24 422173918 ps
T918 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2540058327 Jul 11 05:47:52 PM PDT 24 Jul 11 05:47:59 PM PDT 24 380744346 ps
T919 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1937226055 Jul 11 05:47:33 PM PDT 24 Jul 11 05:47:38 PM PDT 24 298985766 ps
T920 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3899470314 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 481584758 ps

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3437388733
Short name T6
Test name
Test status
Simulation time 124337231627 ps
CPU time 211.04 seconds
Started Jul 11 05:50:41 PM PDT 24
Finished Jul 11 05:54:12 PM PDT 24
Peak memory 210604 kb
Host smart-8f7db9b3-cb54-4037-baeb-7a6a6bd13a49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437388733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3437388733
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2192127468
Short name T9
Test name
Test status
Simulation time 504592305881 ps
CPU time 249.73 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 05:53:14 PM PDT 24
Peak memory 201796 kb
Host smart-c3dc32e8-8f66-4816-9de5-c5e60bbfbb02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192127468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2192127468
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.24948763
Short name T35
Test name
Test status
Simulation time 307939882297 ps
CPU time 159.2 seconds
Started Jul 11 05:48:45 PM PDT 24
Finished Jul 11 05:51:27 PM PDT 24
Peak memory 210228 kb
Host smart-86fb9501-e339-4ab9-843b-7a6c7a3cb27b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24948763 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.24948763
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3944977260
Short name T156
Test name
Test status
Simulation time 690484306585 ps
CPU time 409.25 seconds
Started Jul 11 05:50:53 PM PDT 24
Finished Jul 11 05:57:43 PM PDT 24
Peak memory 202216 kb
Host smart-16b08023-feea-4b3d-93ae-359bed0812f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944977260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3944977260
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2946118504
Short name T151
Test name
Test status
Simulation time 538689580848 ps
CPU time 1176.25 seconds
Started Jul 11 05:49:17 PM PDT 24
Finished Jul 11 06:08:56 PM PDT 24
Peak memory 201740 kb
Host smart-8dcea084-459f-4be0-8c3d-eecbff3fe439
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946118504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2946118504
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3292330430
Short name T14
Test name
Test status
Simulation time 103936223934 ps
CPU time 57.89 seconds
Started Jul 11 05:49:57 PM PDT 24
Finished Jul 11 05:50:56 PM PDT 24
Peak memory 210328 kb
Host smart-6c11c659-330e-4670-92a9-644712d4d348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292330430 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3292330430
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2098139027
Short name T48
Test name
Test status
Simulation time 521130673730 ps
CPU time 369.54 seconds
Started Jul 11 05:48:23 PM PDT 24
Finished Jul 11 05:54:37 PM PDT 24
Peak memory 201912 kb
Host smart-57989617-96b4-4156-96b7-304d04cebb1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098139027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2098139027
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1109499590
Short name T144
Test name
Test status
Simulation time 673581771318 ps
CPU time 1432.2 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 06:12:55 PM PDT 24
Peak memory 201936 kb
Host smart-d635b4f1-d07a-4065-aad1-2ee3ca9b218f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109499590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1109499590
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1153236738
Short name T36
Test name
Test status
Simulation time 87618426301 ps
CPU time 80.45 seconds
Started Jul 11 05:51:05 PM PDT 24
Finished Jul 11 05:52:27 PM PDT 24
Peak memory 210544 kb
Host smart-65b41ff8-da62-4e5a-9f8e-1b5981ed25e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153236738 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1153236738
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.427021489
Short name T146
Test name
Test status
Simulation time 523525880597 ps
CPU time 305.15 seconds
Started Jul 11 05:49:44 PM PDT 24
Finished Jul 11 05:54:50 PM PDT 24
Peak memory 201920 kb
Host smart-df285a45-47dd-451c-b614-9530266d39d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427021489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.427021489
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3808005370
Short name T208
Test name
Test status
Simulation time 362814808134 ps
CPU time 861.83 seconds
Started Jul 11 05:48:48 PM PDT 24
Finished Jul 11 06:03:13 PM PDT 24
Peak memory 201996 kb
Host smart-d82e395a-8660-4a80-9c9c-8037be5e6dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808005370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3808005370
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.561919483
Short name T64
Test name
Test status
Simulation time 4236542559 ps
CPU time 4.07 seconds
Started Jul 11 05:47:34 PM PDT 24
Finished Jul 11 05:47:42 PM PDT 24
Peak memory 201792 kb
Host smart-1bc6c1d5-a092-44f8-9482-d1dca6871608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561919483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.561919483
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.781938922
Short name T242
Test name
Test status
Simulation time 505937409800 ps
CPU time 203.16 seconds
Started Jul 11 05:49:25 PM PDT 24
Finished Jul 11 05:52:50 PM PDT 24
Peak memory 201864 kb
Host smart-a315a7ea-56df-4dab-a8d0-691c34399074
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781938922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.781938922
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3174740011
Short name T261
Test name
Test status
Simulation time 337440028357 ps
CPU time 179.15 seconds
Started Jul 11 05:52:17 PM PDT 24
Finished Jul 11 05:55:17 PM PDT 24
Peak memory 201952 kb
Host smart-0a58e66a-db5f-4cd2-8f07-a379b9f79cfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174740011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3174740011
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1742422123
Short name T155
Test name
Test status
Simulation time 354116063733 ps
CPU time 124.32 seconds
Started Jul 11 05:48:46 PM PDT 24
Finished Jul 11 05:50:53 PM PDT 24
Peak memory 202120 kb
Host smart-4b3774ec-2e13-437c-858a-1e77c2d00a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742422123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1742422123
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.748358080
Short name T42
Test name
Test status
Simulation time 446852230 ps
CPU time 0.89 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:49:06 PM PDT 24
Peak memory 201624 kb
Host smart-1af11774-d4fe-4fba-a4e3-b942247dfd9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748358080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.748358080
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.908702665
Short name T194
Test name
Test status
Simulation time 496745998358 ps
CPU time 130.34 seconds
Started Jul 11 05:49:56 PM PDT 24
Finished Jul 11 05:52:08 PM PDT 24
Peak memory 201952 kb
Host smart-9694bc01-9b11-4b34-9612-d924e6100780
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908702665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.908702665
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.243856136
Short name T265
Test name
Test status
Simulation time 345404148555 ps
CPU time 830.26 seconds
Started Jul 11 05:50:47 PM PDT 24
Finished Jul 11 06:04:39 PM PDT 24
Peak memory 201912 kb
Host smart-7b2ff1c7-891d-4c29-8ee2-5377401520a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243856136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.243856136
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3713530711
Short name T60
Test name
Test status
Simulation time 520727445747 ps
CPU time 1147.5 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 06:09:55 PM PDT 24
Peak memory 201412 kb
Host smart-0195af57-9751-4438-9228-b30f9d649b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713530711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3713530711
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.296354113
Short name T317
Test name
Test status
Simulation time 504112130415 ps
CPU time 986.48 seconds
Started Jul 11 05:49:55 PM PDT 24
Finished Jul 11 06:06:23 PM PDT 24
Peak memory 201956 kb
Host smart-9d7e9102-2c16-433d-b0c0-48b409f0cef2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296354113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.296354113
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2379748795
Short name T124
Test name
Test status
Simulation time 26417724777 ps
CPU time 17.78 seconds
Started Jul 11 05:47:29 PM PDT 24
Finished Jul 11 05:47:48 PM PDT 24
Peak memory 201828 kb
Host smart-92a6e46d-e4e9-4d22-ad5b-425eefd304e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379748795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2379748795
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3616897387
Short name T71
Test name
Test status
Simulation time 502843934 ps
CPU time 3.44 seconds
Started Jul 11 05:47:38 PM PDT 24
Finished Jul 11 05:47:44 PM PDT 24
Peak memory 218116 kb
Host smart-831a7762-3513-4546-a556-979eb3f9c42d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616897387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3616897387
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1698984068
Short name T12
Test name
Test status
Simulation time 330987336954 ps
CPU time 193.17 seconds
Started Jul 11 05:49:32 PM PDT 24
Finished Jul 11 05:52:47 PM PDT 24
Peak memory 201936 kb
Host smart-0820f66a-b633-459c-a113-6c4ee18b36c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698984068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1698984068
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2757675646
Short name T8
Test name
Test status
Simulation time 613178074153 ps
CPU time 1177.84 seconds
Started Jul 11 05:52:12 PM PDT 24
Finished Jul 11 06:11:51 PM PDT 24
Peak memory 201988 kb
Host smart-d40ed9c9-c552-4047-b9c0-a351abf375d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757675646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2757675646
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2532825246
Short name T290
Test name
Test status
Simulation time 333087792328 ps
CPU time 236.02 seconds
Started Jul 11 05:50:57 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 201852 kb
Host smart-32d6f868-f57c-450d-b4f7-e302a1e9a556
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532825246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2532825246
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1105371361
Short name T302
Test name
Test status
Simulation time 524250280260 ps
CPU time 1132.87 seconds
Started Jul 11 05:48:36 PM PDT 24
Finished Jul 11 06:07:30 PM PDT 24
Peak memory 202076 kb
Host smart-f1e8866a-cbc9-4881-98ee-825a64b54c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105371361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1105371361
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.424036458
Short name T246
Test name
Test status
Simulation time 503323365527 ps
CPU time 145.7 seconds
Started Jul 11 05:48:52 PM PDT 24
Finished Jul 11 05:51:22 PM PDT 24
Peak memory 201976 kb
Host smart-33ff1dd7-3b69-44c3-b74a-a391ae1f961e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424036458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.424036458
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3480690707
Short name T307
Test name
Test status
Simulation time 527463933923 ps
CPU time 464.44 seconds
Started Jul 11 05:49:10 PM PDT 24
Finished Jul 11 05:57:01 PM PDT 24
Peak memory 201896 kb
Host smart-dcd664df-ab43-4960-87af-e783fc5b878e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480690707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3480690707
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3682089868
Short name T299
Test name
Test status
Simulation time 377799850701 ps
CPU time 454.93 seconds
Started Jul 11 05:49:13 PM PDT 24
Finished Jul 11 05:56:53 PM PDT 24
Peak memory 201904 kb
Host smart-ac1307aa-77ef-4df0-a839-a8751db2b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682089868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3682089868
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2021582405
Short name T70
Test name
Test status
Simulation time 4591074489 ps
CPU time 10.39 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 05:48:44 PM PDT 24
Peak memory 217152 kb
Host smart-c1e3bbf1-f9d1-48ea-a44f-a4ba0e72fd77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021582405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2021582405
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1875252631
Short name T121
Test name
Test status
Simulation time 552236358 ps
CPU time 1.08 seconds
Started Jul 11 05:47:40 PM PDT 24
Finished Jul 11 05:47:44 PM PDT 24
Peak memory 201504 kb
Host smart-0624247e-3244-41be-beef-6e4b073c9309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875252631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1875252631
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.208709341
Short name T343
Test name
Test status
Simulation time 165461352589 ps
CPU time 93.14 seconds
Started Jul 11 05:51:09 PM PDT 24
Finished Jul 11 05:52:43 PM PDT 24
Peak memory 201980 kb
Host smart-3d308933-09d2-44e0-a7eb-c96f84a2484f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208709341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.208709341
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3504457778
Short name T263
Test name
Test status
Simulation time 331340837963 ps
CPU time 366.33 seconds
Started Jul 11 05:48:48 PM PDT 24
Finished Jul 11 05:54:57 PM PDT 24
Peak memory 201896 kb
Host smart-328623cf-c822-4320-8bd3-6549c68c6e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504457778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3504457778
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1766135436
Short name T251
Test name
Test status
Simulation time 301967640747 ps
CPU time 1050.24 seconds
Started Jul 11 05:49:00 PM PDT 24
Finished Jul 11 06:06:40 PM PDT 24
Peak memory 202192 kb
Host smart-38fc5b48-fec2-4fbe-9ef4-93bb2c10b4c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766135436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1766135436
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1385829886
Short name T316
Test name
Test status
Simulation time 616480733107 ps
CPU time 593.05 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 05:58:56 PM PDT 24
Peak memory 202212 kb
Host smart-006b720e-42bb-44b5-8e46-57f124a27762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385829886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1385829886
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3331065709
Short name T239
Test name
Test status
Simulation time 328605528339 ps
CPU time 176.13 seconds
Started Jul 11 05:51:00 PM PDT 24
Finished Jul 11 05:53:58 PM PDT 24
Peak memory 201840 kb
Host smart-a676db16-208f-4031-99b0-caf368414a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331065709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3331065709
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1884162833
Short name T271
Test name
Test status
Simulation time 324737928944 ps
CPU time 780.64 seconds
Started Jul 11 05:52:11 PM PDT 24
Finished Jul 11 06:05:14 PM PDT 24
Peak memory 201956 kb
Host smart-258f2a66-ed88-4b39-8292-4c0d10dfaac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884162833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1884162833
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1001940616
Short name T289
Test name
Test status
Simulation time 554410010840 ps
CPU time 169.71 seconds
Started Jul 11 05:50:52 PM PDT 24
Finished Jul 11 05:53:43 PM PDT 24
Peak memory 201888 kb
Host smart-2db49df9-4b32-4379-8a46-1912e405575d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001940616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1001940616
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3309085273
Short name T366
Test name
Test status
Simulation time 164620325520 ps
CPU time 404.16 seconds
Started Jul 11 05:52:18 PM PDT 24
Finished Jul 11 05:59:03 PM PDT 24
Peak memory 201976 kb
Host smart-bfb0f6f7-8702-4a43-a118-8fd257a60e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309085273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3309085273
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1042013570
Short name T275
Test name
Test status
Simulation time 476003850484 ps
CPU time 1336.29 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 06:11:53 PM PDT 24
Peak memory 210416 kb
Host smart-6666a9a2-f696-4952-a837-0f177d7f82f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042013570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1042013570
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3758463825
Short name T250
Test name
Test status
Simulation time 589736832730 ps
CPU time 1559.52 seconds
Started Jul 11 05:48:29 PM PDT 24
Finished Jul 11 06:14:31 PM PDT 24
Peak memory 210416 kb
Host smart-f57dbfb3-d51e-41f8-9d7a-95e865f60b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758463825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3758463825
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2942749870
Short name T154
Test name
Test status
Simulation time 488726213561 ps
CPU time 268.26 seconds
Started Jul 11 05:51:03 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 201952 kb
Host smart-a633fbfd-f9fa-4b02-b15a-8bf078c74be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942749870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2942749870
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3937309005
Short name T212
Test name
Test status
Simulation time 484924203186 ps
CPU time 834 seconds
Started Jul 11 05:48:39 PM PDT 24
Finished Jul 11 06:02:34 PM PDT 24
Peak memory 201832 kb
Host smart-a1b08d60-8404-4be7-a7eb-a0541135538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937309005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3937309005
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3009424460
Short name T292
Test name
Test status
Simulation time 674320661735 ps
CPU time 183.63 seconds
Started Jul 11 05:48:38 PM PDT 24
Finished Jul 11 05:51:43 PM PDT 24
Peak memory 201896 kb
Host smart-e0a85879-f35c-4967-9c56-89e490e79f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009424460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3009424460
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3499174858
Short name T45
Test name
Test status
Simulation time 351806385909 ps
CPU time 764.17 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 06:01:17 PM PDT 24
Peak memory 201928 kb
Host smart-708d286e-73a9-4bdb-ac78-0f037e5c91fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499174858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3499174858
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3143831864
Short name T50
Test name
Test status
Simulation time 105326087094 ps
CPU time 401.61 seconds
Started Jul 11 05:48:34 PM PDT 24
Finished Jul 11 05:55:17 PM PDT 24
Peak memory 202448 kb
Host smart-65bdfd39-a408-43b0-b9fd-a318ac5389d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143831864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3143831864
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3807541382
Short name T304
Test name
Test status
Simulation time 55628076599 ps
CPU time 83.49 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:50:07 PM PDT 24
Peak memory 210540 kb
Host smart-acf3d0dd-2535-458b-bf1e-2cc93ec861d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807541382 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3807541382
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3754783263
Short name T358
Test name
Test status
Simulation time 487961240468 ps
CPU time 1070.73 seconds
Started Jul 11 05:48:52 PM PDT 24
Finished Jul 11 06:06:48 PM PDT 24
Peak memory 201916 kb
Host smart-71946ad7-f7a1-4d95-a41c-fda29f1645db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754783263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3754783263
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.223283542
Short name T319
Test name
Test status
Simulation time 490644797340 ps
CPU time 290.08 seconds
Started Jul 11 05:49:24 PM PDT 24
Finished Jul 11 05:54:15 PM PDT 24
Peak memory 201896 kb
Host smart-7759a8d0-a96c-449b-b647-617d03efcc35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223283542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
223283542
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.13412606
Short name T286
Test name
Test status
Simulation time 536309387421 ps
CPU time 286.07 seconds
Started Jul 11 05:49:07 PM PDT 24
Finished Jul 11 05:54:01 PM PDT 24
Peak memory 201952 kb
Host smart-76c0e997-77be-4205-8bc6-8bbe6f6a9c39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13412606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gatin
g.13412606
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1394218553
Short name T67
Test name
Test status
Simulation time 8573228369 ps
CPU time 8.15 seconds
Started Jul 11 05:47:49 PM PDT 24
Finished Jul 11 05:48:00 PM PDT 24
Peak memory 201852 kb
Host smart-fedfa7a1-7241-451a-9283-881b338834b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394218553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1394218553
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3140605703
Short name T327
Test name
Test status
Simulation time 323991480967 ps
CPU time 95.4 seconds
Started Jul 11 05:49:09 PM PDT 24
Finished Jul 11 05:50:51 PM PDT 24
Peak memory 210268 kb
Host smart-f4d3a2ed-f6c4-4c22-902f-ea0eb6ebba7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140605703 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3140605703
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3838466904
Short name T110
Test name
Test status
Simulation time 63865914169 ps
CPU time 166.6 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 05:51:20 PM PDT 24
Peak memory 218156 kb
Host smart-ef9675a6-a35b-44e8-8f6f-b1576e1f8ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838466904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3838466904
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1985548196
Short name T282
Test name
Test status
Simulation time 347500036572 ps
CPU time 768 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 06:03:36 PM PDT 24
Peak memory 201856 kb
Host smart-d9b671d1-9c17-4192-9d42-9e0a055bc520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985548196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1985548196
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3602169968
Short name T355
Test name
Test status
Simulation time 396582036753 ps
CPU time 843.63 seconds
Started Jul 11 05:49:11 PM PDT 24
Finished Jul 11 06:03:20 PM PDT 24
Peak memory 201964 kb
Host smart-4f99aca1-8c69-4fda-8804-58c4e44fe1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602169968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3602169968
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1910297847
Short name T332
Test name
Test status
Simulation time 369120156368 ps
CPU time 840.26 seconds
Started Jul 11 05:51:30 PM PDT 24
Finished Jul 11 06:05:32 PM PDT 24
Peak memory 201892 kb
Host smart-0fcc7e29-8422-45b3-bded-3c272d13f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910297847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1910297847
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1606185250
Short name T323
Test name
Test status
Simulation time 328166489754 ps
CPU time 383.86 seconds
Started Jul 11 05:52:09 PM PDT 24
Finished Jul 11 05:58:34 PM PDT 24
Peak memory 201964 kb
Host smart-7d0d1231-41c7-4ad1-ac0e-48fe21de2552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606185250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1606185250
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3788463483
Short name T335
Test name
Test status
Simulation time 334442715457 ps
CPU time 808.76 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 06:02:42 PM PDT 24
Peak memory 201920 kb
Host smart-be4f56c5-ca1b-48fa-b50b-a0a1174cb268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788463483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3788463483
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.4261151741
Short name T223
Test name
Test status
Simulation time 191238659828 ps
CPU time 422.71 seconds
Started Jul 11 05:50:49 PM PDT 24
Finished Jul 11 05:57:52 PM PDT 24
Peak memory 201884 kb
Host smart-0a4cdfdc-11bc-4448-b50d-f5c26ba0885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261151741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4261151741
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1644502696
Short name T277
Test name
Test status
Simulation time 322914314471 ps
CPU time 787.16 seconds
Started Jul 11 05:50:47 PM PDT 24
Finished Jul 11 06:03:55 PM PDT 24
Peak memory 201904 kb
Host smart-9bd06878-e562-479b-bfab-b958ce3ec24e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644502696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1644502696
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3092871408
Short name T141
Test name
Test status
Simulation time 210534493478 ps
CPU time 342.68 seconds
Started Jul 11 05:50:37 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 202044 kb
Host smart-e8080da2-96ed-4315-a0e0-3d468fdb6443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092871408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3092871408
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2822755498
Short name T78
Test name
Test status
Simulation time 796773294 ps
CPU time 2.71 seconds
Started Jul 11 05:47:32 PM PDT 24
Finished Jul 11 05:47:39 PM PDT 24
Peak memory 210084 kb
Host smart-339cc7cd-feb3-4f6d-9ada-71fd5a01f4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822755498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2822755498
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1496759920
Short name T308
Test name
Test status
Simulation time 176006588992 ps
CPU time 95.48 seconds
Started Jul 11 05:49:00 PM PDT 24
Finished Jul 11 05:50:45 PM PDT 24
Peak memory 201896 kb
Host smart-4a196aab-202d-4e33-94a9-151d4cf597a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496759920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1496759920
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3192855390
Short name T22
Test name
Test status
Simulation time 458885923214 ps
CPU time 199.47 seconds
Started Jul 11 05:49:28 PM PDT 24
Finished Jul 11 05:52:49 PM PDT 24
Peak memory 210252 kb
Host smart-789ce646-748d-485e-8f7e-f4604a880e71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192855390 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3192855390
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.456329791
Short name T288
Test name
Test status
Simulation time 321448501581 ps
CPU time 752.52 seconds
Started Jul 11 05:51:36 PM PDT 24
Finished Jul 11 06:04:10 PM PDT 24
Peak memory 201880 kb
Host smart-f71ff29c-ad5c-4590-9d4f-688be61cce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456329791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.456329791
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.413451784
Short name T18
Test name
Test status
Simulation time 77412590767 ps
CPU time 61.83 seconds
Started Jul 11 05:48:29 PM PDT 24
Finished Jul 11 05:49:33 PM PDT 24
Peak memory 210584 kb
Host smart-89b690f9-583d-46eb-b9bc-ecd6e7017886
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413451784 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.413451784
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2136123919
Short name T365
Test name
Test status
Simulation time 454966178747 ps
CPU time 626.43 seconds
Started Jul 11 05:48:55 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 201956 kb
Host smart-8dde0bb6-2f7e-4e3e-ace6-f53538da1f4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136123919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2136123919
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4276111705
Short name T40
Test name
Test status
Simulation time 31677169163 ps
CPU time 67.28 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:50:45 PM PDT 24
Peak memory 202096 kb
Host smart-ed201585-942f-4fa5-aa38-59b79346f00e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276111705 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.4276111705
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3322111997
Short name T255
Test name
Test status
Simulation time 296385970537 ps
CPU time 958.16 seconds
Started Jul 11 05:48:33 PM PDT 24
Finished Jul 11 06:04:33 PM PDT 24
Peak memory 202116 kb
Host smart-dfe651da-4681-4315-b590-1aa1df74b6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322111997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3322111997
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3742751496
Short name T248
Test name
Test status
Simulation time 127332059799 ps
CPU time 466.33 seconds
Started Jul 11 05:49:32 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 202212 kb
Host smart-49f35139-3ed5-4c3d-9c49-53728a90e069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742751496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3742751496
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.865867625
Short name T216
Test name
Test status
Simulation time 565640076723 ps
CPU time 246.51 seconds
Started Jul 11 05:50:06 PM PDT 24
Finished Jul 11 05:54:15 PM PDT 24
Peak memory 201984 kb
Host smart-9865bfbd-36ae-4f71-9f8d-3c67644ea146
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865867625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.865867625
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3337869123
Short name T168
Test name
Test status
Simulation time 359763793420 ps
CPU time 198.25 seconds
Started Jul 11 05:51:26 PM PDT 24
Finished Jul 11 05:54:46 PM PDT 24
Peak memory 201936 kb
Host smart-5b2c84b6-cfdc-4308-bf48-03f378a86710
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337869123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3337869123
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4292812747
Short name T330
Test name
Test status
Simulation time 573723073131 ps
CPU time 275.87 seconds
Started Jul 11 05:51:38 PM PDT 24
Finished Jul 11 05:56:15 PM PDT 24
Peak memory 201912 kb
Host smart-1637a2d8-cb3d-4d41-955f-deed1d241d07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292812747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4292812747
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.224616221
Short name T322
Test name
Test status
Simulation time 565627651463 ps
CPU time 1348.81 seconds
Started Jul 11 05:52:03 PM PDT 24
Finished Jul 11 06:14:32 PM PDT 24
Peak memory 201888 kb
Host smart-f03215cb-6190-48ed-a9ac-10ad9b8c261e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224616221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
224616221
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2821619286
Short name T294
Test name
Test status
Simulation time 344680808505 ps
CPU time 382.13 seconds
Started Jul 11 05:48:18 PM PDT 24
Finished Jul 11 05:54:46 PM PDT 24
Peak memory 201864 kb
Host smart-edf6e34f-a01a-4545-ac28-6a995dbf973b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821619286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2821619286
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.844244249
Short name T532
Test name
Test status
Simulation time 330422297134 ps
CPU time 182.2 seconds
Started Jul 11 05:48:17 PM PDT 24
Finished Jul 11 05:51:24 PM PDT 24
Peak memory 201936 kb
Host smart-7f26df74-0b47-467d-b3ce-12f44a0f993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844244249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.844244249
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2681538919
Short name T260
Test name
Test status
Simulation time 384036268715 ps
CPU time 858.21 seconds
Started Jul 11 05:48:35 PM PDT 24
Finished Jul 11 06:02:55 PM PDT 24
Peak memory 201848 kb
Host smart-da690c40-4c69-4e36-a16a-5a22712b7edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681538919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2681538919
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.220818539
Short name T350
Test name
Test status
Simulation time 523413144242 ps
CPU time 553.54 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 201912 kb
Host smart-3336b908-449d-47ff-93bc-355aead7acde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220818539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.220818539
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2494018679
Short name T169
Test name
Test status
Simulation time 257291294601 ps
CPU time 613.58 seconds
Started Jul 11 05:48:50 PM PDT 24
Finished Jul 11 05:59:08 PM PDT 24
Peak memory 202252 kb
Host smart-43eee735-e560-417d-a545-6fdca7223f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494018679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2494018679
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1188750989
Short name T364
Test name
Test status
Simulation time 177574587713 ps
CPU time 241.5 seconds
Started Jul 11 05:48:53 PM PDT 24
Finished Jul 11 05:53:00 PM PDT 24
Peak memory 201964 kb
Host smart-72f0b3a5-33a0-41cd-b941-e327df5a1aee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188750989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1188750989
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2941164367
Short name T256
Test name
Test status
Simulation time 94467862580 ps
CPU time 361.26 seconds
Started Jul 11 05:48:52 PM PDT 24
Finished Jul 11 05:54:59 PM PDT 24
Peak memory 202224 kb
Host smart-562c9382-1a37-4f4f-a8e8-c7ce683e83ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941164367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2941164367
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3438579526
Short name T313
Test name
Test status
Simulation time 525243762855 ps
CPU time 1137.43 seconds
Started Jul 11 05:48:51 PM PDT 24
Finished Jul 11 06:07:53 PM PDT 24
Peak memory 201860 kb
Host smart-cc27802e-3172-486a-9f05-89afcd87649c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438579526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3438579526
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1720934195
Short name T354
Test name
Test status
Simulation time 342543707650 ps
CPU time 97.37 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:51:15 PM PDT 24
Peak memory 201916 kb
Host smart-c0efa373-5bf8-4b95-8f25-ebc5b4d59c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720934195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1720934195
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4205794221
Short name T306
Test name
Test status
Simulation time 336065662217 ps
CPU time 796.15 seconds
Started Jul 11 05:49:00 PM PDT 24
Finished Jul 11 06:02:25 PM PDT 24
Peak memory 201836 kb
Host smart-8aea2e66-a60a-4b11-bb6e-8ba76e9f38d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205794221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4205794221
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2948504375
Short name T97
Test name
Test status
Simulation time 245496295308 ps
CPU time 346.18 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 05:55:05 PM PDT 24
Peak memory 210816 kb
Host smart-705e90f1-2407-433c-b35a-6857371310eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948504375 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2948504375
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1678742220
Short name T90
Test name
Test status
Simulation time 524705812933 ps
CPU time 372.44 seconds
Started Jul 11 05:50:05 PM PDT 24
Finished Jul 11 05:56:20 PM PDT 24
Peak memory 201888 kb
Host smart-11d7b276-d3f5-4186-b11e-8238cc959875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678742220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1678742220
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1420285719
Short name T378
Test name
Test status
Simulation time 106041038160 ps
CPU time 431.67 seconds
Started Jul 11 05:50:05 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 202232 kb
Host smart-331c732a-20d0-4cad-b71b-47d4b664dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420285719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1420285719
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1661727335
Short name T339
Test name
Test status
Simulation time 165984500591 ps
CPU time 96.11 seconds
Started Jul 11 05:50:57 PM PDT 24
Finished Jul 11 05:52:34 PM PDT 24
Peak memory 201964 kb
Host smart-f1f7a538-45c0-43f2-a23b-f8ce489a92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661727335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1661727335
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2632668870
Short name T180
Test name
Test status
Simulation time 176735206589 ps
CPU time 414.25 seconds
Started Jul 11 05:51:58 PM PDT 24
Finished Jul 11 05:58:54 PM PDT 24
Peak memory 201904 kb
Host smart-6e43c163-796a-47cd-807a-5de0f5199f4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632668870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2632668870
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1012625531
Short name T865
Test name
Test status
Simulation time 839767858 ps
CPU time 3.39 seconds
Started Jul 11 05:47:21 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 201724 kb
Host smart-ff23357b-027c-4090-bf28-98aa55a13541
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012625531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1012625531
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3967852143
Short name T130
Test name
Test status
Simulation time 21523194487 ps
CPU time 83.78 seconds
Started Jul 11 05:47:20 PM PDT 24
Finished Jul 11 05:48:47 PM PDT 24
Peak memory 201828 kb
Host smart-a2da1b35-33a9-4476-89bd-5b24781f77a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967852143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3967852143
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3805488704
Short name T911
Test name
Test status
Simulation time 1097934193 ps
CPU time 0.87 seconds
Started Jul 11 05:47:32 PM PDT 24
Finished Jul 11 05:47:37 PM PDT 24
Peak memory 201616 kb
Host smart-2d26758c-3de9-460b-8342-a4ff764a264c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805488704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3805488704
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4037498418
Short name T875
Test name
Test status
Simulation time 503301740 ps
CPU time 2.01 seconds
Started Jul 11 05:47:23 PM PDT 24
Finished Jul 11 05:47:28 PM PDT 24
Peak memory 201556 kb
Host smart-c526af07-5fb0-4e55-98ec-6fe23ed2ac02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037498418 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4037498418
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2142951059
Short name T885
Test name
Test status
Simulation time 422844082 ps
CPU time 1.07 seconds
Started Jul 11 05:47:23 PM PDT 24
Finished Jul 11 05:47:26 PM PDT 24
Peak memory 201400 kb
Host smart-8e2d406f-289a-4495-a5f0-b10e70d9ea5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142951059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2142951059
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2884629894
Short name T812
Test name
Test status
Simulation time 304473343 ps
CPU time 0.99 seconds
Started Jul 11 05:47:23 PM PDT 24
Finished Jul 11 05:47:26 PM PDT 24
Peak memory 201444 kb
Host smart-7a67b16d-df35-413f-a9b8-cd631b940034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884629894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2884629894
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3153833170
Short name T58
Test name
Test status
Simulation time 4495027297 ps
CPU time 8.69 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:37 PM PDT 24
Peak memory 201816 kb
Host smart-0046c783-b766-4224-a7cb-01e4bc9ab53a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153833170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3153833170
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1225879512
Short name T874
Test name
Test status
Simulation time 603953301 ps
CPU time 3.1 seconds
Started Jul 11 05:47:22 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 218148 kb
Host smart-a5c5eacf-68cb-46e6-8c31-c11520117cae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225879512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1225879512
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3168195236
Short name T899
Test name
Test status
Simulation time 1199276351 ps
CPU time 4.66 seconds
Started Jul 11 05:47:38 PM PDT 24
Finished Jul 11 05:47:46 PM PDT 24
Peak memory 201648 kb
Host smart-5322a6a6-fb26-4f5c-ad18-7ff1079548e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168195236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3168195236
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1471956936
Short name T908
Test name
Test status
Simulation time 989396971 ps
CPU time 1.39 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:29 PM PDT 24
Peak memory 201508 kb
Host smart-1d149b2a-1f91-44f6-93c2-d6c88f709e73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471956936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1471956936
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1140948560
Short name T73
Test name
Test status
Simulation time 412374846 ps
CPU time 1.84 seconds
Started Jul 11 05:47:21 PM PDT 24
Finished Jul 11 05:47:25 PM PDT 24
Peak memory 201544 kb
Host smart-099acb04-a509-4987-a76d-67b90db79507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140948560 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1140948560
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.529516374
Short name T131
Test name
Test status
Simulation time 560187865 ps
CPU time 1.4 seconds
Started Jul 11 05:47:22 PM PDT 24
Finished Jul 11 05:47:26 PM PDT 24
Peak memory 201400 kb
Host smart-4e12fffb-e9da-4885-ac6b-ada9674c0a53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529516374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.529516374
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.286082754
Short name T905
Test name
Test status
Simulation time 428275245 ps
CPU time 1.67 seconds
Started Jul 11 05:47:21 PM PDT 24
Finished Jul 11 05:47:26 PM PDT 24
Peak memory 201372 kb
Host smart-4e58b8a9-c573-450d-a59a-6163f1c7e81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286082754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.286082754
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2354979850
Short name T834
Test name
Test status
Simulation time 4009135750 ps
CPU time 8.89 seconds
Started Jul 11 05:47:28 PM PDT 24
Finished Jul 11 05:47:39 PM PDT 24
Peak memory 201816 kb
Host smart-121df888-cd2a-4cd4-98b1-3c0e81a3930b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354979850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2354979850
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1567305786
Short name T83
Test name
Test status
Simulation time 7530192340 ps
CPU time 17.31 seconds
Started Jul 11 05:47:34 PM PDT 24
Finished Jul 11 05:47:56 PM PDT 24
Peak memory 201872 kb
Host smart-b8268142-6124-46d4-83a6-80f6755d689f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567305786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1567305786
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.207138758
Short name T832
Test name
Test status
Simulation time 565531856 ps
CPU time 1.35 seconds
Started Jul 11 05:47:33 PM PDT 24
Finished Jul 11 05:47:39 PM PDT 24
Peak memory 201544 kb
Host smart-48b58f81-e468-4783-9e85-986e13d75cca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207138758 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.207138758
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.72380143
Short name T861
Test name
Test status
Simulation time 336145940 ps
CPU time 0.91 seconds
Started Jul 11 05:47:39 PM PDT 24
Finished Jul 11 05:47:43 PM PDT 24
Peak memory 201520 kb
Host smart-089dcf16-9424-45d5-b53e-d39a92dcd382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72380143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.72380143
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1789730590
Short name T890
Test name
Test status
Simulation time 525333717 ps
CPU time 0.99 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:57 PM PDT 24
Peak memory 201400 kb
Host smart-3e4845b0-3b28-4f24-be75-d91b3c54c7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789730590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1789730590
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2461996899
Short name T912
Test name
Test status
Simulation time 5000389652 ps
CPU time 6.24 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:48:04 PM PDT 24
Peak memory 201804 kb
Host smart-c454e12b-7281-4f88-8b17-b5568c4d4faf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461996899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2461996899
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4252431659
Short name T856
Test name
Test status
Simulation time 741212040 ps
CPU time 2.16 seconds
Started Jul 11 05:47:37 PM PDT 24
Finished Jul 11 05:47:42 PM PDT 24
Peak memory 217644 kb
Host smart-597e778a-8698-4e79-a8ba-d0d35329167f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252431659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4252431659
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2388414204
Short name T897
Test name
Test status
Simulation time 8776954545 ps
CPU time 5.67 seconds
Started Jul 11 05:47:35 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 201820 kb
Host smart-522f86c1-c26e-4e3a-8b59-893a64cf3728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388414204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2388414204
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1108391956
Short name T830
Test name
Test status
Simulation time 543554470 ps
CPU time 1.52 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 209908 kb
Host smart-f0033822-8512-4656-b853-449f93cfcee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108391956 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1108391956
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2874011952
Short name T900
Test name
Test status
Simulation time 732654410 ps
CPU time 0.9 seconds
Started Jul 11 05:47:37 PM PDT 24
Finished Jul 11 05:47:42 PM PDT 24
Peak memory 201492 kb
Host smart-0a1345f8-ee71-40e9-adb8-ce6aa12af195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874011952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2874011952
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1937226055
Short name T919
Test name
Test status
Simulation time 298985766 ps
CPU time 0.77 seconds
Started Jul 11 05:47:33 PM PDT 24
Finished Jul 11 05:47:38 PM PDT 24
Peak memory 201440 kb
Host smart-792b073c-3136-40d8-a744-ae86b3e194a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937226055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1937226055
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1165394033
Short name T884
Test name
Test status
Simulation time 2458694759 ps
CPU time 5.98 seconds
Started Jul 11 05:47:39 PM PDT 24
Finished Jul 11 05:47:49 PM PDT 24
Peak memory 201644 kb
Host smart-a9546716-147e-4092-a4ce-94baa2ff5dba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165394033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1165394033
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3105322001
Short name T883
Test name
Test status
Simulation time 375216830 ps
CPU time 1.52 seconds
Started Jul 11 05:48:14 PM PDT 24
Finished Jul 11 05:48:21 PM PDT 24
Peak memory 201496 kb
Host smart-0b2d5f2e-e7ea-4a1b-a3cf-458e63cb65d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105322001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3105322001
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.930524872
Short name T891
Test name
Test status
Simulation time 5072222888 ps
CPU time 2.43 seconds
Started Jul 11 05:47:44 PM PDT 24
Finished Jul 11 05:47:49 PM PDT 24
Peak memory 201876 kb
Host smart-edf20ac5-b7a8-4a80-a989-718b658f1f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930524872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.930524872
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2211829096
Short name T877
Test name
Test status
Simulation time 417435326 ps
CPU time 1.73 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:57 PM PDT 24
Peak memory 201468 kb
Host smart-6da70357-c4e5-4675-b9b5-e78ba01c5c88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211829096 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2211829096
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.606223117
Short name T866
Test name
Test status
Simulation time 301447423 ps
CPU time 1.43 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:56 PM PDT 24
Peak memory 201512 kb
Host smart-35b28941-89d2-4650-a3c7-72869b6c76a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606223117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.606223117
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1252097127
Short name T849
Test name
Test status
Simulation time 319386913 ps
CPU time 0.97 seconds
Started Jul 11 05:47:45 PM PDT 24
Finished Jul 11 05:47:49 PM PDT 24
Peak memory 201444 kb
Host smart-13aaaa9a-b917-4b67-8c08-6bfee77497be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252097127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1252097127
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1369255988
Short name T879
Test name
Test status
Simulation time 1957037016 ps
CPU time 3.84 seconds
Started Jul 11 05:47:44 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 201520 kb
Host smart-d298ec1e-06f8-4e0e-83e1-d56a337645d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369255988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1369255988
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.101399867
Short name T917
Test name
Test status
Simulation time 422173918 ps
CPU time 3.56 seconds
Started Jul 11 05:47:38 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 201768 kb
Host smart-7c5caaae-20ed-4e15-b32f-fa6bfda9b5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101399867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.101399867
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4084730678
Short name T860
Test name
Test status
Simulation time 4099132955 ps
CPU time 6.19 seconds
Started Jul 11 05:47:39 PM PDT 24
Finished Jul 11 05:47:48 PM PDT 24
Peak memory 201892 kb
Host smart-938badb9-aa00-433c-900a-3e06ae8ad48a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084730678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4084730678
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.174934485
Short name T817
Test name
Test status
Simulation time 431947763 ps
CPU time 1.88 seconds
Started Jul 11 05:47:55 PM PDT 24
Finished Jul 11 05:48:03 PM PDT 24
Peak memory 201492 kb
Host smart-fbe6b65e-594f-4e7f-b0e3-2e516b0ca5ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174934485 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.174934485
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1183906577
Short name T129
Test name
Test status
Simulation time 445680636 ps
CPU time 1.73 seconds
Started Jul 11 05:47:47 PM PDT 24
Finished Jul 11 05:47:52 PM PDT 24
Peak memory 201496 kb
Host smart-b5f90c72-3faf-40a8-ba63-ecbf4a054b28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183906577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1183906577
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3884350245
Short name T809
Test name
Test status
Simulation time 444767132 ps
CPU time 0.87 seconds
Started Jul 11 05:47:54 PM PDT 24
Finished Jul 11 05:48:01 PM PDT 24
Peak memory 201452 kb
Host smart-87afaec8-fe3c-4f2b-9889-4979364827e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884350245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3884350245
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.989716825
Short name T135
Test name
Test status
Simulation time 4694250690 ps
CPU time 5.54 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 201864 kb
Host smart-a5b90052-c060-4cd2-bd5c-3581f3c25d09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989716825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.989716825
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1563891795
Short name T831
Test name
Test status
Simulation time 375215644 ps
CPU time 2.46 seconds
Started Jul 11 05:47:42 PM PDT 24
Finished Jul 11 05:47:47 PM PDT 24
Peak memory 201784 kb
Host smart-98173715-5b44-4bda-a0bf-82217c95be81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563891795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1563891795
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3287964671
Short name T84
Test name
Test status
Simulation time 8899004680 ps
CPU time 25.05 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:48:10 PM PDT 24
Peak memory 201972 kb
Host smart-a1776170-f905-4a9b-9630-71d442ac22c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287964671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3287964671
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2540058327
Short name T918
Test name
Test status
Simulation time 380744346 ps
CPU time 1.7 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201572 kb
Host smart-f661fad1-c372-4348-bb52-d7839af82bac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540058327 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2540058327
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2789666606
Short name T127
Test name
Test status
Simulation time 529603703 ps
CPU time 1.24 seconds
Started Jul 11 05:47:49 PM PDT 24
Finished Jul 11 05:47:53 PM PDT 24
Peak memory 201476 kb
Host smart-eed4673d-b4f7-4baf-aafa-e28b1f897af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789666606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2789666606
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3481317041
Short name T814
Test name
Test status
Simulation time 325130554 ps
CPU time 1.41 seconds
Started Jul 11 05:47:40 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 201408 kb
Host smart-f99db677-4530-44f4-a38f-34b9723659df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481317041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3481317041
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.415066910
Short name T823
Test name
Test status
Simulation time 4878020757 ps
CPU time 5.61 seconds
Started Jul 11 05:47:49 PM PDT 24
Finished Jul 11 05:47:58 PM PDT 24
Peak memory 201816 kb
Host smart-f4c9ba06-d4b8-4c3d-974a-5d360aed09f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415066910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.415066910
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3087559613
Short name T842
Test name
Test status
Simulation time 429432451 ps
CPU time 2.13 seconds
Started Jul 11 05:47:46 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 210008 kb
Host smart-6e81edb6-e9a5-4ebe-9dea-9219cabfcc37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087559613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3087559613
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.32453726
Short name T63
Test name
Test status
Simulation time 8268288524 ps
CPU time 11.28 seconds
Started Jul 11 05:47:54 PM PDT 24
Finished Jul 11 05:48:11 PM PDT 24
Peak memory 201852 kb
Host smart-b9ce02be-6113-452e-8a81-7b00229123df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32453726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_int
g_err.32453726
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2562501491
Short name T66
Test name
Test status
Simulation time 455810406 ps
CPU time 1.04 seconds
Started Jul 11 05:47:49 PM PDT 24
Finished Jul 11 05:47:53 PM PDT 24
Peak memory 201572 kb
Host smart-07de4680-dbde-4615-a558-26e5de72f326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562501491 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2562501491
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.720643323
Short name T851
Test name
Test status
Simulation time 348528950 ps
CPU time 1.12 seconds
Started Jul 11 05:47:45 PM PDT 24
Finished Jul 11 05:47:49 PM PDT 24
Peak memory 201688 kb
Host smart-d4effc3d-ccb5-44e5-a1df-fcb118e5fed1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720643323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.720643323
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.427052369
Short name T869
Test name
Test status
Simulation time 519156569 ps
CPU time 1.73 seconds
Started Jul 11 05:48:10 PM PDT 24
Finished Jul 11 05:48:18 PM PDT 24
Peak memory 201396 kb
Host smart-a8b39b76-8901-49c9-9ba0-748caae3a530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427052369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.427052369
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1265384125
Short name T852
Test name
Test status
Simulation time 2418540877 ps
CPU time 4.59 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:48:02 PM PDT 24
Peak memory 201636 kb
Host smart-c96c3a85-b6f3-4c13-9ab5-a6fbb8c335a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265384125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1265384125
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1157262495
Short name T72
Test name
Test status
Simulation time 684350162 ps
CPU time 2.68 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:58 PM PDT 24
Peak memory 217656 kb
Host smart-505b7f5e-4a12-43d0-85df-68c297de2520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157262495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1157262495
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3640166439
Short name T813
Test name
Test status
Simulation time 4386288846 ps
CPU time 5.05 seconds
Started Jul 11 05:47:47 PM PDT 24
Finished Jul 11 05:47:55 PM PDT 24
Peak memory 201860 kb
Host smart-859728ef-e6bd-4988-9797-35df8dc56cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640166439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3640166439
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.109896107
Short name T99
Test name
Test status
Simulation time 773133270 ps
CPU time 1.12 seconds
Started Jul 11 05:47:49 PM PDT 24
Finished Jul 11 05:47:53 PM PDT 24
Peak memory 201536 kb
Host smart-c3eab37b-9f76-4efd-b8b7-f55270eee102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109896107 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.109896107
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.74459999
Short name T867
Test name
Test status
Simulation time 456657960 ps
CPU time 1.8 seconds
Started Jul 11 05:48:10 PM PDT 24
Finished Jul 11 05:48:18 PM PDT 24
Peak memory 201476 kb
Host smart-77e56d1e-31b5-417e-970e-e386d44b35c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74459999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.74459999
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3405082477
Short name T854
Test name
Test status
Simulation time 451411579 ps
CPU time 1.1 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:56 PM PDT 24
Peak memory 201308 kb
Host smart-1d885194-64d4-45da-9946-b6c052463e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405082477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3405082477
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4116863077
Short name T833
Test name
Test status
Simulation time 2320893742 ps
CPU time 9.22 seconds
Started Jul 11 05:47:44 PM PDT 24
Finished Jul 11 05:47:56 PM PDT 24
Peak memory 201592 kb
Host smart-2d33ac1e-449f-42cc-9b4e-912c0f23d0bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116863077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4116863077
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.614716652
Short name T894
Test name
Test status
Simulation time 378843033 ps
CPU time 2.11 seconds
Started Jul 11 05:48:07 PM PDT 24
Finished Jul 11 05:48:16 PM PDT 24
Peak memory 201772 kb
Host smart-fe9b8bd6-4878-4aed-8d03-d75febad2680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614716652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.614716652
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3748401195
Short name T76
Test name
Test status
Simulation time 4087374494 ps
CPU time 3.95 seconds
Started Jul 11 05:47:45 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 201808 kb
Host smart-8e24a2b1-160f-4583-99a0-0935eedfc5fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748401195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3748401195
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.441943873
Short name T881
Test name
Test status
Simulation time 572432937 ps
CPU time 1.5 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 209988 kb
Host smart-f3585706-ed30-4845-b04e-5e2e88bbc769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441943873 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.441943873
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2316827363
Short name T125
Test name
Test status
Simulation time 467180288 ps
CPU time 1.82 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:58 PM PDT 24
Peak memory 201464 kb
Host smart-fc61d268-96c0-4e59-8913-32af0206d233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316827363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2316827363
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2029869546
Short name T802
Test name
Test status
Simulation time 615395004 ps
CPU time 0.8 seconds
Started Jul 11 05:48:10 PM PDT 24
Finished Jul 11 05:48:17 PM PDT 24
Peak memory 201400 kb
Host smart-2c9a71d1-9a64-4638-8064-efa62081b713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029869546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2029869546
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1311238110
Short name T846
Test name
Test status
Simulation time 4493243219 ps
CPU time 21.88 seconds
Started Jul 11 05:48:07 PM PDT 24
Finished Jul 11 05:48:36 PM PDT 24
Peak memory 201848 kb
Host smart-79002c1b-9abb-4a17-8745-81bb3e098cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311238110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1311238110
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2012105497
Short name T80
Test name
Test status
Simulation time 457416391 ps
CPU time 3.11 seconds
Started Jul 11 05:47:41 PM PDT 24
Finished Jul 11 05:47:47 PM PDT 24
Peak memory 201748 kb
Host smart-1aed714d-a097-4eaf-a20b-a7900605d699
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012105497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2012105497
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2520418889
Short name T62
Test name
Test status
Simulation time 8723525854 ps
CPU time 10.5 seconds
Started Jul 11 05:48:07 PM PDT 24
Finished Jul 11 05:48:24 PM PDT 24
Peak memory 201784 kb
Host smart-152bb5cb-7d55-4b6f-b4bc-6f7ad8985140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520418889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2520418889
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4233514386
Short name T100
Test name
Test status
Simulation time 513592990 ps
CPU time 1.54 seconds
Started Jul 11 05:47:45 PM PDT 24
Finished Jul 11 05:47:49 PM PDT 24
Peak memory 201520 kb
Host smart-c9e57d9b-abf5-4412-9e81-5052f4b1f4a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233514386 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.4233514386
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1146023949
Short name T898
Test name
Test status
Simulation time 441908132 ps
CPU time 1.74 seconds
Started Jul 11 05:47:55 PM PDT 24
Finished Jul 11 05:48:03 PM PDT 24
Peak memory 201512 kb
Host smart-479290e6-a192-4ace-b08c-885501d540aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146023949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1146023949
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.39960803
Short name T847
Test name
Test status
Simulation time 290118557 ps
CPU time 0.99 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:54 PM PDT 24
Peak memory 201416 kb
Host smart-3c558a41-8eef-4da7-9960-7bf7d161bab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.39960803
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4124503
Short name T910
Test name
Test status
Simulation time 2373615426 ps
CPU time 2.13 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:57 PM PDT 24
Peak memory 201636 kb
Host smart-2df8601b-e6f0-47bf-8bcb-a8667842bd35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctr
l_same_csr_outstanding.4124503
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4042122221
Short name T895
Test name
Test status
Simulation time 444075874 ps
CPU time 2.99 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:48 PM PDT 24
Peak memory 201764 kb
Host smart-ee3d2abf-6cc2-40d0-9dea-89f87324db36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042122221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4042122221
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.264803100
Short name T857
Test name
Test status
Simulation time 8259689906 ps
CPU time 4.97 seconds
Started Jul 11 05:47:44 PM PDT 24
Finished Jul 11 05:47:52 PM PDT 24
Peak memory 201860 kb
Host smart-05d6c494-23cb-4e93-a543-937f4d9a532b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264803100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.264803100
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3362807927
Short name T855
Test name
Test status
Simulation time 633762759 ps
CPU time 1.32 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:56 PM PDT 24
Peak memory 201748 kb
Host smart-ddf29adc-a537-461d-8fe3-85b935668f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362807927 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3362807927
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2350360157
Short name T862
Test name
Test status
Simulation time 597302813 ps
CPU time 0.99 seconds
Started Jul 11 05:47:48 PM PDT 24
Finished Jul 11 05:47:52 PM PDT 24
Peak memory 201520 kb
Host smart-f0c895f2-509d-40dd-a067-dc7b3f8c2228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350360157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2350360157
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1255221948
Short name T810
Test name
Test status
Simulation time 327165143 ps
CPU time 1.34 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201360 kb
Host smart-c1406444-0135-4e90-a877-8dbe70aaf516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255221948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1255221948
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2005135470
Short name T893
Test name
Test status
Simulation time 1760154337 ps
CPU time 2.63 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:48:00 PM PDT 24
Peak memory 201512 kb
Host smart-d8e73e1e-d8b6-4e9a-98a1-2cb97726a754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005135470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2005135470
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4287192228
Short name T909
Test name
Test status
Simulation time 589162200 ps
CPU time 1.75 seconds
Started Jul 11 05:47:42 PM PDT 24
Finished Jul 11 05:47:47 PM PDT 24
Peak memory 201832 kb
Host smart-0bf07f6d-5d15-436b-ad8b-ef037530724f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287192228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4287192228
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2235611332
Short name T122
Test name
Test status
Simulation time 1150032201 ps
CPU time 2.81 seconds
Started Jul 11 05:47:36 PM PDT 24
Finished Jul 11 05:47:42 PM PDT 24
Peak memory 201756 kb
Host smart-3a2a4190-6e25-4183-a5d9-27650466f3f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235611332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2235611332
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2576664040
Short name T138
Test name
Test status
Simulation time 27000907597 ps
CPU time 129.56 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:49:44 PM PDT 24
Peak memory 201860 kb
Host smart-75888604-0089-40ce-9ca4-f78bd90decb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576664040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2576664040
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2878400918
Short name T137
Test name
Test status
Simulation time 1286566080 ps
CPU time 1.6 seconds
Started Jul 11 05:47:27 PM PDT 24
Finished Jul 11 05:47:31 PM PDT 24
Peak memory 201520 kb
Host smart-e6e5c54b-dca2-4533-a08a-324f8143584b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878400918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2878400918
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4040413090
Short name T914
Test name
Test status
Simulation time 479422042 ps
CPU time 1.23 seconds
Started Jul 11 05:47:28 PM PDT 24
Finished Jul 11 05:47:31 PM PDT 24
Peak memory 201744 kb
Host smart-d2bb0d45-2755-4150-ba6f-aeca239ce61f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040413090 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4040413090
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1902892319
Short name T901
Test name
Test status
Simulation time 542546562 ps
CPU time 1.36 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 201520 kb
Host smart-0ae7113c-790b-4f09-bb45-60ed1b504dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902892319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1902892319
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3899470314
Short name T920
Test name
Test status
Simulation time 481584758 ps
CPU time 0.94 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 201336 kb
Host smart-89ca829e-2c24-4cc2-a85d-fc7efc0bb1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899470314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3899470314
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.824719753
Short name T132
Test name
Test status
Simulation time 2648943894 ps
CPU time 6.73 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:40 PM PDT 24
Peak memory 201636 kb
Host smart-3cffccb4-e287-4b28-a5ab-0b70b5caab36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824719753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.824719753
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.832586794
Short name T904
Test name
Test status
Simulation time 502891841 ps
CPU time 3.5 seconds
Started Jul 11 05:47:32 PM PDT 24
Finished Jul 11 05:47:39 PM PDT 24
Peak memory 201900 kb
Host smart-e61c5ea6-bbd9-44fd-8fde-d7de3373b72c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832586794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.832586794
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1164639221
Short name T853
Test name
Test status
Simulation time 8331451834 ps
CPU time 22.68 seconds
Started Jul 11 05:47:29 PM PDT 24
Finished Jul 11 05:47:53 PM PDT 24
Peak memory 201824 kb
Host smart-ee62bc8b-bc73-4559-af7a-9bcd461d9ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164639221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1164639221
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2192847519
Short name T799
Test name
Test status
Simulation time 291429228 ps
CPU time 1.34 seconds
Started Jul 11 05:47:58 PM PDT 24
Finished Jul 11 05:48:05 PM PDT 24
Peak memory 201436 kb
Host smart-ee462c8b-ec40-45d9-a558-cc3ec2473c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192847519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2192847519
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4125584176
Short name T807
Test name
Test status
Simulation time 465100387 ps
CPU time 1.1 seconds
Started Jul 11 05:48:11 PM PDT 24
Finished Jul 11 05:48:18 PM PDT 24
Peak memory 201368 kb
Host smart-5fcd3cac-a69c-4294-96f0-82ef3fdb87fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125584176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4125584176
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.734743635
Short name T816
Test name
Test status
Simulation time 459402187 ps
CPU time 1.16 seconds
Started Jul 11 05:48:00 PM PDT 24
Finished Jul 11 05:48:06 PM PDT 24
Peak memory 201408 kb
Host smart-6852218f-5562-4c77-9048-4663d53b1b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734743635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.734743635
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1068343814
Short name T818
Test name
Test status
Simulation time 529066138 ps
CPU time 1.28 seconds
Started Jul 11 05:48:05 PM PDT 24
Finished Jul 11 05:48:13 PM PDT 24
Peak memory 201396 kb
Host smart-d2619284-92d1-4a11-89ae-3cd2d8296dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068343814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1068343814
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2851027354
Short name T839
Test name
Test status
Simulation time 344804686 ps
CPU time 0.82 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:56 PM PDT 24
Peak memory 201428 kb
Host smart-72929fb9-9439-47e4-a455-d01f8d7c5763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851027354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2851027354
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.463982211
Short name T837
Test name
Test status
Simulation time 569086048 ps
CPU time 0.75 seconds
Started Jul 11 05:48:00 PM PDT 24
Finished Jul 11 05:48:06 PM PDT 24
Peak memory 201312 kb
Host smart-8dcdb81c-beb2-45b6-b2b4-f7a4f0f8ff66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463982211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.463982211
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2092622956
Short name T848
Test name
Test status
Simulation time 444977093 ps
CPU time 0.86 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:58 PM PDT 24
Peak memory 201420 kb
Host smart-e1dfdc93-7164-4fe8-8945-1e3459766565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092622956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2092622956
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2718744807
Short name T801
Test name
Test status
Simulation time 531402743 ps
CPU time 1.83 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201388 kb
Host smart-05cfb22e-248f-4a1b-bfa1-6976609979c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718744807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2718744807
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3139832173
Short name T820
Test name
Test status
Simulation time 288163678 ps
CPU time 1.34 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201416 kb
Host smart-2c9482f1-5fa8-4140-b8a2-e2d6d35ff830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139832173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3139832173
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3594779970
Short name T805
Test name
Test status
Simulation time 354160442 ps
CPU time 0.84 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:54 PM PDT 24
Peak memory 201416 kb
Host smart-2a4c7944-6db9-418d-9417-581f7b0ec226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594779970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3594779970
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1418179774
Short name T915
Test name
Test status
Simulation time 740612050 ps
CPU time 2.95 seconds
Started Jul 11 05:47:53 PM PDT 24
Finished Jul 11 05:48:01 PM PDT 24
Peak memory 201660 kb
Host smart-c54e72c2-fe5e-42ca-9b4e-0fa48a788075
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418179774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1418179774
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4140090833
Short name T57
Test name
Test status
Simulation time 26348693967 ps
CPU time 29.39 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:48:03 PM PDT 24
Peak memory 201860 kb
Host smart-9d8e648b-bcb3-4862-b00c-255262fe269b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140090833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.4140090833
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.795459089
Short name T123
Test name
Test status
Simulation time 624287386 ps
CPU time 2.03 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:36 PM PDT 24
Peak memory 201488 kb
Host smart-7d12f8c8-e358-42d7-8f8a-07fe3675e490
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795459089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.795459089
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3672042321
Short name T77
Test name
Test status
Simulation time 679142416 ps
CPU time 1.32 seconds
Started Jul 11 05:47:33 PM PDT 24
Finished Jul 11 05:47:38 PM PDT 24
Peak memory 201548 kb
Host smart-468487f8-5e08-4fc8-af0c-978000cc344d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672042321 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3672042321
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3423308159
Short name T829
Test name
Test status
Simulation time 475262499 ps
CPU time 0.98 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:46 PM PDT 24
Peak memory 201508 kb
Host smart-f6752a45-a698-484c-8768-6ee93e3a416a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423308159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3423308159
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4007903091
Short name T840
Test name
Test status
Simulation time 323398984 ps
CPU time 0.82 seconds
Started Jul 11 05:47:36 PM PDT 24
Finished Jul 11 05:47:41 PM PDT 24
Peak memory 201352 kb
Host smart-d5f0cfe9-ec07-4088-82d6-db06f918fe62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007903091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4007903091
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4151748549
Short name T903
Test name
Test status
Simulation time 2512667478 ps
CPU time 8.67 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:47:41 PM PDT 24
Peak memory 201648 kb
Host smart-8a02ade8-4797-4042-872c-4c96baabe87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151748549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4151748549
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1887775984
Short name T82
Test name
Test status
Simulation time 440694107 ps
CPU time 1.84 seconds
Started Jul 11 05:47:32 PM PDT 24
Finished Jul 11 05:47:37 PM PDT 24
Peak memory 201720 kb
Host smart-06a8c356-2018-4157-aa94-05e011c3741d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887775984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1887775984
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.71096065
Short name T872
Test name
Test status
Simulation time 5030293096 ps
CPU time 4.11 seconds
Started Jul 11 05:47:34 PM PDT 24
Finished Jul 11 05:47:42 PM PDT 24
Peak memory 201800 kb
Host smart-0f0ed71e-9981-45dd-8961-c8a49447a3e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71096065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg
_err.71096065
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1543394563
Short name T843
Test name
Test status
Simulation time 352294838 ps
CPU time 1.47 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:55 PM PDT 24
Peak memory 201444 kb
Host smart-d3edf8de-64dd-489c-aad3-2bbcdb13954c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543394563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1543394563
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3080045606
Short name T841
Test name
Test status
Simulation time 347344641 ps
CPU time 0.85 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201544 kb
Host smart-6a9cab23-49a2-4d5e-9b62-e57b35909320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080045606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3080045606
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1369089248
Short name T871
Test name
Test status
Simulation time 420629987 ps
CPU time 0.86 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201416 kb
Host smart-5940aa59-fc98-4d93-b52b-d20fe3cdf579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369089248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1369089248
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1299424745
Short name T868
Test name
Test status
Simulation time 416493691 ps
CPU time 1.56 seconds
Started Jul 11 05:48:00 PM PDT 24
Finished Jul 11 05:48:07 PM PDT 24
Peak memory 201332 kb
Host smart-3c7c6b60-19e2-4a6c-90ef-ae08289f628d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299424745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1299424745
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1617233179
Short name T858
Test name
Test status
Simulation time 293366505 ps
CPU time 0.92 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:58 PM PDT 24
Peak memory 201412 kb
Host smart-9516097e-e7fa-4ed5-9fde-1dea4cda5c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617233179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1617233179
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1910741557
Short name T887
Test name
Test status
Simulation time 377696526 ps
CPU time 1.47 seconds
Started Jul 11 05:47:49 PM PDT 24
Finished Jul 11 05:47:53 PM PDT 24
Peak memory 201432 kb
Host smart-25570825-9625-40a5-8894-d71cb6a09d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910741557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1910741557
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.11080004
Short name T804
Test name
Test status
Simulation time 424771743 ps
CPU time 0.87 seconds
Started Jul 11 05:47:47 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 201636 kb
Host smart-3b9f47ce-d54c-4cd9-9d94-e0bb36d1a454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11080004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.11080004
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.871121415
Short name T808
Test name
Test status
Simulation time 417779319 ps
CPU time 1.54 seconds
Started Jul 11 05:47:46 PM PDT 24
Finished Jul 11 05:47:50 PM PDT 24
Peak memory 201428 kb
Host smart-8c3dc487-8dcc-431f-89a5-57b5b9cff1d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871121415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.871121415
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4287549769
Short name T888
Test name
Test status
Simulation time 310116147 ps
CPU time 0.98 seconds
Started Jul 11 05:47:56 PM PDT 24
Finished Jul 11 05:48:02 PM PDT 24
Peak memory 201444 kb
Host smart-06451dde-fe36-47fb-852d-bd8ec67002a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287549769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.4287549769
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2065389683
Short name T803
Test name
Test status
Simulation time 305788017 ps
CPU time 1.01 seconds
Started Jul 11 05:47:54 PM PDT 24
Finished Jul 11 05:48:01 PM PDT 24
Peak memory 201392 kb
Host smart-b4f7a7a4-cd24-4878-948e-f1af2f2777ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065389683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2065389683
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1165897600
Short name T126
Test name
Test status
Simulation time 920213900 ps
CPU time 4.62 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:47:38 PM PDT 24
Peak memory 201708 kb
Host smart-496eeff1-63bb-40cd-878a-b9c7eeb4c4ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165897600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1165897600
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1117524086
Short name T128
Test name
Test status
Simulation time 45983413407 ps
CPU time 94.89 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:49:07 PM PDT 24
Peak memory 201816 kb
Host smart-2371e58d-a758-4d62-b833-ef450233e2ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117524086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1117524086
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2916531129
Short name T906
Test name
Test status
Simulation time 882602328 ps
CPU time 0.9 seconds
Started Jul 11 05:47:35 PM PDT 24
Finished Jul 11 05:47:40 PM PDT 24
Peak memory 201492 kb
Host smart-3c5b949c-6539-46d4-a6b1-7cce08cfa867
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916531129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2916531129
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.590434736
Short name T98
Test name
Test status
Simulation time 446503631 ps
CPU time 1.77 seconds
Started Jul 11 05:47:29 PM PDT 24
Finished Jul 11 05:47:33 PM PDT 24
Peak memory 201596 kb
Host smart-ea00ff42-b3e6-451d-9a33-6c4c169e3ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590434736 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.590434736
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.271016997
Short name T120
Test name
Test status
Simulation time 508195464 ps
CPU time 1.38 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:36 PM PDT 24
Peak memory 201520 kb
Host smart-18191f8f-31e1-47a1-9c88-7f524aca1580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271016997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.271016997
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1184527144
Short name T882
Test name
Test status
Simulation time 410973375 ps
CPU time 1.58 seconds
Started Jul 11 05:47:29 PM PDT 24
Finished Jul 11 05:47:33 PM PDT 24
Peak memory 201640 kb
Host smart-124d781c-254a-414b-87ad-9bbb5e6c3d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184527144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1184527144
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.462898143
Short name T59
Test name
Test status
Simulation time 4939877256 ps
CPU time 12.61 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 201828 kb
Host smart-ddce4e32-11f3-4545-975b-ede07f18d4ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462898143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.462898143
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.4219448919
Short name T822
Test name
Test status
Simulation time 466107467 ps
CPU time 2.48 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:47:36 PM PDT 24
Peak memory 201804 kb
Host smart-51257c4f-47b4-4cfa-a2dc-d303d95d3ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219448919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.4219448919
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2665717144
Short name T75
Test name
Test status
Simulation time 8356008309 ps
CPU time 22.57 seconds
Started Jul 11 05:47:34 PM PDT 24
Finished Jul 11 05:48:00 PM PDT 24
Peak memory 201776 kb
Host smart-86f34500-1091-4ad9-876a-22bf14e4f3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665717144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2665717144
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.468254673
Short name T916
Test name
Test status
Simulation time 299921395 ps
CPU time 1 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:55 PM PDT 24
Peak memory 201320 kb
Host smart-7163d4fb-e13a-49dd-bbd9-072dd512fb5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468254673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.468254673
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.916510422
Short name T819
Test name
Test status
Simulation time 324590397 ps
CPU time 0.79 seconds
Started Jul 11 05:47:55 PM PDT 24
Finished Jul 11 05:48:02 PM PDT 24
Peak memory 201444 kb
Host smart-86924ef5-5433-4d27-9cb0-d4c712b2737c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916510422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.916510422
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.726004622
Short name T880
Test name
Test status
Simulation time 390762511 ps
CPU time 1.5 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201392 kb
Host smart-2a0cb0f9-10f3-444e-ac46-97af2430957f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726004622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.726004622
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1111475635
Short name T907
Test name
Test status
Simulation time 309376678 ps
CPU time 1.19 seconds
Started Jul 11 05:47:58 PM PDT 24
Finished Jul 11 05:48:05 PM PDT 24
Peak memory 201388 kb
Host smart-bd86ddf1-1d4c-47b6-a78a-e9d1db217ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111475635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1111475635
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2451786228
Short name T886
Test name
Test status
Simulation time 400388535 ps
CPU time 1.59 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:55 PM PDT 24
Peak memory 201440 kb
Host smart-12fcfe5b-bf9b-4357-9202-3c5f725293de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451786228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2451786228
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.908100497
Short name T902
Test name
Test status
Simulation time 316554539 ps
CPU time 0.82 seconds
Started Jul 11 05:47:49 PM PDT 24
Finished Jul 11 05:47:54 PM PDT 24
Peak memory 201412 kb
Host smart-85e9e018-26af-481a-8d94-071f8a2ef234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908100497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.908100497
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1154922835
Short name T876
Test name
Test status
Simulation time 375442066 ps
CPU time 1.51 seconds
Started Jul 11 05:47:52 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201444 kb
Host smart-610d0982-3f5f-4229-a54c-0f9e015d4ce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154922835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1154922835
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2623514106
Short name T863
Test name
Test status
Simulation time 399225129 ps
CPU time 0.71 seconds
Started Jul 11 05:47:50 PM PDT 24
Finished Jul 11 05:47:55 PM PDT 24
Peak memory 201424 kb
Host smart-f6615a30-e926-4267-845d-55e10e15d6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623514106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2623514106
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.694179707
Short name T838
Test name
Test status
Simulation time 310024802 ps
CPU time 1 seconds
Started Jul 11 05:47:54 PM PDT 24
Finished Jul 11 05:48:01 PM PDT 24
Peak memory 201428 kb
Host smart-3c204e1d-0466-460f-a0bc-c12cea909e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694179707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.694179707
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2355176820
Short name T845
Test name
Test status
Simulation time 387447225 ps
CPU time 0.87 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:57 PM PDT 24
Peak memory 201408 kb
Host smart-90371d5e-9ec8-45a9-a982-e7072fea88e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355176820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2355176820
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1494235308
Short name T824
Test name
Test status
Simulation time 411727429 ps
CPU time 1.07 seconds
Started Jul 11 05:47:32 PM PDT 24
Finished Jul 11 05:47:37 PM PDT 24
Peak memory 201580 kb
Host smart-082737fc-9142-4c4e-9f91-d5b56bee42d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494235308 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1494235308
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.841238512
Short name T825
Test name
Test status
Simulation time 360576148 ps
CPU time 1.63 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 201516 kb
Host smart-b40192c8-cf0c-46cf-96cb-79546126d54f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841238512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.841238512
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1931849907
Short name T806
Test name
Test status
Simulation time 501487964 ps
CPU time 1.03 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 201384 kb
Host smart-0d7ef2d6-6f15-4afd-85e5-69cd848f6fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931849907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1931849907
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.450321771
Short name T134
Test name
Test status
Simulation time 3044782809 ps
CPU time 9.97 seconds
Started Jul 11 05:47:29 PM PDT 24
Finished Jul 11 05:47:40 PM PDT 24
Peak memory 201848 kb
Host smart-515faf08-a25a-423b-ba89-b54269d35866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450321771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.450321771
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2454353588
Short name T79
Test name
Test status
Simulation time 622533924 ps
CPU time 1.8 seconds
Started Jul 11 05:47:34 PM PDT 24
Finished Jul 11 05:47:40 PM PDT 24
Peak memory 209928 kb
Host smart-3661d268-eada-4dc4-8a13-001314b9958e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454353588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2454353588
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3839816724
Short name T827
Test name
Test status
Simulation time 4292020764 ps
CPU time 11.32 seconds
Started Jul 11 05:47:53 PM PDT 24
Finished Jul 11 05:48:10 PM PDT 24
Peak memory 201780 kb
Host smart-1b30ee06-5afb-4842-a20b-b615b8aea6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839816724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3839816724
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3569733701
Short name T815
Test name
Test status
Simulation time 346018145 ps
CPU time 1.19 seconds
Started Jul 11 05:48:13 PM PDT 24
Finished Jul 11 05:48:19 PM PDT 24
Peak memory 201504 kb
Host smart-9ca09e52-882b-438c-b047-e48dea5c4a73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569733701 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3569733701
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2895192317
Short name T859
Test name
Test status
Simulation time 533471420 ps
CPU time 1.25 seconds
Started Jul 11 05:47:41 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 201464 kb
Host smart-785435d1-8601-4fa4-901b-ec43ac6cfc6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895192317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2895192317
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2408618677
Short name T870
Test name
Test status
Simulation time 435204089 ps
CPU time 0.76 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 201448 kb
Host smart-df1a4a21-441e-445e-abfa-19a6a3e86248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408618677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2408618677
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2206106138
Short name T133
Test name
Test status
Simulation time 4369749342 ps
CPU time 5.18 seconds
Started Jul 11 05:47:35 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 201772 kb
Host smart-5b3d699a-87cc-4e16-8b7f-c4df04eac222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206106138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2206106138
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2157557929
Short name T836
Test name
Test status
Simulation time 495734174 ps
CPU time 1.84 seconds
Started Jul 11 05:47:30 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 201780 kb
Host smart-86790460-5aa8-4d05-b675-e24288abb734
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157557929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2157557929
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.606233213
Short name T878
Test name
Test status
Simulation time 4474375495 ps
CPU time 11.28 seconds
Started Jul 11 05:47:36 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 201792 kb
Host smart-b3c828e3-f87b-4b74-b725-90b32f4368bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606233213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.606233213
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.236270768
Short name T811
Test name
Test status
Simulation time 486341195 ps
CPU time 1.17 seconds
Started Jul 11 05:47:40 PM PDT 24
Finished Jul 11 05:47:44 PM PDT 24
Peak memory 201560 kb
Host smart-5f4d81de-91e5-401b-826c-2e88d6908382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236270768 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.236270768
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.313872072
Short name T826
Test name
Test status
Simulation time 456116925 ps
CPU time 0.81 seconds
Started Jul 11 05:47:33 PM PDT 24
Finished Jul 11 05:47:39 PM PDT 24
Peak memory 201432 kb
Host smart-5fcf8789-b94c-4ff6-8ae5-6794f2a64a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313872072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.313872072
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3142697286
Short name T913
Test name
Test status
Simulation time 4518416441 ps
CPU time 2.13 seconds
Started Jul 11 05:47:51 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 201860 kb
Host smart-bc4d828f-23ca-4e17-86e8-64c457618fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142697286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3142697286
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3970861769
Short name T896
Test name
Test status
Simulation time 4223595780 ps
CPU time 10.48 seconds
Started Jul 11 05:47:35 PM PDT 24
Finished Jul 11 05:47:50 PM PDT 24
Peak memory 202016 kb
Host smart-935feb85-99d4-4d86-83b8-19d2e52e371f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970861769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3970861769
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.837574025
Short name T81
Test name
Test status
Simulation time 425546458 ps
CPU time 1.81 seconds
Started Jul 11 05:47:47 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 201552 kb
Host smart-6303cc22-9c67-4c38-9e03-68ed434da49d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837574025 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.837574025
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2775728836
Short name T864
Test name
Test status
Simulation time 444164960 ps
CPU time 1.78 seconds
Started Jul 11 05:47:37 PM PDT 24
Finished Jul 11 05:47:42 PM PDT 24
Peak memory 201508 kb
Host smart-2d5578ba-cf09-4928-8c46-20070697d02f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775728836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2775728836
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.404344628
Short name T800
Test name
Test status
Simulation time 413294039 ps
CPU time 0.9 seconds
Started Jul 11 05:47:47 PM PDT 24
Finished Jul 11 05:47:51 PM PDT 24
Peak memory 201416 kb
Host smart-4690fe01-fbe5-4505-8bb8-8e89499ce7a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404344628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.404344628
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.893276037
Short name T136
Test name
Test status
Simulation time 2479370102 ps
CPU time 3.16 seconds
Started Jul 11 05:47:38 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 201616 kb
Host smart-2e707973-5b72-4ee1-a6fc-bdb1bdb059f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893276037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.893276037
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.334280083
Short name T828
Test name
Test status
Simulation time 434423865 ps
CPU time 2.44 seconds
Started Jul 11 05:48:14 PM PDT 24
Finished Jul 11 05:48:22 PM PDT 24
Peak memory 201712 kb
Host smart-dc40fafd-c259-4528-a12c-9843447f50ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334280083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.334280083
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1828640658
Short name T835
Test name
Test status
Simulation time 4509661560 ps
CPU time 11.04 seconds
Started Jul 11 05:47:38 PM PDT 24
Finished Jul 11 05:47:52 PM PDT 24
Peak memory 201792 kb
Host smart-e826add7-8401-48b0-a0d1-579327ad946b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828640658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1828640658
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1794641778
Short name T850
Test name
Test status
Simulation time 582445585 ps
CPU time 2.16 seconds
Started Jul 11 05:47:35 PM PDT 24
Finished Jul 11 05:47:41 PM PDT 24
Peak memory 201560 kb
Host smart-392c53c7-732c-4082-9385-8847fe5aa72b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794641778 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1794641778
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3754331588
Short name T892
Test name
Test status
Simulation time 499882633 ps
CPU time 1.35 seconds
Started Jul 11 05:47:53 PM PDT 24
Finished Jul 11 05:48:00 PM PDT 24
Peak memory 201520 kb
Host smart-5bc710ac-a878-4ba5-9a6d-526b840f4b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754331588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3754331588
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2012904749
Short name T821
Test name
Test status
Simulation time 310652977 ps
CPU time 0.8 seconds
Started Jul 11 05:48:14 PM PDT 24
Finished Jul 11 05:48:20 PM PDT 24
Peak memory 201368 kb
Host smart-f238aaea-9bff-4ed9-9f82-e8c9cb4dcfa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012904749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2012904749
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1853788835
Short name T889
Test name
Test status
Simulation time 3157963864 ps
CPU time 2.51 seconds
Started Jul 11 05:47:34 PM PDT 24
Finished Jul 11 05:47:41 PM PDT 24
Peak memory 201852 kb
Host smart-2936492b-9b93-4c3f-b026-72fe83f55d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853788835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1853788835
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1066341097
Short name T873
Test name
Test status
Simulation time 721021818 ps
CPU time 2.31 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:47 PM PDT 24
Peak memory 201760 kb
Host smart-6568ff11-10ba-40c6-b0be-c53f73240b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066341097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1066341097
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3246958695
Short name T844
Test name
Test status
Simulation time 4636019234 ps
CPU time 6.93 seconds
Started Jul 11 05:59:19 PM PDT 24
Finished Jul 11 05:59:35 PM PDT 24
Peak memory 201808 kb
Host smart-cdafb621-f58f-4422-8f6b-e28d8b078ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246958695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3246958695
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2960147274
Short name T778
Test name
Test status
Simulation time 374860079 ps
CPU time 0.82 seconds
Started Jul 11 05:48:15 PM PDT 24
Finished Jul 11 05:48:21 PM PDT 24
Peak memory 201652 kb
Host smart-cb6cd5aa-c0cc-492c-8135-bea79960a72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960147274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2960147274
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4010543309
Short name T139
Test name
Test status
Simulation time 367906651568 ps
CPU time 509.19 seconds
Started Jul 11 05:48:30 PM PDT 24
Finished Jul 11 05:57:02 PM PDT 24
Peak memory 201960 kb
Host smart-34f9bfb7-da42-49e9-a28d-9a46861b6993
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010543309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4010543309
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.206313314
Short name T273
Test name
Test status
Simulation time 360513480863 ps
CPU time 409.84 seconds
Started Jul 11 05:48:18 PM PDT 24
Finished Jul 11 05:55:14 PM PDT 24
Peak memory 201996 kb
Host smart-1c449f5e-c88b-4eb1-af44-14c3fb1205af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206313314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.206313314
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3178584077
Short name T637
Test name
Test status
Simulation time 492951058051 ps
CPU time 260.82 seconds
Started Jul 11 05:48:47 PM PDT 24
Finished Jul 11 05:53:11 PM PDT 24
Peak memory 201932 kb
Host smart-e455d905-9698-4e23-ba81-b24091a8d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178584077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3178584077
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2717411698
Short name T715
Test name
Test status
Simulation time 488167226822 ps
CPU time 279.91 seconds
Started Jul 11 05:48:17 PM PDT 24
Finished Jul 11 05:53:03 PM PDT 24
Peak memory 201888 kb
Host smart-578dbf65-54a0-4cf3-b509-cc83b71f590f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717411698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2717411698
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1826259952
Short name T667
Test name
Test status
Simulation time 167859195019 ps
CPU time 371.62 seconds
Started Jul 11 05:48:11 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 201908 kb
Host smart-da7403e2-5ee8-4dd8-a840-b576d800ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826259952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1826259952
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2768972207
Short name T789
Test name
Test status
Simulation time 166421678620 ps
CPU time 197.46 seconds
Started Jul 11 05:48:14 PM PDT 24
Finished Jul 11 05:51:36 PM PDT 24
Peak memory 201836 kb
Host smart-6b9a8465-6f9f-4932-a202-613f9faf13a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768972207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2768972207
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.635207837
Short name T166
Test name
Test status
Simulation time 187677662436 ps
CPU time 425.95 seconds
Started Jul 11 05:48:17 PM PDT 24
Finished Jul 11 05:55:29 PM PDT 24
Peak memory 201868 kb
Host smart-3797db6d-5266-41d6-8a65-19deac8ba0db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635207837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.635207837
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.325714647
Short name T4
Test name
Test status
Simulation time 189867572836 ps
CPU time 447.39 seconds
Started Jul 11 05:48:13 PM PDT 24
Finished Jul 11 05:55:45 PM PDT 24
Peak memory 201888 kb
Host smart-1e710f9c-202a-4c44-bece-1efc67a5a914
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325714647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.325714647
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3696097694
Short name T783
Test name
Test status
Simulation time 95859939478 ps
CPU time 441.27 seconds
Started Jul 11 05:48:18 PM PDT 24
Finished Jul 11 05:55:45 PM PDT 24
Peak memory 202160 kb
Host smart-1a599363-d97a-4a10-82e5-f83fea8cbb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696097694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3696097694
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4141424269
Short name T671
Test name
Test status
Simulation time 26390588940 ps
CPU time 31.95 seconds
Started Jul 11 05:48:20 PM PDT 24
Finished Jul 11 05:48:58 PM PDT 24
Peak memory 201620 kb
Host smart-757c2d69-87e8-4c87-a4aa-213d755a44e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141424269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4141424269
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2492252680
Short name T734
Test name
Test status
Simulation time 4112870638 ps
CPU time 5.76 seconds
Started Jul 11 05:48:20 PM PDT 24
Finished Jul 11 05:48:31 PM PDT 24
Peak memory 201708 kb
Host smart-64927c3d-5191-4cc2-b8f9-ed3b352ae491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492252680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2492252680
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1526572894
Short name T383
Test name
Test status
Simulation time 5733369479 ps
CPU time 4.25 seconds
Started Jul 11 05:48:30 PM PDT 24
Finished Jul 11 05:48:37 PM PDT 24
Peak memory 201704 kb
Host smart-1df7a743-c930-4faa-9492-5fd2f8ac852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526572894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1526572894
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3798915394
Short name T617
Test name
Test status
Simulation time 216659455227 ps
CPU time 247.08 seconds
Started Jul 11 05:48:19 PM PDT 24
Finished Jul 11 05:52:31 PM PDT 24
Peak memory 201956 kb
Host smart-1fdcf6f1-62cf-4872-8918-2ed5c8ce7489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798915394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3798915394
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1321169058
Short name T756
Test name
Test status
Simulation time 72211481355 ps
CPU time 161.42 seconds
Started Jul 11 05:48:35 PM PDT 24
Finished Jul 11 05:51:18 PM PDT 24
Peak memory 210260 kb
Host smart-2add198a-6049-48e4-8bc1-3fdb3099d559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321169058 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1321169058
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4276051191
Short name T570
Test name
Test status
Simulation time 163050912543 ps
CPU time 181.32 seconds
Started Jul 11 05:48:34 PM PDT 24
Finished Jul 11 05:51:37 PM PDT 24
Peak memory 201856 kb
Host smart-ed8591f7-b37b-461d-b65b-3fa36c54b2d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276051191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.4276051191
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1485722100
Short name T745
Test name
Test status
Simulation time 162658043369 ps
CPU time 345.44 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 05:54:16 PM PDT 24
Peak memory 201908 kb
Host smart-aae5f264-9a31-4a36-a1da-36e20dc05a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485722100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1485722100
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.4227988453
Short name T615
Test name
Test status
Simulation time 337669145577 ps
CPU time 182.5 seconds
Started Jul 11 05:48:34 PM PDT 24
Finished Jul 11 05:51:38 PM PDT 24
Peak memory 201880 kb
Host smart-2cf6fa0f-a3bd-4041-b1e3-ea7b11112afc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227988453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.4227988453
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.4191230004
Short name T2
Test name
Test status
Simulation time 179425455505 ps
CPU time 190.98 seconds
Started Jul 11 05:48:23 PM PDT 24
Finished Jul 11 05:51:39 PM PDT 24
Peak memory 201916 kb
Host smart-bb91bdfc-d244-451f-8b6e-186080f989c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191230004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.4191230004
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2966767570
Short name T476
Test name
Test status
Simulation time 399727584546 ps
CPU time 739.78 seconds
Started Jul 11 05:48:19 PM PDT 24
Finished Jul 11 06:00:45 PM PDT 24
Peak memory 201780 kb
Host smart-b697c72c-69f5-4ae8-becd-fee49344e568
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966767570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2966767570
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2502606209
Short name T669
Test name
Test status
Simulation time 84221909945 ps
CPU time 467.32 seconds
Started Jul 11 05:48:20 PM PDT 24
Finished Jul 11 05:56:13 PM PDT 24
Peak memory 202232 kb
Host smart-34f256cd-ddc7-40d2-b507-919ba95afdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502606209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2502606209
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.44593537
Short name T781
Test name
Test status
Simulation time 37103030365 ps
CPU time 41.17 seconds
Started Jul 11 05:48:19 PM PDT 24
Finished Jul 11 05:49:06 PM PDT 24
Peak memory 201588 kb
Host smart-fae828cf-8876-42cf-a73e-0e3b7708662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44593537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.44593537
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2589548339
Short name T732
Test name
Test status
Simulation time 2799263769 ps
CPU time 7.19 seconds
Started Jul 11 05:48:18 PM PDT 24
Finished Jul 11 05:48:31 PM PDT 24
Peak memory 201716 kb
Host smart-4a3b3e88-ea16-4b7a-b60c-f9ec746c2dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589548339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2589548339
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.85776607
Short name T68
Test name
Test status
Simulation time 4157746301 ps
CPU time 10.03 seconds
Started Jul 11 05:48:16 PM PDT 24
Finished Jul 11 05:48:32 PM PDT 24
Peak memory 217272 kb
Host smart-9fc70810-31c8-4ac6-ba46-ca8b2627ac89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85776607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.85776607
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3068801010
Short name T381
Test name
Test status
Simulation time 5935479692 ps
CPU time 13.72 seconds
Started Jul 11 05:48:33 PM PDT 24
Finished Jul 11 05:48:49 PM PDT 24
Peak memory 201716 kb
Host smart-533a637c-2563-484f-b0c6-5ee361c2b519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068801010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3068801010
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.345860486
Short name T404
Test name
Test status
Simulation time 472404128 ps
CPU time 1.62 seconds
Started Jul 11 05:48:55 PM PDT 24
Finished Jul 11 05:49:03 PM PDT 24
Peak memory 201652 kb
Host smart-e1072a36-0077-46ba-a67e-16b3db391b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345860486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.345860486
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.314013
Short name T303
Test name
Test status
Simulation time 526551977545 ps
CPU time 826.16 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 06:03:00 PM PDT 24
Peak memory 201868 kb
Host smart-c0e2fc85-8a3e-461d-aa3b-05eec5998561
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gati
ng_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.314013
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2828126381
Short name T584
Test name
Test status
Simulation time 484174728427 ps
CPU time 1101.09 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 06:07:06 PM PDT 24
Peak memory 201908 kb
Host smart-b09852bc-49e1-4fe7-b42d-f8b3b3c3e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828126381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2828126381
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4064498285
Short name T173
Test name
Test status
Simulation time 162909666925 ps
CPU time 170.07 seconds
Started Jul 11 05:49:05 PM PDT 24
Finished Jul 11 05:52:04 PM PDT 24
Peak memory 201852 kb
Host smart-8898f3ef-50f7-4e44-8522-6ca24cad3275
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064498285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4064498285
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2932095398
Short name T472
Test name
Test status
Simulation time 488979927689 ps
CPU time 1127.25 seconds
Started Jul 11 05:48:39 PM PDT 24
Finished Jul 11 06:07:28 PM PDT 24
Peak memory 201900 kb
Host smart-4b32cc72-fea5-4691-99d6-2f78a9ff1d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932095398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2932095398
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3797936647
Short name T591
Test name
Test status
Simulation time 159727993590 ps
CPU time 378.32 seconds
Started Jul 11 05:49:29 PM PDT 24
Finished Jul 11 05:55:48 PM PDT 24
Peak memory 201852 kb
Host smart-b185a813-91cc-468d-882f-abc768585aa5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797936647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3797936647
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.695609691
Short name T159
Test name
Test status
Simulation time 353363255892 ps
CPU time 51.29 seconds
Started Jul 11 05:49:05 PM PDT 24
Finished Jul 11 05:50:05 PM PDT 24
Peak memory 201940 kb
Host smart-e625c368-2c80-4e91-bc3d-f46a8860531a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695609691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.695609691
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1004797833
Short name T544
Test name
Test status
Simulation time 592483157656 ps
CPU time 364.35 seconds
Started Jul 11 05:48:44 PM PDT 24
Finished Jul 11 05:54:52 PM PDT 24
Peak memory 201880 kb
Host smart-ff41e7c5-d7ac-42b8-acaf-8f0f86a6e70b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004797833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1004797833
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.200388342
Short name T106
Test name
Test status
Simulation time 116849418217 ps
CPU time 368.23 seconds
Started Jul 11 05:48:53 PM PDT 24
Finished Jul 11 05:55:07 PM PDT 24
Peak memory 202228 kb
Host smart-7694f9c3-5761-4fc4-b6b8-5764c0426212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200388342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.200388342
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3793945198
Short name T594
Test name
Test status
Simulation time 33525084066 ps
CPU time 75.46 seconds
Started Jul 11 05:48:45 PM PDT 24
Finished Jul 11 05:50:04 PM PDT 24
Peak memory 201712 kb
Host smart-63965ed4-6ecf-4fc3-95e2-87f0ac749690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793945198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3793945198
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4266516101
Short name T204
Test name
Test status
Simulation time 3233876014 ps
CPU time 2.43 seconds
Started Jul 11 05:48:53 PM PDT 24
Finished Jul 11 05:49:01 PM PDT 24
Peak memory 201708 kb
Host smart-e959b542-ec79-4f36-b0b5-11faba4aaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266516101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4266516101
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.4218003056
Short name T30
Test name
Test status
Simulation time 5993998899 ps
CPU time 7.59 seconds
Started Jul 11 05:48:48 PM PDT 24
Finished Jul 11 05:48:59 PM PDT 24
Peak memory 201704 kb
Host smart-07084426-f0b1-433c-9c2a-e7f1078d48da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218003056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.4218003056
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2432316669
Short name T43
Test name
Test status
Simulation time 42771421783 ps
CPU time 187.61 seconds
Started Jul 11 05:48:39 PM PDT 24
Finished Jul 11 05:51:49 PM PDT 24
Peak memory 210604 kb
Host smart-dafdebd9-7a9f-4947-8078-2934338051a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432316669 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2432316669
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4068955236
Short name T614
Test name
Test status
Simulation time 516819488 ps
CPU time 1.83 seconds
Started Jul 11 05:48:51 PM PDT 24
Finished Jul 11 05:48:57 PM PDT 24
Peak memory 201644 kb
Host smart-86dbf037-7b9b-43de-8434-39e496566907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068955236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4068955236
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3002272696
Short name T526
Test name
Test status
Simulation time 511742301902 ps
CPU time 598.23 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 05:59:12 PM PDT 24
Peak memory 201872 kb
Host smart-854664cb-b514-49c5-97d9-7907faf935de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002272696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3002272696
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1807898309
Short name T300
Test name
Test status
Simulation time 162337412045 ps
CPU time 324.66 seconds
Started Jul 11 05:49:28 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 201956 kb
Host smart-adfbd0da-b366-4b1d-9773-b614dcebd0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807898309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1807898309
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1346906504
Short name T220
Test name
Test status
Simulation time 165095842235 ps
CPU time 387.62 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:55:13 PM PDT 24
Peak memory 201884 kb
Host smart-427ca32b-0f31-4ce3-8f8f-b2b10ea9bd98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346906504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1346906504
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.916044515
Short name T266
Test name
Test status
Simulation time 172742424984 ps
CPU time 154.57 seconds
Started Jul 11 05:48:53 PM PDT 24
Finished Jul 11 05:51:32 PM PDT 24
Peak memory 201924 kb
Host smart-7d3831cf-7248-4dba-ae39-4f1573595f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916044515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.916044515
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2121427670
Short name T565
Test name
Test status
Simulation time 165560893411 ps
CPU time 88.06 seconds
Started Jul 11 05:48:39 PM PDT 24
Finished Jul 11 05:50:09 PM PDT 24
Peak memory 201792 kb
Host smart-55484aec-61fc-4f3f-8fd9-f334f860bacc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121427670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2121427670
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1116260399
Short name T353
Test name
Test status
Simulation time 540630136468 ps
CPU time 302.98 seconds
Started Jul 11 05:48:46 PM PDT 24
Finished Jul 11 05:53:53 PM PDT 24
Peak memory 201960 kb
Host smart-65242581-5506-4479-94e5-105cd6d9f3b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116260399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1116260399
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1998814172
Short name T710
Test name
Test status
Simulation time 387244251788 ps
CPU time 79.96 seconds
Started Jul 11 05:48:51 PM PDT 24
Finished Jul 11 05:50:15 PM PDT 24
Peak memory 201876 kb
Host smart-f9f4132d-ae8d-4347-9c61-5ffa34b9c1ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998814172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1998814172
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2569626766
Short name T249
Test name
Test status
Simulation time 103259961147 ps
CPU time 512.02 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:57:11 PM PDT 24
Peak memory 202304 kb
Host smart-7f882205-0ceb-4d52-b882-2c18f9342768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569626766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2569626766
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3513329376
Short name T178
Test name
Test status
Simulation time 27338924710 ps
CPU time 36.62 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:49:23 PM PDT 24
Peak memory 201692 kb
Host smart-f814eaee-ec2c-4c3d-8bbc-49bf6cbcce1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513329376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3513329376
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1995700543
Short name T411
Test name
Test status
Simulation time 4860703043 ps
CPU time 3.51 seconds
Started Jul 11 05:49:05 PM PDT 24
Finished Jul 11 05:49:17 PM PDT 24
Peak memory 201684 kb
Host smart-7c594172-31a4-4aee-bf72-41a9eed0fe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995700543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1995700543
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.591212975
Short name T554
Test name
Test status
Simulation time 5904733291 ps
CPU time 7.22 seconds
Started Jul 11 05:49:28 PM PDT 24
Finished Jul 11 05:49:36 PM PDT 24
Peak memory 201680 kb
Host smart-7a4fe4b6-e11a-483d-ad0e-603e026d4863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591212975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.591212975
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3125560926
Short name T96
Test name
Test status
Simulation time 68973162111 ps
CPU time 125.43 seconds
Started Jul 11 05:48:41 PM PDT 24
Finished Jul 11 05:50:48 PM PDT 24
Peak memory 202044 kb
Host smart-08e447d8-7eb6-4cfc-9a21-0d48f5ce2581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125560926 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3125560926
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2213790707
Short name T529
Test name
Test status
Simulation time 298173582 ps
CPU time 0.86 seconds
Started Jul 11 05:49:00 PM PDT 24
Finished Jul 11 05:49:10 PM PDT 24
Peak memory 201656 kb
Host smart-b56fc15c-f013-47f9-81f9-0ffb6f4097cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213790707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2213790707
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2759980055
Short name T362
Test name
Test status
Simulation time 327280925529 ps
CPU time 790.29 seconds
Started Jul 11 05:48:46 PM PDT 24
Finished Jul 11 06:01:59 PM PDT 24
Peak memory 201964 kb
Host smart-21497b03-7916-411a-8052-1614e710212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759980055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2759980055
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1284233549
Short name T573
Test name
Test status
Simulation time 162799281372 ps
CPU time 345.48 seconds
Started Jul 11 05:50:08 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 201788 kb
Host smart-dc9b721a-a40a-4fa6-89a3-9ef31c9ceabf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284233549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1284233549
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3675399472
Short name T1
Test name
Test status
Simulation time 164026339700 ps
CPU time 350.23 seconds
Started Jul 11 05:48:53 PM PDT 24
Finished Jul 11 05:54:49 PM PDT 24
Peak memory 201944 kb
Host smart-fce33dbc-fc51-47f4-861a-e82afadca120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675399472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3675399472
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1320926828
Short name T720
Test name
Test status
Simulation time 326367557559 ps
CPU time 710.92 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 06:00:54 PM PDT 24
Peak memory 201880 kb
Host smart-158e762a-0086-4ee0-b400-0342065c78a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320926828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1320926828
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2582654886
Short name T547
Test name
Test status
Simulation time 202554309061 ps
CPU time 315.63 seconds
Started Jul 11 05:48:59 PM PDT 24
Finished Jul 11 05:54:24 PM PDT 24
Peak memory 201888 kb
Host smart-53b5cbba-a8bf-4403-981a-e34f6d9017d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582654886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2582654886
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.409190721
Short name T750
Test name
Test status
Simulation time 76464505135 ps
CPU time 259.68 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 05:53:33 PM PDT 24
Peak memory 202140 kb
Host smart-6c994608-05ef-48e8-bce5-6e02f4b488fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409190721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.409190721
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1160250507
Short name T777
Test name
Test status
Simulation time 27285680965 ps
CPU time 32.7 seconds
Started Jul 11 05:48:59 PM PDT 24
Finished Jul 11 05:49:41 PM PDT 24
Peak memory 201712 kb
Host smart-08cc0baa-57a8-4860-9f73-9f19e6a85f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160250507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1160250507
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3661077994
Short name T496
Test name
Test status
Simulation time 2893433465 ps
CPU time 2.36 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:48:49 PM PDT 24
Peak memory 201916 kb
Host smart-0a95d28a-d947-4395-8b2b-74dd794770e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661077994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3661077994
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1202514610
Short name T398
Test name
Test status
Simulation time 5924956791 ps
CPU time 13.65 seconds
Started Jul 11 05:49:27 PM PDT 24
Finished Jul 11 05:49:42 PM PDT 24
Peak memory 201716 kb
Host smart-109e0c28-4828-427f-82e2-787ea50f8d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202514610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1202514610
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1736588993
Short name T470
Test name
Test status
Simulation time 217589876454 ps
CPU time 265.26 seconds
Started Jul 11 05:48:52 PM PDT 24
Finished Jul 11 05:53:22 PM PDT 24
Peak memory 201964 kb
Host smart-b8a857e4-07f5-4b3f-9e87-b3584ec64f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736588993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1736588993
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.388050157
Short name T645
Test name
Test status
Simulation time 52289095011 ps
CPU time 131.21 seconds
Started Jul 11 05:48:52 PM PDT 24
Finished Jul 11 05:51:08 PM PDT 24
Peak memory 210684 kb
Host smart-4547e253-7439-461a-a635-2f3362ea8d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388050157 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.388050157
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1462649705
Short name T623
Test name
Test status
Simulation time 510076757 ps
CPU time 0.84 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:49:07 PM PDT 24
Peak memory 201612 kb
Host smart-71ef35c5-109f-4e2e-b1e2-92d5e57e572e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462649705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1462649705
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2976722975
Short name T243
Test name
Test status
Simulation time 337067660389 ps
CPU time 177.86 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 05:51:51 PM PDT 24
Peak memory 201896 kb
Host smart-168e52ed-dcac-4e69-ac46-252e3fdcdea6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976722975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2976722975
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1582251641
Short name T552
Test name
Test status
Simulation time 484551838580 ps
CPU time 534.27 seconds
Started Jul 11 05:48:59 PM PDT 24
Finished Jul 11 05:58:03 PM PDT 24
Peak memory 201908 kb
Host smart-dbcd5312-c499-4135-b0c9-ccb0be03aa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582251641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1582251641
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.4095789073
Short name T525
Test name
Test status
Simulation time 484142488019 ps
CPU time 152.36 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 05:51:25 PM PDT 24
Peak memory 201852 kb
Host smart-e18017a0-ac6c-4705-bb29-b222608fff13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095789073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.4095789073
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2114064600
Short name T334
Test name
Test status
Simulation time 329046918009 ps
CPU time 753.12 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 06:01:20 PM PDT 24
Peak memory 201968 kb
Host smart-82ea8180-7c00-4f9e-b7a4-30f1cb913fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114064600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2114064600
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2635596044
Short name T466
Test name
Test status
Simulation time 496899857918 ps
CPU time 281.71 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:53:48 PM PDT 24
Peak memory 201836 kb
Host smart-32d0cfb8-956b-4b41-a810-4ccb3f2b3bd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635596044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2635596044
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3853416966
Short name T199
Test name
Test status
Simulation time 358795513050 ps
CPU time 770.13 seconds
Started Jul 11 05:49:05 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 201812 kb
Host smart-68210f60-042c-4ebc-b1c6-fdb850e4d694
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853416966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3853416966
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3080040564
Short name T749
Test name
Test status
Simulation time 417881630182 ps
CPU time 464.19 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 201788 kb
Host smart-4af9e961-9a8f-4405-9a6b-13e37facb1ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080040564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3080040564
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2850708000
Short name T478
Test name
Test status
Simulation time 86482729697 ps
CPU time 506.83 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:57:33 PM PDT 24
Peak memory 202240 kb
Host smart-9a75cb6b-4099-45b5-b1db-8f148224ec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850708000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2850708000
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2259364629
Short name T394
Test name
Test status
Simulation time 35435275393 ps
CPU time 85.49 seconds
Started Jul 11 05:49:17 PM PDT 24
Finished Jul 11 05:50:45 PM PDT 24
Peak memory 201704 kb
Host smart-63cf44f6-586b-474e-a568-425371a061ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259364629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2259364629
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3941673351
Short name T105
Test name
Test status
Simulation time 3811866952 ps
CPU time 9.69 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 05:49:13 PM PDT 24
Peak memory 201712 kb
Host smart-ee483ac9-2882-41a5-ad72-8421a6a0e54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941673351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3941673351
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.304512098
Short name T713
Test name
Test status
Simulation time 5914326005 ps
CPU time 14.88 seconds
Started Jul 11 05:48:47 PM PDT 24
Finished Jul 11 05:49:05 PM PDT 24
Peak memory 201696 kb
Host smart-a57a1ffd-b9b2-4dfb-8408-1ca31747d51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304512098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.304512098
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.437509064
Short name T766
Test name
Test status
Simulation time 187771644995 ps
CPU time 38.75 seconds
Started Jul 11 05:48:52 PM PDT 24
Finished Jul 11 05:49:35 PM PDT 24
Peak memory 201948 kb
Host smart-bce59730-f439-40c3-be47-37373b419491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437509064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
437509064
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.759071130
Short name T13
Test name
Test status
Simulation time 468392520 ps
CPU time 1.14 seconds
Started Jul 11 05:48:50 PM PDT 24
Finished Jul 11 05:48:55 PM PDT 24
Peak memory 201572 kb
Host smart-085419ba-0476-4495-bf75-c9301f0d93bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759071130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.759071130
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3402058167
Short name T658
Test name
Test status
Simulation time 509481690755 ps
CPU time 543.23 seconds
Started Jul 11 05:48:48 PM PDT 24
Finished Jul 11 05:57:55 PM PDT 24
Peak memory 201892 kb
Host smart-c009715c-320e-483c-9ed9-ff0be7deeda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402058167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3402058167
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2701938587
Short name T238
Test name
Test status
Simulation time 330147541130 ps
CPU time 683.74 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 201792 kb
Host smart-45426094-9435-4d7b-967a-035c38de16c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701938587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2701938587
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2497705136
Short name T748
Test name
Test status
Simulation time 491498012539 ps
CPU time 542.2 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:58:09 PM PDT 24
Peak memory 201868 kb
Host smart-e9da9355-7221-4bbf-9353-55ee1f15f33a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497705136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2497705136
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1548163705
Short name T555
Test name
Test status
Simulation time 489240274855 ps
CPU time 1136.8 seconds
Started Jul 11 05:48:50 PM PDT 24
Finished Jul 11 06:07:51 PM PDT 24
Peak memory 201900 kb
Host smart-cd83f95a-9fc8-41df-a4b5-e615dfca6421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548163705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1548163705
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1897649253
Short name T179
Test name
Test status
Simulation time 160855345888 ps
CPU time 341.93 seconds
Started Jul 11 05:49:02 PM PDT 24
Finished Jul 11 05:54:53 PM PDT 24
Peak memory 201812 kb
Host smart-102f695c-0eda-49e8-9c1f-1bc1e0d61c0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897649253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1897649253
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.133564125
Short name T47
Test name
Test status
Simulation time 182731566213 ps
CPU time 295.45 seconds
Started Jul 11 05:49:15 PM PDT 24
Finished Jul 11 05:54:14 PM PDT 24
Peak memory 201976 kb
Host smart-72322737-46d6-4bc5-904f-3bec3129d894
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133564125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.133564125
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1907044800
Short name T716
Test name
Test status
Simulation time 203028262587 ps
CPU time 239.44 seconds
Started Jul 11 05:48:48 PM PDT 24
Finished Jul 11 05:52:51 PM PDT 24
Peak memory 202096 kb
Host smart-6a366ef5-546b-4905-ae1d-a07f94703884
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907044800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1907044800
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2998847392
Short name T441
Test name
Test status
Simulation time 40049578894 ps
CPU time 74.12 seconds
Started Jul 11 05:49:18 PM PDT 24
Finished Jul 11 05:50:35 PM PDT 24
Peak memory 201596 kb
Host smart-b8148033-e9b6-497f-881d-2e844e9d8107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998847392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2998847392
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2489550436
Short name T473
Test name
Test status
Simulation time 4948378528 ps
CPU time 3.05 seconds
Started Jul 11 05:48:50 PM PDT 24
Finished Jul 11 05:48:57 PM PDT 24
Peak memory 201712 kb
Host smart-f4a73ad4-1ab9-4e0c-a5d8-361a28ee80db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489550436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2489550436
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2614439827
Short name T235
Test name
Test status
Simulation time 5535358552 ps
CPU time 12.06 seconds
Started Jul 11 05:49:25 PM PDT 24
Finished Jul 11 05:49:39 PM PDT 24
Peak memory 201700 kb
Host smart-153f3ee6-e42c-448b-b98c-a2f9c9514894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614439827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2614439827
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2463599029
Short name T17
Test name
Test status
Simulation time 26648871084 ps
CPU time 54.13 seconds
Started Jul 11 05:48:55 PM PDT 24
Finished Jul 11 05:49:55 PM PDT 24
Peak memory 210212 kb
Host smart-89836778-c5c7-4b5b-83f7-64ca4bc46160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463599029 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2463599029
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2261395807
Short name T393
Test name
Test status
Simulation time 379914873 ps
CPU time 1.47 seconds
Started Jul 11 05:48:51 PM PDT 24
Finished Jul 11 05:48:56 PM PDT 24
Peak memory 201656 kb
Host smart-82b3c43a-d04f-4005-9d1c-5185d42b67a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261395807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2261395807
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2227260655
Short name T711
Test name
Test status
Simulation time 166059967768 ps
CPU time 114.32 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:51:01 PM PDT 24
Peak memory 201908 kb
Host smart-f07434b7-f8f6-43b7-b591-4baae41d23f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227260655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2227260655
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3629615145
Short name T157
Test name
Test status
Simulation time 170786104420 ps
CPU time 201.69 seconds
Started Jul 11 05:48:51 PM PDT 24
Finished Jul 11 05:52:18 PM PDT 24
Peak memory 201828 kb
Host smart-00b8690d-a45b-49c5-9b07-e764f355931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629615145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3629615145
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3460138110
Short name T264
Test name
Test status
Simulation time 336225358058 ps
CPU time 192.6 seconds
Started Jul 11 05:49:27 PM PDT 24
Finished Jul 11 05:52:41 PM PDT 24
Peak memory 201920 kb
Host smart-e5ad184f-2d25-4027-9af9-a05e391cfda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460138110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3460138110
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3781110247
Short name T702
Test name
Test status
Simulation time 317239911575 ps
CPU time 109.63 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 05:50:52 PM PDT 24
Peak memory 201128 kb
Host smart-5df6a9a2-ed22-49a2-a695-652c3add77b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781110247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3781110247
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.798571335
Short name T722
Test name
Test status
Simulation time 335048273246 ps
CPU time 197.38 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:52:22 PM PDT 24
Peak memory 201920 kb
Host smart-b8423441-680c-4a67-8f8e-5519b16f5fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798571335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.798571335
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.145244984
Short name T186
Test name
Test status
Simulation time 489988571256 ps
CPU time 273.28 seconds
Started Jul 11 05:48:51 PM PDT 24
Finished Jul 11 05:53:28 PM PDT 24
Peak memory 201832 kb
Host smart-242d4284-7603-4dbd-ac0c-987278572139
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=145244984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.145244984
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3368428239
Short name T700
Test name
Test status
Simulation time 356254319788 ps
CPU time 742.16 seconds
Started Jul 11 05:49:01 PM PDT 24
Finished Jul 11 06:01:32 PM PDT 24
Peak memory 201916 kb
Host smart-e7a8b304-6e04-49cf-ad94-2ac22783a967
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368428239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3368428239
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4176388776
Short name T493
Test name
Test status
Simulation time 200198116308 ps
CPU time 417.08 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 05:55:59 PM PDT 24
Peak memory 200988 kb
Host smart-2b89b41e-a9a3-4224-ac45-191c7e7f3261
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176388776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4176388776
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2325469622
Short name T782
Test name
Test status
Simulation time 139615737269 ps
CPU time 419.83 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:56:06 PM PDT 24
Peak memory 202140 kb
Host smart-8ef7f003-a4d6-417f-b8dd-7b98e06902e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325469622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2325469622
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3457404626
Short name T657
Test name
Test status
Simulation time 30380472038 ps
CPU time 69.28 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:50:16 PM PDT 24
Peak memory 201660 kb
Host smart-83b54b6d-6c1a-4860-a0b3-9390989d3858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457404626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3457404626
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3996419769
Short name T775
Test name
Test status
Simulation time 5299880338 ps
CPU time 3.64 seconds
Started Jul 11 05:48:53 PM PDT 24
Finished Jul 11 05:49:02 PM PDT 24
Peak memory 201652 kb
Host smart-79663cd2-2892-473c-a76c-e2365bffb128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996419769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3996419769
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1044976159
Short name T401
Test name
Test status
Simulation time 5682321610 ps
CPU time 4.03 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:49:09 PM PDT 24
Peak memory 201716 kb
Host smart-7afab7b0-dc82-4f63-88b6-caf2d8c9c47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044976159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1044976159
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2779638108
Short name T39
Test name
Test status
Simulation time 62450723133 ps
CPU time 137.59 seconds
Started Jul 11 05:48:47 PM PDT 24
Finished Jul 11 05:51:08 PM PDT 24
Peak memory 210300 kb
Host smart-fc7ce44b-62b2-4c2e-a8f9-aec53441da77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779638108 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2779638108
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2094201791
Short name T410
Test name
Test status
Simulation time 435601203 ps
CPU time 1.38 seconds
Started Jul 11 05:49:09 PM PDT 24
Finished Jul 11 05:49:17 PM PDT 24
Peak memory 201656 kb
Host smart-105b1935-2baa-4556-a257-631e5422b830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094201791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2094201791
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3787748273
Short name T764
Test name
Test status
Simulation time 512459642593 ps
CPU time 375.38 seconds
Started Jul 11 05:48:50 PM PDT 24
Finished Jul 11 05:55:09 PM PDT 24
Peak memory 201960 kb
Host smart-6892f0fb-882e-4589-94d8-4bbcaf20cd93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787748273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3787748273
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2543051066
Short name T612
Test name
Test status
Simulation time 164989165024 ps
CPU time 337.52 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:54:44 PM PDT 24
Peak memory 201944 kb
Host smart-6982dc09-aeca-4a63-88c2-dbaa661f1a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543051066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2543051066
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1199651188
Short name T280
Test name
Test status
Simulation time 169798889735 ps
CPU time 99.73 seconds
Started Jul 11 05:49:10 PM PDT 24
Finished Jul 11 05:50:56 PM PDT 24
Peak memory 201832 kb
Host smart-047777ab-da97-47e1-8ae2-6996207dd991
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199651188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1199651188
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1517448191
Short name T598
Test name
Test status
Simulation time 484562804820 ps
CPU time 261.74 seconds
Started Jul 11 05:48:53 PM PDT 24
Finished Jul 11 05:53:19 PM PDT 24
Peak memory 201964 kb
Host smart-f4b9123e-10c0-4797-b0d7-3f7c24a85202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517448191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1517448191
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1385539238
Short name T574
Test name
Test status
Simulation time 488239337659 ps
CPU time 1043.47 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 06:06:28 PM PDT 24
Peak memory 201776 kb
Host smart-8c9c4d48-7752-4ef8-bec9-6258e10c6f66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385539238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1385539238
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1225581508
Short name T285
Test name
Test status
Simulation time 354354188694 ps
CPU time 420.9 seconds
Started Jul 11 05:48:50 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 201976 kb
Host smart-5e3ff821-4dcc-4b41-9a02-a18672583a00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225581508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1225581508
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.168325815
Short name T543
Test name
Test status
Simulation time 593836030751 ps
CPU time 713.45 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 06:01:00 PM PDT 24
Peak memory 201908 kb
Host smart-8bd2d79c-1047-485e-87d1-34225148a1fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168325815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.168325815
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2313790465
Short name T254
Test name
Test status
Simulation time 84842900840 ps
CPU time 275.89 seconds
Started Jul 11 05:49:18 PM PDT 24
Finished Jul 11 05:53:56 PM PDT 24
Peak memory 202168 kb
Host smart-9e61ddd7-a1e1-428f-b64b-f73d92cdae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313790465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2313790465
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2123839184
Short name T527
Test name
Test status
Simulation time 33454883305 ps
CPU time 10.37 seconds
Started Jul 11 05:49:09 PM PDT 24
Finished Jul 11 05:49:25 PM PDT 24
Peak memory 201712 kb
Host smart-6060f030-eba0-4f47-94a5-d7e6af3d0b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123839184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2123839184
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3716576862
Short name T731
Test name
Test status
Simulation time 4483056770 ps
CPU time 6.25 seconds
Started Jul 11 05:48:59 PM PDT 24
Finished Jul 11 05:49:14 PM PDT 24
Peak memory 201724 kb
Host smart-b73caf7f-b312-440d-9851-173544e70e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716576862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3716576862
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1855916213
Short name T568
Test name
Test status
Simulation time 5872148516 ps
CPU time 8.05 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:49:12 PM PDT 24
Peak memory 201660 kb
Host smart-bbbadea6-95a1-434a-9dbb-954607542a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855916213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1855916213
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3362844537
Short name T28
Test name
Test status
Simulation time 169249900606 ps
CPU time 349.57 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:54:56 PM PDT 24
Peak memory 218612 kb
Host smart-ab6de86a-a0fb-44c0-a937-42500d6e3541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362844537 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3362844537
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.359506674
Short name T487
Test name
Test status
Simulation time 344190411 ps
CPU time 1.29 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:49:08 PM PDT 24
Peak memory 201856 kb
Host smart-aaef42e5-b107-4447-8106-b76ae4b92bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359506674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.359506674
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.308415255
Short name T735
Test name
Test status
Simulation time 329921868807 ps
CPU time 388.79 seconds
Started Jul 11 05:49:36 PM PDT 24
Finished Jul 11 05:56:07 PM PDT 24
Peak memory 201964 kb
Host smart-e3b30475-f8b8-4ef4-95c9-e8a1f24e93bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308415255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.308415255
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4148469217
Short name T685
Test name
Test status
Simulation time 340836390026 ps
CPU time 69.76 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:50:16 PM PDT 24
Peak memory 201920 kb
Host smart-e51535dc-1ca9-48ab-b90d-a363d5f46ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148469217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4148469217
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3498178107
Short name T272
Test name
Test status
Simulation time 330846599305 ps
CPU time 241.71 seconds
Started Jul 11 05:49:34 PM PDT 24
Finished Jul 11 05:53:37 PM PDT 24
Peak memory 201904 kb
Host smart-41f5dc1b-c6cc-4d2c-9fed-b9a8471eb156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498178107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3498178107
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2723889596
Short name T786
Test name
Test status
Simulation time 323619017184 ps
CPU time 345.64 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 05:54:59 PM PDT 24
Peak memory 201844 kb
Host smart-2930af85-0097-4209-87a6-8094cb04e267
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723889596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2723889596
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2319698954
Short name T754
Test name
Test status
Simulation time 163760813963 ps
CPU time 88.73 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 05:50:42 PM PDT 24
Peak memory 201960 kb
Host smart-1ccb0da6-8fec-437f-b9d5-fc0c06f80bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319698954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2319698954
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2687997308
Short name T635
Test name
Test status
Simulation time 169589447185 ps
CPU time 270.9 seconds
Started Jul 11 05:49:34 PM PDT 24
Finished Jul 11 05:54:07 PM PDT 24
Peak memory 201880 kb
Host smart-0be21395-a438-4fd9-a36c-cf4d5684ce0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687997308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2687997308
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2855779900
Short name T363
Test name
Test status
Simulation time 352232514709 ps
CPU time 51.54 seconds
Started Jul 11 05:49:01 PM PDT 24
Finished Jul 11 05:50:02 PM PDT 24
Peak memory 201844 kb
Host smart-5fdd334f-7f15-494a-9246-8426399a5af9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855779900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2855779900
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1757046257
Short name T520
Test name
Test status
Simulation time 401151320353 ps
CPU time 219.7 seconds
Started Jul 11 05:49:11 PM PDT 24
Finished Jul 11 05:52:56 PM PDT 24
Peak memory 201852 kb
Host smart-e5e776a5-b0e3-48de-8891-90fb1d90c0db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757046257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1757046257
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1452669827
Short name T116
Test name
Test status
Simulation time 125635803371 ps
CPU time 455.51 seconds
Started Jul 11 05:49:36 PM PDT 24
Finished Jul 11 05:57:14 PM PDT 24
Peak memory 202224 kb
Host smart-fcd020a6-827a-4853-b6fc-bacfd1a052db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452669827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1452669827
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.355764076
Short name T538
Test name
Test status
Simulation time 28441867986 ps
CPU time 31.45 seconds
Started Jul 11 05:49:02 PM PDT 24
Finished Jul 11 05:49:43 PM PDT 24
Peak memory 201712 kb
Host smart-cb5b6a44-9b69-4dc0-bb72-296c509fda5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355764076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.355764076
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.555289752
Short name T423
Test name
Test status
Simulation time 4033687666 ps
CPU time 5.42 seconds
Started Jul 11 05:49:10 PM PDT 24
Finished Jul 11 05:49:21 PM PDT 24
Peak memory 201608 kb
Host smart-f9962860-0d3e-42c1-8ac7-5771be4f6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555289752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.555289752
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4106069740
Short name T403
Test name
Test status
Simulation time 5875490544 ps
CPU time 6.87 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:49:13 PM PDT 24
Peak memory 201928 kb
Host smart-088bd496-c5b9-4b01-99e8-c50954ffc6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106069740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4106069740
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.67630930
Short name T247
Test name
Test status
Simulation time 6451636719 ps
CPU time 4.38 seconds
Started Jul 11 05:48:52 PM PDT 24
Finished Jul 11 05:49:02 PM PDT 24
Peak memory 201692 kb
Host smart-06e86590-6db5-4157-bd19-cc96405e7737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67630930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.67630930
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3208673006
Short name T541
Test name
Test status
Simulation time 347967375 ps
CPU time 1.37 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:49:08 PM PDT 24
Peak memory 201856 kb
Host smart-1cc4716d-c637-4e36-b6e4-9e177e7b6e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208673006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3208673006
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3475925829
Short name T785
Test name
Test status
Simulation time 499994074116 ps
CPU time 292.71 seconds
Started Jul 11 05:48:58 PM PDT 24
Finished Jul 11 05:54:00 PM PDT 24
Peak memory 201856 kb
Host smart-f0061046-b4cd-4b4c-93e0-7f0b12570839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475925829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3475925829
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.404195904
Short name T497
Test name
Test status
Simulation time 162959826810 ps
CPU time 76.69 seconds
Started Jul 11 05:49:10 PM PDT 24
Finished Jul 11 05:50:32 PM PDT 24
Peak memory 201776 kb
Host smart-1ab3d0b8-48e8-431f-8516-f18c3614f6e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=404195904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.404195904
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3557795779
Short name T197
Test name
Test status
Simulation time 493838105524 ps
CPU time 172.52 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 05:51:55 PM PDT 24
Peak memory 201884 kb
Host smart-fc1e2e20-f1ba-4d86-b720-5e004a44ad84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557795779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3557795779
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1129027869
Short name T114
Test name
Test status
Simulation time 489456677836 ps
CPU time 1136.24 seconds
Started Jul 11 05:49:05 PM PDT 24
Finished Jul 11 06:08:10 PM PDT 24
Peak memory 201884 kb
Host smart-b790c262-0851-4825-bac9-d53bac60661d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129027869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1129027869
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1747788483
Short name T675
Test name
Test status
Simulation time 387666554981 ps
CPU time 52.33 seconds
Started Jul 11 05:49:01 PM PDT 24
Finished Jul 11 05:50:02 PM PDT 24
Peak memory 201796 kb
Host smart-7d5c3310-f571-4419-b92e-b39375e8e920
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747788483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1747788483
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3070556880
Short name T502
Test name
Test status
Simulation time 99336696548 ps
CPU time 316.33 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:54:54 PM PDT 24
Peak memory 202288 kb
Host smart-7d99e0fc-06ee-40a8-89b8-11f1f438ad27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070556880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3070556880
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3573952011
Short name T796
Test name
Test status
Simulation time 39416857020 ps
CPU time 90 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 05:50:43 PM PDT 24
Peak memory 201708 kb
Host smart-8f92974d-6f58-4696-91ba-c59c084d0c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573952011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3573952011
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1686616115
Short name T792
Test name
Test status
Simulation time 3568288695 ps
CPU time 2.75 seconds
Started Jul 11 05:49:10 PM PDT 24
Finished Jul 11 05:49:19 PM PDT 24
Peak memory 201684 kb
Host smart-54e7f7c8-5407-4cfb-b0c5-3c9e6088f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686616115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1686616115
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2207302393
Short name T428
Test name
Test status
Simulation time 6106184529 ps
CPU time 4.22 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:49:41 PM PDT 24
Peak memory 201704 kb
Host smart-6f3906b7-978d-4d4b-ab22-878499f3991b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207302393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2207302393
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.775705664
Short name T65
Test name
Test status
Simulation time 92906333008 ps
CPU time 155.14 seconds
Started Jul 11 05:48:54 PM PDT 24
Finished Jul 11 05:51:35 PM PDT 24
Peak memory 210284 kb
Host smart-dfcf072c-a8ca-45f9-ba99-cdcd382c9cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775705664 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.775705664
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2873716866
Short name T397
Test name
Test status
Simulation time 399459683 ps
CPU time 1.02 seconds
Started Jul 11 05:49:03 PM PDT 24
Finished Jul 11 05:49:13 PM PDT 24
Peak memory 201732 kb
Host smart-111eb23f-dddf-4760-a745-62e3fc5c66b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873716866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2873716866
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2604726884
Short name T281
Test name
Test status
Simulation time 337570799335 ps
CPU time 569.16 seconds
Started Jul 11 05:49:03 PM PDT 24
Finished Jul 11 05:58:41 PM PDT 24
Peak memory 201976 kb
Host smart-05915eb0-a9b4-4dff-af12-592f4242025a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604726884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2604726884
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2027823191
Short name T336
Test name
Test status
Simulation time 494853795279 ps
CPU time 578.79 seconds
Started Jul 11 05:49:00 PM PDT 24
Finished Jul 11 05:58:48 PM PDT 24
Peak memory 201944 kb
Host smart-6be0f3ef-aebf-4340-b7bd-c8159891d692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027823191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2027823191
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4190512440
Short name T479
Test name
Test status
Simulation time 508524827844 ps
CPU time 171.21 seconds
Started Jul 11 05:49:03 PM PDT 24
Finished Jul 11 05:52:03 PM PDT 24
Peak memory 201792 kb
Host smart-608a3984-93aa-44a8-a528-417dbf4d6616
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190512440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4190512440
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3117056135
Short name T703
Test name
Test status
Simulation time 323371859262 ps
CPU time 763.17 seconds
Started Jul 11 05:49:03 PM PDT 24
Finished Jul 11 06:01:55 PM PDT 24
Peak memory 201828 kb
Host smart-c8f871fc-e8fa-44cb-bd8f-b2a45382d98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117056135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3117056135
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2492205277
Short name T176
Test name
Test status
Simulation time 168602628632 ps
CPU time 57.67 seconds
Started Jul 11 05:48:56 PM PDT 24
Finished Jul 11 05:50:00 PM PDT 24
Peak memory 201864 kb
Host smart-df3d2aff-1dba-42c4-b2f9-58834db251a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492205277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2492205277
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.584930061
Short name T293
Test name
Test status
Simulation time 519887013689 ps
CPU time 334.51 seconds
Started Jul 11 05:48:59 PM PDT 24
Finished Jul 11 05:54:43 PM PDT 24
Peak memory 202176 kb
Host smart-962f2424-188c-4001-840b-df36d6eed274
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584930061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.584930061
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1993082898
Short name T451
Test name
Test status
Simulation time 199438478343 ps
CPU time 419.26 seconds
Started Jul 11 05:49:02 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 201760 kb
Host smart-59dc3957-c0e2-4435-b2f3-97c136b92366
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993082898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1993082898
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1786386859
Short name T192
Test name
Test status
Simulation time 71917932147 ps
CPU time 383.41 seconds
Started Jul 11 05:49:00 PM PDT 24
Finished Jul 11 05:55:33 PM PDT 24
Peak memory 202232 kb
Host smart-d853c67f-23ce-4488-bcd0-b80613fa9904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786386859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1786386859
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3125443284
Short name T407
Test name
Test status
Simulation time 23199869130 ps
CPU time 25.98 seconds
Started Jul 11 05:49:01 PM PDT 24
Finished Jul 11 05:49:37 PM PDT 24
Peak memory 201712 kb
Host smart-d2fbc354-5f23-4677-85a3-56ffdca7caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125443284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3125443284
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3090759431
Short name T787
Test name
Test status
Simulation time 3750738650 ps
CPU time 2.61 seconds
Started Jul 11 05:49:03 PM PDT 24
Finished Jul 11 05:49:14 PM PDT 24
Peak memory 201620 kb
Host smart-1420c0d3-3d6d-4c1d-8d57-64666ff2fc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090759431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3090759431
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1444147437
Short name T205
Test name
Test status
Simulation time 5861666363 ps
CPU time 7.48 seconds
Started Jul 11 05:49:03 PM PDT 24
Finished Jul 11 05:49:20 PM PDT 24
Peak memory 201620 kb
Host smart-801877dd-f99f-49a5-aa1d-7a6e3a0d7d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444147437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1444147437
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.339004680
Short name T757
Test name
Test status
Simulation time 347701839 ps
CPU time 1.02 seconds
Started Jul 11 05:48:21 PM PDT 24
Finished Jul 11 05:48:27 PM PDT 24
Peak memory 201572 kb
Host smart-67cd1a12-992e-4322-91ed-7087f8d39a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339004680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.339004680
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3235742829
Short name T643
Test name
Test status
Simulation time 372352431110 ps
CPU time 423.86 seconds
Started Jul 11 05:48:35 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 201888 kb
Host smart-cbcd8a4a-a7c5-4e9e-a03d-e0511cd5a425
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235742829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3235742829
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3942607819
Short name T171
Test name
Test status
Simulation time 335216879570 ps
CPU time 70.29 seconds
Started Jul 11 05:48:22 PM PDT 24
Finished Jul 11 05:49:37 PM PDT 24
Peak memory 201924 kb
Host smart-d8de7519-8690-43c3-8e87-d84eb483a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942607819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3942607819
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.98091546
Short name T491
Test name
Test status
Simulation time 161442077564 ps
CPU time 181.01 seconds
Started Jul 11 05:48:30 PM PDT 24
Finished Jul 11 05:51:34 PM PDT 24
Peak memory 201924 kb
Host smart-84612fd2-d2d9-43bd-a96c-0bc369d1b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98091546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.98091546
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1493460108
Short name T620
Test name
Test status
Simulation time 161648880730 ps
CPU time 365.26 seconds
Started Jul 11 05:48:22 PM PDT 24
Finished Jul 11 05:54:32 PM PDT 24
Peak memory 201872 kb
Host smart-9a0ae6ed-c3c7-4a76-a572-5bc5769d9ce3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493460108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1493460108
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3124664904
Short name T88
Test name
Test status
Simulation time 317206351780 ps
CPU time 350.85 seconds
Started Jul 11 05:48:17 PM PDT 24
Finished Jul 11 05:54:14 PM PDT 24
Peak memory 201888 kb
Host smart-87f24471-2775-400a-9eb0-cc17272965a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124664904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3124664904
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3495636390
Short name T501
Test name
Test status
Simulation time 328994184562 ps
CPU time 696.66 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 06:00:42 PM PDT 24
Peak memory 201832 kb
Host smart-5a7c231b-b307-4012-9bcb-cd2d0604d067
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495636390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3495636390
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.4061799638
Short name T119
Test name
Test status
Simulation time 404223481134 ps
CPU time 481.28 seconds
Started Jul 11 05:48:21 PM PDT 24
Finished Jul 11 05:56:27 PM PDT 24
Peak memory 201872 kb
Host smart-4660ea24-2eae-421a-a373-931d7b92ecd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061799638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.4061799638
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3779827350
Short name T37
Test name
Test status
Simulation time 91009643882 ps
CPU time 358.6 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:54:43 PM PDT 24
Peak memory 202168 kb
Host smart-68bfe7fe-21ed-4432-9ab9-0fbea2ddd482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779827350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3779827350
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1696668995
Short name T719
Test name
Test status
Simulation time 29987300310 ps
CPU time 62.04 seconds
Started Jul 11 05:48:21 PM PDT 24
Finished Jul 11 05:49:28 PM PDT 24
Peak memory 201584 kb
Host smart-15c9c46c-1d89-4e4a-b37b-e52b3fb2f480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696668995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1696668995
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1369276958
Short name T103
Test name
Test status
Simulation time 4323341583 ps
CPU time 3.32 seconds
Started Jul 11 05:48:28 PM PDT 24
Finished Jul 11 05:48:34 PM PDT 24
Peak memory 201708 kb
Host smart-95ae2eb5-9dbe-4543-9892-28f6142d4041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369276958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1369276958
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1415261092
Short name T86
Test name
Test status
Simulation time 4349811323 ps
CPU time 10.46 seconds
Started Jul 11 05:48:24 PM PDT 24
Finished Jul 11 05:48:39 PM PDT 24
Peak memory 217164 kb
Host smart-67107bbd-2e9d-4765-808c-c89b2e3651f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415261092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1415261092
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1750253935
Short name T3
Test name
Test status
Simulation time 5841622239 ps
CPU time 7.46 seconds
Started Jul 11 05:48:18 PM PDT 24
Finished Jul 11 05:48:31 PM PDT 24
Peak memory 201708 kb
Host smart-5f7d1500-3b41-4e56-9fe0-199d629b3209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750253935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1750253935
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1154224043
Short name T19
Test name
Test status
Simulation time 211691222613 ps
CPU time 55.35 seconds
Started Jul 11 05:48:28 PM PDT 24
Finished Jul 11 05:49:26 PM PDT 24
Peak memory 210224 kb
Host smart-718eedec-53a3-4d1b-9aae-aefd4642a900
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154224043 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1154224043
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3778929381
Short name T386
Test name
Test status
Simulation time 491910359 ps
CPU time 0.9 seconds
Started Jul 11 05:49:22 PM PDT 24
Finished Jul 11 05:49:24 PM PDT 24
Peak memory 201404 kb
Host smart-6eab5a3e-d840-4d25-a6be-0872d7353995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778929381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3778929381
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2545442032
Short name T321
Test name
Test status
Simulation time 492266305316 ps
CPU time 996.65 seconds
Started Jul 11 05:48:59 PM PDT 24
Finished Jul 11 06:05:45 PM PDT 24
Peak memory 201924 kb
Host smart-94fc9de6-e18b-44f9-b0a9-46b3d381fc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545442032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2545442032
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.371353746
Short name T666
Test name
Test status
Simulation time 160662615583 ps
CPU time 388.4 seconds
Started Jul 11 05:49:08 PM PDT 24
Finished Jul 11 05:55:44 PM PDT 24
Peak memory 201880 kb
Host smart-a0d9512d-1dc6-446d-8162-22ffb56f4d07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=371353746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.371353746
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2852694675
Short name T373
Test name
Test status
Simulation time 163606798377 ps
CPU time 52.15 seconds
Started Jul 11 05:49:04 PM PDT 24
Finished Jul 11 05:50:06 PM PDT 24
Peak memory 201972 kb
Host smart-ad8d4250-66ed-4ca9-a0c3-8ae94c4708c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852694675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2852694675
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.170479996
Short name T460
Test name
Test status
Simulation time 497891299379 ps
CPU time 1107.38 seconds
Started Jul 11 05:49:02 PM PDT 24
Finished Jul 11 06:07:39 PM PDT 24
Peak memory 201892 kb
Host smart-0f8af766-bcf5-4736-9c5c-6d87885e9248
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=170479996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.170479996
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.484105758
Short name T348
Test name
Test status
Simulation time 352482696777 ps
CPU time 414.88 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 05:56:13 PM PDT 24
Peak memory 201940 kb
Host smart-f7ab9c7f-4712-418a-a219-43f2d8303731
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484105758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.484105758
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4143445882
Short name T746
Test name
Test status
Simulation time 606787373188 ps
CPU time 1132.21 seconds
Started Jul 11 05:49:13 PM PDT 24
Finished Jul 11 06:08:10 PM PDT 24
Peak memory 201888 kb
Host smart-f7e0a1df-2299-4ac2-b3d5-816af30317db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143445882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4143445882
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3407488262
Short name T770
Test name
Test status
Simulation time 106064554766 ps
CPU time 497.16 seconds
Started Jul 11 05:49:08 PM PDT 24
Finished Jul 11 05:57:32 PM PDT 24
Peak memory 202228 kb
Host smart-22c979d9-7bd1-4a3f-b0c8-9d911e1ff485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407488262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3407488262
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1045095321
Short name T589
Test name
Test status
Simulation time 36955624781 ps
CPU time 21.98 seconds
Started Jul 11 05:49:22 PM PDT 24
Finished Jul 11 05:49:45 PM PDT 24
Peak memory 201488 kb
Host smart-7f43f562-6f28-4987-acb9-005c782cc127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045095321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1045095321
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1830532394
Short name T448
Test name
Test status
Simulation time 4272349120 ps
CPU time 5.02 seconds
Started Jul 11 05:49:16 PM PDT 24
Finished Jul 11 05:49:24 PM PDT 24
Peak memory 201712 kb
Host smart-b70154ff-3da4-4ea1-bdc3-3c2a8d377414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830532394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1830532394
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.207756109
Short name T452
Test name
Test status
Simulation time 5528727217 ps
CPU time 12.87 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 05:49:30 PM PDT 24
Peak memory 201696 kb
Host smart-c63dcff7-deba-4148-8929-015644da2f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207756109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.207756109
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.755015429
Short name T16
Test name
Test status
Simulation time 414304873931 ps
CPU time 156.47 seconds
Started Jul 11 05:49:05 PM PDT 24
Finished Jul 11 05:51:50 PM PDT 24
Peak memory 210456 kb
Host smart-85766770-72a5-4919-8a92-c40cd6c55aef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755015429 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.755015429
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3915807392
Short name T421
Test name
Test status
Simulation time 383923250 ps
CPU time 1.45 seconds
Started Jul 11 05:49:17 PM PDT 24
Finished Jul 11 05:49:21 PM PDT 24
Peak memory 201444 kb
Host smart-e2aa7189-3251-4313-9774-b281ed6d6541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915807392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3915807392
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1544267525
Short name T534
Test name
Test status
Simulation time 159282291505 ps
CPU time 333.66 seconds
Started Jul 11 05:49:13 PM PDT 24
Finished Jul 11 05:54:51 PM PDT 24
Peak memory 201964 kb
Host smart-afbcfaea-3fd8-46f6-a583-675162fbfdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544267525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1544267525
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1123135262
Short name T11
Test name
Test status
Simulation time 340959780464 ps
CPU time 210.4 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 05:52:49 PM PDT 24
Peak memory 201944 kb
Host smart-92a745ca-25f3-41ab-a8d0-9257dc37a854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123135262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1123135262
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1720707085
Short name T498
Test name
Test status
Simulation time 161303890277 ps
CPU time 36.38 seconds
Started Jul 11 05:49:08 PM PDT 24
Finished Jul 11 05:49:51 PM PDT 24
Peak memory 201860 kb
Host smart-b6970682-a1d7-494c-928e-081e0d2c9f52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720707085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1720707085
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.592839081
Short name T642
Test name
Test status
Simulation time 325464763423 ps
CPU time 764.56 seconds
Started Jul 11 05:49:10 PM PDT 24
Finished Jul 11 06:02:01 PM PDT 24
Peak memory 201992 kb
Host smart-62a48fdb-1186-4dca-bb99-d770fd65fb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592839081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.592839081
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1311875466
Short name T696
Test name
Test status
Simulation time 325017344473 ps
CPU time 733.6 seconds
Started Jul 11 05:49:16 PM PDT 24
Finished Jul 11 06:01:33 PM PDT 24
Peak memory 201836 kb
Host smart-e5d28b57-a93c-407f-b381-d598fac1077d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311875466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1311875466
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3809920353
Short name T301
Test name
Test status
Simulation time 517807060620 ps
CPU time 648.71 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 06:00:06 PM PDT 24
Peak memory 201984 kb
Host smart-63d5c41e-180b-46ff-8e58-1eaa39d7b2d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809920353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3809920353
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2344483186
Short name T504
Test name
Test status
Simulation time 411125380016 ps
CPU time 435.12 seconds
Started Jul 11 05:49:19 PM PDT 24
Finished Jul 11 05:56:36 PM PDT 24
Peak memory 201876 kb
Host smart-e539436b-55a8-463c-822e-f15fb7bd864c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344483186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2344483186
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.191465945
Short name T632
Test name
Test status
Simulation time 78180331743 ps
CPU time 375.88 seconds
Started Jul 11 05:49:06 PM PDT 24
Finished Jul 11 05:55:30 PM PDT 24
Peak memory 202288 kb
Host smart-160e0ffe-7c38-428f-acd2-514c357705a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191465945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.191465945
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3851981109
Short name T91
Test name
Test status
Simulation time 28542937251 ps
CPU time 16.92 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 05:49:35 PM PDT 24
Peak memory 201664 kb
Host smart-af93e443-e61c-457e-bdee-799660edd643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851981109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3851981109
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1543242228
Short name T415
Test name
Test status
Simulation time 3832269993 ps
CPU time 2.87 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 05:49:20 PM PDT 24
Peak memory 201748 kb
Host smart-ceb425d1-4113-492d-a268-db2d1b548da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543242228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1543242228
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2967608083
Short name T769
Test name
Test status
Simulation time 6085729316 ps
CPU time 4.56 seconds
Started Jul 11 05:49:13 PM PDT 24
Finished Jul 11 05:49:22 PM PDT 24
Peak memory 201704 kb
Host smart-d1af25ad-75c3-46bb-b3b8-4dfe9638e75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967608083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2967608083
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.385688180
Short name T680
Test name
Test status
Simulation time 438348165924 ps
CPU time 805.96 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 06:02:44 PM PDT 24
Peak memory 201892 kb
Host smart-7a23805b-ab53-4f9b-8205-7e6ce481fcde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385688180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
385688180
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3592678098
Short name T736
Test name
Test status
Simulation time 374492825 ps
CPU time 0.86 seconds
Started Jul 11 05:49:19 PM PDT 24
Finished Jul 11 05:49:22 PM PDT 24
Peak memory 201652 kb
Host smart-1d4d4f54-3482-4038-9d02-7289ffb1f3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592678098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3592678098
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2474921499
Short name T742
Test name
Test status
Simulation time 552866163663 ps
CPU time 649.41 seconds
Started Jul 11 05:49:18 PM PDT 24
Finished Jul 11 06:00:10 PM PDT 24
Peak memory 201832 kb
Host smart-822cff2b-c963-4b11-9246-4d50f4af4a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474921499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2474921499
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1715403476
Short name T283
Test name
Test status
Simulation time 163518865132 ps
CPU time 102.38 seconds
Started Jul 11 05:49:14 PM PDT 24
Finished Jul 11 05:51:00 PM PDT 24
Peak memory 201932 kb
Host smart-ae8a17f6-2004-4c03-a728-18b4ec8a0edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715403476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1715403476
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.884705731
Short name T519
Test name
Test status
Simulation time 499654721244 ps
CPU time 1221.59 seconds
Started Jul 11 05:49:11 PM PDT 24
Finished Jul 11 06:09:38 PM PDT 24
Peak memory 201936 kb
Host smart-80cf910d-aa10-437e-ab68-97f4a77fd5b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=884705731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.884705731
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3994912824
Short name T219
Test name
Test status
Simulation time 163362694826 ps
CPU time 29.65 seconds
Started Jul 11 05:49:08 PM PDT 24
Finished Jul 11 05:49:45 PM PDT 24
Peak memory 201896 kb
Host smart-c5e7a70a-e234-450f-97f2-2059cd4d825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994912824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3994912824
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.804768521
Short name T463
Test name
Test status
Simulation time 483638616899 ps
CPU time 251.35 seconds
Started Jul 11 05:49:07 PM PDT 24
Finished Jul 11 05:53:26 PM PDT 24
Peak memory 201896 kb
Host smart-1af19862-8e21-440f-bf8a-66b4f5f00bec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=804768521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.804768521
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.852800307
Short name T211
Test name
Test status
Simulation time 365587758368 ps
CPU time 131.29 seconds
Started Jul 11 05:49:11 PM PDT 24
Finished Jul 11 05:51:28 PM PDT 24
Peak memory 201904 kb
Host smart-ef5f1bcf-6047-40e1-9dc6-01886f9b8d51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852800307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.852800307
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.438842114
Short name T517
Test name
Test status
Simulation time 397208317010 ps
CPU time 424.79 seconds
Started Jul 11 05:49:11 PM PDT 24
Finished Jul 11 05:56:21 PM PDT 24
Peak memory 201900 kb
Host smart-be1b41ac-c0c1-411c-9f5f-84673ae9a836
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438842114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.438842114
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1309945734
Short name T499
Test name
Test status
Simulation time 69501791749 ps
CPU time 419.44 seconds
Started Jul 11 05:49:23 PM PDT 24
Finished Jul 11 05:56:24 PM PDT 24
Peak memory 202284 kb
Host smart-4fb9e551-b80f-49e7-9c04-d768d050ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309945734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1309945734
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.364995309
Short name T450
Test name
Test status
Simulation time 44183520975 ps
CPU time 26.7 seconds
Started Jul 11 05:49:27 PM PDT 24
Finished Jul 11 05:49:55 PM PDT 24
Peak memory 201716 kb
Host smart-168e1178-d772-417b-abb1-dedce86af078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364995309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.364995309
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.524279097
Short name T112
Test name
Test status
Simulation time 2938097512 ps
CPU time 6.52 seconds
Started Jul 11 05:49:17 PM PDT 24
Finished Jul 11 05:49:26 PM PDT 24
Peak memory 201652 kb
Host smart-b77c93d5-6d57-4bfc-863c-a458397b3773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524279097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.524279097
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1242440414
Short name T240
Test name
Test status
Simulation time 5850556954 ps
CPU time 4.9 seconds
Started Jul 11 05:49:18 PM PDT 24
Finished Jul 11 05:49:25 PM PDT 24
Peak memory 201704 kb
Host smart-7b9c4bb2-47e1-4b2d-89df-d6f3f87e3ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242440414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1242440414
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.4015966771
Short name T495
Test name
Test status
Simulation time 26161057041 ps
CPU time 48.42 seconds
Started Jul 11 05:49:22 PM PDT 24
Finished Jul 11 05:50:12 PM PDT 24
Peak memory 210592 kb
Host smart-211af25a-0a9e-48e6-87af-f5df3c524f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015966771 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.4015966771
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3249489934
Short name T542
Test name
Test status
Simulation time 411143433 ps
CPU time 0.87 seconds
Started Jul 11 05:49:25 PM PDT 24
Finished Jul 11 05:49:27 PM PDT 24
Peak memory 201656 kb
Host smart-48ee4314-0b65-41ef-b02b-18abb55db202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249489934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3249489934
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.4059638692
Short name T200
Test name
Test status
Simulation time 418732954410 ps
CPU time 68.49 seconds
Started Jul 11 05:49:16 PM PDT 24
Finished Jul 11 05:50:28 PM PDT 24
Peak memory 201936 kb
Host smart-3af0f41a-5009-41ab-94ce-e5dd82f614e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059638692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.4059638692
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.198382863
Short name T312
Test name
Test status
Simulation time 209116945314 ps
CPU time 436.59 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:56:54 PM PDT 24
Peak memory 201752 kb
Host smart-c8703671-2a6c-4a31-9d6c-04888bf16051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198382863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.198382863
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2947221383
Short name T458
Test name
Test status
Simulation time 491642264385 ps
CPU time 280.44 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:54:18 PM PDT 24
Peak memory 201696 kb
Host smart-f355ac1a-74f4-4470-abba-9d2cf51549dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947221383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2947221383
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1871530772
Short name T434
Test name
Test status
Simulation time 324409499877 ps
CPU time 676.61 seconds
Started Jul 11 05:49:19 PM PDT 24
Finished Jul 11 06:00:37 PM PDT 24
Peak memory 201876 kb
Host smart-3f62c804-e96f-4851-8074-3810e299225d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871530772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1871530772
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.21450789
Short name T593
Test name
Test status
Simulation time 161933960412 ps
CPU time 352.57 seconds
Started Jul 11 05:49:27 PM PDT 24
Finished Jul 11 05:55:21 PM PDT 24
Peak memory 201920 kb
Host smart-62b63cd1-179e-4ad6-8bed-50065b2607b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21450789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.21450789
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.881083473
Short name T454
Test name
Test status
Simulation time 496880147027 ps
CPU time 1174.08 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 06:09:10 PM PDT 24
Peak memory 201964 kb
Host smart-1d86a1a6-7baf-4a73-b7a0-48983ef18ce1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=881083473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.881083473
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.353442291
Short name T511
Test name
Test status
Simulation time 169230252339 ps
CPU time 343.92 seconds
Started Jul 11 05:49:18 PM PDT 24
Finished Jul 11 05:55:04 PM PDT 24
Peak memory 201912 kb
Host smart-6a1e0ca0-2201-467c-8ad7-53d337239f11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353442291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.353442291
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3696578984
Short name T228
Test name
Test status
Simulation time 604648284290 ps
CPU time 358.15 seconds
Started Jul 11 05:49:18 PM PDT 24
Finished Jul 11 05:55:19 PM PDT 24
Peak memory 201892 kb
Host smart-125dab38-a744-4c87-915e-239b83d496fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696578984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3696578984
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1080483506
Short name T659
Test name
Test status
Simulation time 79547059996 ps
CPU time 442.08 seconds
Started Jul 11 05:49:21 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 202264 kb
Host smart-5eb4695c-60f1-4ac3-8ef7-5f88c761f819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080483506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1080483506
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.129182672
Short name T691
Test name
Test status
Simulation time 26533651296 ps
CPU time 56.29 seconds
Started Jul 11 05:49:31 PM PDT 24
Finished Jul 11 05:50:29 PM PDT 24
Peak memory 201604 kb
Host smart-fc843e62-8921-465e-a260-ad7ae71ab121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129182672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.129182672
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3552587781
Short name T382
Test name
Test status
Simulation time 5139338038 ps
CPU time 3.36 seconds
Started Jul 11 05:49:23 PM PDT 24
Finished Jul 11 05:49:28 PM PDT 24
Peak memory 201588 kb
Host smart-1b372d44-d77f-46e6-8c3e-7532a039b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552587781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3552587781
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4277079815
Short name T533
Test name
Test status
Simulation time 5951735011 ps
CPU time 2.06 seconds
Started Jul 11 05:49:23 PM PDT 24
Finished Jul 11 05:49:26 PM PDT 24
Peak memory 201700 kb
Host smart-0be10009-af13-4c4d-acdc-502e2bc1d47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277079815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4277079815
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3724792527
Short name T361
Test name
Test status
Simulation time 780414256505 ps
CPU time 2220.85 seconds
Started Jul 11 05:49:26 PM PDT 24
Finished Jul 11 06:26:29 PM PDT 24
Peak memory 202196 kb
Host smart-61370d44-ad73-44cd-a9b8-d0c441e52b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724792527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3724792527
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2154925791
Short name T697
Test name
Test status
Simulation time 99038097183 ps
CPU time 231.68 seconds
Started Jul 11 05:49:28 PM PDT 24
Finished Jul 11 05:53:21 PM PDT 24
Peak memory 210296 kb
Host smart-2924ed95-dfc3-44f7-82fe-da214df6111e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154925791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2154925791
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3247931949
Short name T485
Test name
Test status
Simulation time 474354539 ps
CPU time 1.58 seconds
Started Jul 11 05:49:41 PM PDT 24
Finished Jul 11 05:49:44 PM PDT 24
Peak memory 201668 kb
Host smart-e124276e-1f3e-4dc4-a3f6-40a2dabc7f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247931949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3247931949
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.189310363
Short name T92
Test name
Test status
Simulation time 168563246663 ps
CPU time 369.97 seconds
Started Jul 11 05:49:29 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 201928 kb
Host smart-d8a4a4e7-4eaa-4f46-bbab-1e555c3b4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189310363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.189310363
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2946175670
Short name T368
Test name
Test status
Simulation time 162935405891 ps
CPU time 378.29 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 201952 kb
Host smart-f193b56f-b58a-410f-98f1-74eb2d20abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946175670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2946175670
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2582864831
Short name T522
Test name
Test status
Simulation time 332638679386 ps
CPU time 725.98 seconds
Started Jul 11 05:49:40 PM PDT 24
Finished Jul 11 06:01:48 PM PDT 24
Peak memory 201824 kb
Host smart-2a0f7430-c391-4fd7-8343-b556a1284712
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582864831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2582864831
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3369769211
Short name T24
Test name
Test status
Simulation time 490480124109 ps
CPU time 288.55 seconds
Started Jul 11 05:49:25 PM PDT 24
Finished Jul 11 05:54:14 PM PDT 24
Peak memory 201892 kb
Host smart-a33085b6-0d94-4bf3-9809-d0917cab3c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369769211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3369769211
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3393125078
Short name T391
Test name
Test status
Simulation time 333742391448 ps
CPU time 750.67 seconds
Started Jul 11 05:49:31 PM PDT 24
Finished Jul 11 06:02:03 PM PDT 24
Peak memory 201876 kb
Host smart-b552ff6b-7942-4d70-9eb9-e69f86415b92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393125078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3393125078
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1499579779
Short name T142
Test name
Test status
Simulation time 364799479583 ps
CPU time 378.5 seconds
Started Jul 11 05:49:21 PM PDT 24
Finished Jul 11 05:55:40 PM PDT 24
Peak memory 201920 kb
Host smart-5f7c2a1f-a1ad-4f42-a2a1-912be64cc020
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499579779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1499579779
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.693135979
Short name T87
Test name
Test status
Simulation time 607715631794 ps
CPU time 661.83 seconds
Started Jul 11 05:49:29 PM PDT 24
Finished Jul 11 06:00:32 PM PDT 24
Peak memory 201868 kb
Host smart-b827f91a-6a5b-4116-a3f4-d7bb4bb73339
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693135979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.693135979
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.666796943
Short name T670
Test name
Test status
Simulation time 36286299720 ps
CPU time 76.82 seconds
Started Jul 11 05:49:33 PM PDT 24
Finished Jul 11 05:50:51 PM PDT 24
Peak memory 201672 kb
Host smart-1e710cf4-cf14-45b7-8ab2-442e63c15565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666796943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.666796943
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.292315740
Short name T512
Test name
Test status
Simulation time 5681743734 ps
CPU time 3.76 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:49:41 PM PDT 24
Peak memory 201696 kb
Host smart-312cd12c-33b2-455f-bdaa-6cdac325b524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292315740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.292315740
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.4155888661
Short name T616
Test name
Test status
Simulation time 5729419164 ps
CPU time 12.75 seconds
Started Jul 11 05:49:26 PM PDT 24
Finished Jul 11 05:49:40 PM PDT 24
Peak memory 201708 kb
Host smart-99c675b5-8bb4-4c4d-8080-c5963de3c44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155888661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4155888661
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3045834368
Short name T318
Test name
Test status
Simulation time 476409878181 ps
CPU time 1326.36 seconds
Started Jul 11 05:49:23 PM PDT 24
Finished Jul 11 06:11:30 PM PDT 24
Peak memory 212556 kb
Host smart-c7659312-2173-47db-a6c9-0b3bc8f6bf77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045834368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3045834368
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.694583020
Short name T626
Test name
Test status
Simulation time 196875021150 ps
CPU time 135.07 seconds
Started Jul 11 05:49:25 PM PDT 24
Finished Jul 11 05:51:42 PM PDT 24
Peak memory 210612 kb
Host smart-4090a8fa-b866-4a3d-a13a-0338b7a4c4be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694583020 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.694583020
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1153287709
Short name T41
Test name
Test status
Simulation time 456921696 ps
CPU time 1.69 seconds
Started Jul 11 05:49:30 PM PDT 24
Finished Jul 11 05:49:33 PM PDT 24
Peak memory 201864 kb
Host smart-e3e01556-c499-4a56-b6ea-108ba5b1870a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153287709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1153287709
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1610529037
Short name T89
Test name
Test status
Simulation time 337120261860 ps
CPU time 110.41 seconds
Started Jul 11 05:49:31 PM PDT 24
Finished Jul 11 05:51:22 PM PDT 24
Peak memory 201900 kb
Host smart-fbca524b-6ae4-4804-b6ae-8068c11f0718
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610529037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1610529037
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2282416894
Short name T284
Test name
Test status
Simulation time 170667369388 ps
CPU time 381.37 seconds
Started Jul 11 05:49:34 PM PDT 24
Finished Jul 11 05:55:56 PM PDT 24
Peak memory 201916 kb
Host smart-90265ab3-992d-4058-b5c1-79fdffe6ff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282416894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2282416894
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2573271185
Short name T772
Test name
Test status
Simulation time 322920301185 ps
CPU time 765.71 seconds
Started Jul 11 05:49:32 PM PDT 24
Finished Jul 11 06:02:19 PM PDT 24
Peak memory 201948 kb
Host smart-3b69f001-7a94-4e44-9039-ac0a84492070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573271185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2573271185
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2401005660
Short name T567
Test name
Test status
Simulation time 164976160705 ps
CPU time 368.53 seconds
Started Jul 11 05:49:22 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 201876 kb
Host smart-4c545877-7023-47fc-b46e-d50962b03737
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401005660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2401005660
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1863395955
Short name T655
Test name
Test status
Simulation time 318255841393 ps
CPU time 726.32 seconds
Started Jul 11 05:49:40 PM PDT 24
Finished Jul 11 06:01:48 PM PDT 24
Peak memory 201872 kb
Host smart-b658937f-43c7-490e-9dca-3731409b90dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863395955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1863395955
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4294529783
Short name T202
Test name
Test status
Simulation time 493787118338 ps
CPU time 544.51 seconds
Started Jul 11 05:49:27 PM PDT 24
Finished Jul 11 05:58:33 PM PDT 24
Peak memory 201900 kb
Host smart-2e1258de-bf12-4772-9ec3-ddcfc6777f2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294529783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4294529783
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1388372456
Short name T580
Test name
Test status
Simulation time 555343254348 ps
CPU time 1237.84 seconds
Started Jul 11 05:49:22 PM PDT 24
Finished Jul 11 06:10:01 PM PDT 24
Peak memory 201912 kb
Host smart-20e8710b-60c7-45e9-856a-f0e8b14b2bdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388372456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1388372456
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1360829143
Short name T396
Test name
Test status
Simulation time 415520551617 ps
CPU time 563.73 seconds
Started Jul 11 05:49:40 PM PDT 24
Finished Jul 11 05:59:06 PM PDT 24
Peak memory 201784 kb
Host smart-81a55fcf-9c31-43de-97a6-21d673a0734e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360829143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1360829143
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.277058525
Short name T55
Test name
Test status
Simulation time 141590697957 ps
CPU time 749.59 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 06:02:06 PM PDT 24
Peak memory 202292 kb
Host smart-6c1021da-2f78-42af-bb4f-813893b7fa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277058525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.277058525
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.366321611
Short name T564
Test name
Test status
Simulation time 34847779448 ps
CPU time 39.17 seconds
Started Jul 11 05:49:31 PM PDT 24
Finished Jul 11 05:50:12 PM PDT 24
Peak memory 201632 kb
Host smart-377e5e9e-569c-4373-803c-8298f33ca22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366321611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.366321611
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.827399728
Short name T109
Test name
Test status
Simulation time 4762493047 ps
CPU time 11.25 seconds
Started Jul 11 05:49:32 PM PDT 24
Finished Jul 11 05:49:44 PM PDT 24
Peak memory 201728 kb
Host smart-45f0f0ad-1c71-4751-a07f-d85c06eba658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827399728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.827399728
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.4045972150
Short name T733
Test name
Test status
Simulation time 5741124331 ps
CPU time 14.19 seconds
Started Jul 11 05:49:26 PM PDT 24
Finished Jul 11 05:49:42 PM PDT 24
Peak memory 201716 kb
Host smart-63a274fe-b4aa-48f4-ba07-0c2f63902072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045972150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.4045972150
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.611037002
Short name T111
Test name
Test status
Simulation time 249713155264 ps
CPU time 1297.01 seconds
Started Jul 11 05:49:41 PM PDT 24
Finished Jul 11 06:11:19 PM PDT 24
Peak memory 202212 kb
Host smart-36c13454-b097-4d38-9bbe-ceb662dc0579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611037002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
611037002
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1531943120
Short name T673
Test name
Test status
Simulation time 315195942 ps
CPU time 0.8 seconds
Started Jul 11 05:49:51 PM PDT 24
Finished Jul 11 05:49:52 PM PDT 24
Peak memory 201656 kb
Host smart-770317d7-f557-4c5d-903d-a7496982f7d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531943120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1531943120
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.787456877
Short name T270
Test name
Test status
Simulation time 182575890523 ps
CPU time 107.35 seconds
Started Jul 11 05:49:37 PM PDT 24
Finished Jul 11 05:51:26 PM PDT 24
Peak memory 201948 kb
Host smart-d7b0ecf5-db44-4fdf-866c-94cdb294d1d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787456877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.787456877
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1753501308
Short name T221
Test name
Test status
Simulation time 190515306402 ps
CPU time 204.35 seconds
Started Jul 11 05:49:37 PM PDT 24
Finished Jul 11 05:53:03 PM PDT 24
Peak memory 201980 kb
Host smart-6ddf4122-fe7d-406f-bb9a-c6219dc61fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753501308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1753501308
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3745130486
Short name T338
Test name
Test status
Simulation time 497992970388 ps
CPU time 156.84 seconds
Started Jul 11 05:49:33 PM PDT 24
Finished Jul 11 05:52:11 PM PDT 24
Peak memory 201864 kb
Host smart-fd4fbe9c-4cb2-48cc-a6c0-6efe24d82ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745130486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3745130486
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3410822316
Short name T150
Test name
Test status
Simulation time 492190675270 ps
CPU time 297.11 seconds
Started Jul 11 05:49:31 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 201904 kb
Host smart-09065ff0-a1de-4292-9448-5e875e932a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410822316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3410822316
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2368558523
Short name T402
Test name
Test status
Simulation time 330288040538 ps
CPU time 468.93 seconds
Started Jul 11 05:49:32 PM PDT 24
Finished Jul 11 05:57:22 PM PDT 24
Peak memory 201880 kb
Host smart-a3cf8e0f-6e9a-45b5-909c-2dca211379ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368558523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2368558523
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2810599039
Short name T701
Test name
Test status
Simulation time 357106252385 ps
CPU time 221.91 seconds
Started Jul 11 05:49:33 PM PDT 24
Finished Jul 11 05:53:16 PM PDT 24
Peak memory 201852 kb
Host smart-eb53af32-c8df-4278-b08e-9723369e9197
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810599039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2810599039
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.195424634
Short name T540
Test name
Test status
Simulation time 191805990886 ps
CPU time 43.18 seconds
Started Jul 11 05:49:35 PM PDT 24
Finished Jul 11 05:50:20 PM PDT 24
Peak memory 201896 kb
Host smart-463df7ce-1bae-45d7-99cd-56656c31c146
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195424634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.195424634
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.46649011
Short name T52
Test name
Test status
Simulation time 87953316920 ps
CPU time 353.21 seconds
Started Jul 11 05:49:39 PM PDT 24
Finished Jul 11 05:55:33 PM PDT 24
Peak memory 202228 kb
Host smart-c3e7a86e-5079-4214-83d3-eda1373afd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46649011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.46649011
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2090697255
Short name T492
Test name
Test status
Simulation time 36972184519 ps
CPU time 85.55 seconds
Started Jul 11 05:49:36 PM PDT 24
Finished Jul 11 05:51:04 PM PDT 24
Peak memory 201700 kb
Host smart-81ecf1fc-4d4d-44b5-ac5a-4360ae948dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090697255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2090697255
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4289551116
Short name T412
Test name
Test status
Simulation time 3888370566 ps
CPU time 5.02 seconds
Started Jul 11 05:49:48 PM PDT 24
Finished Jul 11 05:49:54 PM PDT 24
Peak memory 201708 kb
Host smart-a0ec49eb-1455-4c89-8485-e859d12c541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289551116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4289551116
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.550485569
Short name T435
Test name
Test status
Simulation time 5833475388 ps
CPU time 4.06 seconds
Started Jul 11 05:49:32 PM PDT 24
Finished Jul 11 05:49:37 PM PDT 24
Peak memory 201700 kb
Host smart-5e20e82a-b265-4815-8934-8c86e325e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550485569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.550485569
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1049850455
Short name T726
Test name
Test status
Simulation time 167249750257 ps
CPU time 371.57 seconds
Started Jul 11 05:49:36 PM PDT 24
Finished Jul 11 05:55:50 PM PDT 24
Peak memory 201872 kb
Host smart-1c3814bc-d970-41c5-8ab0-42f4e1c5090f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049850455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1049850455
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.124418571
Short name T788
Test name
Test status
Simulation time 82073045706 ps
CPU time 165.51 seconds
Started Jul 11 05:49:40 PM PDT 24
Finished Jul 11 05:52:27 PM PDT 24
Peak memory 202048 kb
Host smart-58583047-dce6-4f25-815d-a9c76784bac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124418571 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.124418571
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1549745759
Short name T164
Test name
Test status
Simulation time 449641535 ps
CPU time 0.72 seconds
Started Jul 11 05:49:52 PM PDT 24
Finished Jul 11 05:49:54 PM PDT 24
Peak memory 201656 kb
Host smart-c1cc4e1f-bb16-4391-bba7-3e551385a538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549745759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1549745759
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3191501993
Short name T747
Test name
Test status
Simulation time 496868284686 ps
CPU time 1160 seconds
Started Jul 11 05:49:46 PM PDT 24
Finished Jul 11 06:09:07 PM PDT 24
Peak memory 201972 kb
Host smart-cc8c8993-4472-49c6-a587-27530f21ebab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191501993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3191501993
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2538688059
Short name T209
Test name
Test status
Simulation time 167181767370 ps
CPU time 24.72 seconds
Started Jul 11 05:49:41 PM PDT 24
Finished Jul 11 05:50:07 PM PDT 24
Peak memory 201904 kb
Host smart-e3d916a7-4a5f-4b3a-85ae-1cdb6b5bad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538688059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2538688059
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1982172343
Short name T575
Test name
Test status
Simulation time 483476361731 ps
CPU time 236.95 seconds
Started Jul 11 05:49:37 PM PDT 24
Finished Jul 11 05:53:36 PM PDT 24
Peak memory 202096 kb
Host smart-b9bb6ccb-3e40-450b-b127-e4bf6d607099
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982172343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1982172343
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2075853947
Short name T210
Test name
Test status
Simulation time 494516377567 ps
CPU time 1127.14 seconds
Started Jul 11 05:49:43 PM PDT 24
Finished Jul 11 06:08:31 PM PDT 24
Peak memory 201928 kb
Host smart-a8f8706c-79ee-4ff8-8f5b-a8d586af0d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075853947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2075853947
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.999421221
Short name T203
Test name
Test status
Simulation time 492991620205 ps
CPU time 1015.16 seconds
Started Jul 11 05:49:42 PM PDT 24
Finished Jul 11 06:06:38 PM PDT 24
Peak memory 201896 kb
Host smart-108f5b4f-5da6-4046-be5a-10bb857b6fb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=999421221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.999421221
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2627309800
Short name T640
Test name
Test status
Simulation time 370889889171 ps
CPU time 906.3 seconds
Started Jul 11 05:49:40 PM PDT 24
Finished Jul 11 06:04:48 PM PDT 24
Peak memory 201912 kb
Host smart-82a12168-b37e-42e8-8267-88d1806f56bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627309800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2627309800
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2676031819
Short name T646
Test name
Test status
Simulation time 386707473377 ps
CPU time 227.15 seconds
Started Jul 11 05:49:37 PM PDT 24
Finished Jul 11 05:53:26 PM PDT 24
Peak memory 201920 kb
Host smart-4334dceb-5aae-4267-8e34-842761101d55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676031819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2676031819
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.143179511
Short name T624
Test name
Test status
Simulation time 82695003977 ps
CPU time 246.2 seconds
Started Jul 11 05:49:45 PM PDT 24
Finished Jul 11 05:53:52 PM PDT 24
Peak memory 202268 kb
Host smart-0da3df60-461f-4bbd-a6fe-82772309004a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143179511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.143179511
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1226561041
Short name T443
Test name
Test status
Simulation time 47003169685 ps
CPU time 111.48 seconds
Started Jul 11 05:49:57 PM PDT 24
Finished Jul 11 05:51:50 PM PDT 24
Peak memory 201624 kb
Host smart-2c405a3a-2dda-4d3d-b4b7-f54d62155bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226561041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1226561041
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3787552959
Short name T644
Test name
Test status
Simulation time 4338183527 ps
CPU time 1.94 seconds
Started Jul 11 05:49:44 PM PDT 24
Finished Jul 11 05:49:47 PM PDT 24
Peak memory 201696 kb
Host smart-01a145c4-8aeb-4bb7-a3a4-53a14ca232aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787552959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3787552959
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4111041250
Short name T413
Test name
Test status
Simulation time 5707739927 ps
CPU time 7.59 seconds
Started Jul 11 05:49:38 PM PDT 24
Finished Jul 11 05:49:47 PM PDT 24
Peak memory 201716 kb
Host smart-b809ca57-edc7-4149-b5d9-fe3ae0699a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111041250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4111041250
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3899154993
Short name T741
Test name
Test status
Simulation time 521575089599 ps
CPU time 1680.97 seconds
Started Jul 11 05:49:46 PM PDT 24
Finished Jul 11 06:17:48 PM PDT 24
Peak memory 213792 kb
Host smart-31d65b54-6923-447a-9aea-e2e34db1c604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899154993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3899154993
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1423913774
Short name T326
Test name
Test status
Simulation time 219514514964 ps
CPU time 127.48 seconds
Started Jul 11 05:49:49 PM PDT 24
Finished Jul 11 05:51:57 PM PDT 24
Peak memory 216988 kb
Host smart-908f9407-3b79-4cdc-ae38-e43ab9bfca4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423913774 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1423913774
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2372688481
Short name T767
Test name
Test status
Simulation time 431686432 ps
CPU time 1.03 seconds
Started Jul 11 05:50:00 PM PDT 24
Finished Jul 11 05:50:02 PM PDT 24
Peak memory 201632 kb
Host smart-2b3a92c0-9225-433c-bd55-dba117cbde01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372688481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2372688481
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.707533384
Short name T346
Test name
Test status
Simulation time 162100502633 ps
CPU time 174.21 seconds
Started Jul 11 05:49:55 PM PDT 24
Finished Jul 11 05:52:50 PM PDT 24
Peak memory 201888 kb
Host smart-541eb054-9cc8-4fe5-89af-a9430e97fa0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707533384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.707533384
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3546514119
Short name T222
Test name
Test status
Simulation time 163861414444 ps
CPU time 66.57 seconds
Started Jul 11 05:49:49 PM PDT 24
Finished Jul 11 05:50:57 PM PDT 24
Peak memory 201916 kb
Host smart-92fe0374-9568-4b7b-b05e-39bb8ea923f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546514119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3546514119
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3827918235
Short name T569
Test name
Test status
Simulation time 164087689613 ps
CPU time 357.81 seconds
Started Jul 11 05:49:49 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 201920 kb
Host smart-1ea7a67e-1e5c-4417-aebe-e6c66d135976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827918235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3827918235
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.4037712190
Short name T224
Test name
Test status
Simulation time 159157911373 ps
CPU time 84.7 seconds
Started Jul 11 05:49:47 PM PDT 24
Finished Jul 11 05:51:12 PM PDT 24
Peak memory 201880 kb
Host smart-69ba1c92-8465-410e-a1b6-01a3a1901a4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037712190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.4037712190
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.751860499
Short name T38
Test name
Test status
Simulation time 165209997456 ps
CPU time 346.31 seconds
Started Jul 11 05:49:49 PM PDT 24
Finished Jul 11 05:55:36 PM PDT 24
Peak memory 201920 kb
Host smart-43abcbd5-bbe3-4a6d-b6ec-0cbf598dacb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751860499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.751860499
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2318262763
Short name T639
Test name
Test status
Simulation time 329300449953 ps
CPU time 113.19 seconds
Started Jul 11 05:49:57 PM PDT 24
Finished Jul 11 05:51:51 PM PDT 24
Peak memory 201792 kb
Host smart-89380d64-c848-4028-b6f4-bdce49356f88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318262763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2318262763
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.603957334
Short name T676
Test name
Test status
Simulation time 376508450065 ps
CPU time 794 seconds
Started Jul 11 05:49:53 PM PDT 24
Finished Jul 11 06:03:09 PM PDT 24
Peak memory 201976 kb
Host smart-5aa959fd-eddd-427e-a3b4-75f5d850828c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603957334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.603957334
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1455159317
Short name T422
Test name
Test status
Simulation time 198319665994 ps
CPU time 107.54 seconds
Started Jul 11 05:49:46 PM PDT 24
Finished Jul 11 05:51:34 PM PDT 24
Peak memory 201764 kb
Host smart-52c5f3ae-728c-4aeb-8863-5e42596b169b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455159317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1455159317
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3774434323
Short name T259
Test name
Test status
Simulation time 126262559452 ps
CPU time 635.42 seconds
Started Jul 11 05:49:52 PM PDT 24
Finished Jul 11 06:00:29 PM PDT 24
Peak memory 202220 kb
Host smart-bc61701f-06d1-45b8-a050-36466e1c9cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774434323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3774434323
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4138253695
Short name T108
Test name
Test status
Simulation time 28704378739 ps
CPU time 16.12 seconds
Started Jul 11 05:49:55 PM PDT 24
Finished Jul 11 05:50:13 PM PDT 24
Peak memory 201748 kb
Host smart-61a2e553-b829-4ab3-8fdb-a8912183b60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138253695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4138253695
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1873114724
Short name T419
Test name
Test status
Simulation time 4478493896 ps
CPU time 5.29 seconds
Started Jul 11 05:49:51 PM PDT 24
Finished Jul 11 05:49:57 PM PDT 24
Peak memory 201712 kb
Host smart-31667123-b2ae-4061-984b-3a0ee1da09ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873114724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1873114724
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1784105272
Short name T102
Test name
Test status
Simulation time 5560093492 ps
CPU time 3.72 seconds
Started Jul 11 05:49:49 PM PDT 24
Finished Jul 11 05:49:54 PM PDT 24
Peak memory 201660 kb
Host smart-1470bfb8-cc39-4e7c-9c69-a5b2fa96e70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784105272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1784105272
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2359157911
Short name T341
Test name
Test status
Simulation time 251935934011 ps
CPU time 482.89 seconds
Started Jul 11 05:49:55 PM PDT 24
Finished Jul 11 05:58:00 PM PDT 24
Peak memory 210408 kb
Host smart-48a43621-65f8-41e9-b5a4-16f46819df30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359157911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2359157911
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1336953226
Short name T253
Test name
Test status
Simulation time 268265101639 ps
CPU time 241.68 seconds
Started Jul 11 05:49:57 PM PDT 24
Finished Jul 11 05:54:00 PM PDT 24
Peak memory 210496 kb
Host smart-24792656-8f92-4f4c-a110-4a026ecb385f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336953226 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1336953226
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.721448274
Short name T558
Test name
Test status
Simulation time 490779159 ps
CPU time 1.6 seconds
Started Jul 11 05:49:52 PM PDT 24
Finished Jul 11 05:49:55 PM PDT 24
Peak memory 201668 kb
Host smart-4c3557b3-c8ee-4482-bb30-16ce6b500c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721448274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.721448274
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3648206133
Short name T233
Test name
Test status
Simulation time 495014365418 ps
CPU time 279.94 seconds
Started Jul 11 05:49:59 PM PDT 24
Finished Jul 11 05:54:40 PM PDT 24
Peak memory 201972 kb
Host smart-1790f1d6-d8f1-48f7-b421-b4b4a55e6929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648206133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3648206133
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4251516320
Short name T514
Test name
Test status
Simulation time 163822512961 ps
CPU time 364.59 seconds
Started Jul 11 05:49:49 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 201876 kb
Host smart-f662e55f-95a6-4997-aa0a-60ad177ba420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251516320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4251516320
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.136499749
Short name T621
Test name
Test status
Simulation time 492756579362 ps
CPU time 274.71 seconds
Started Jul 11 05:49:53 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 201872 kb
Host smart-961ae2d4-fdb5-4627-afae-8c24d46fbdd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=136499749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.136499749
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3553728222
Short name T191
Test name
Test status
Simulation time 329601458865 ps
CPU time 361.28 seconds
Started Jul 11 05:49:52 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 201944 kb
Host smart-095c943a-4e6f-4698-a225-93c48c423e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553728222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3553728222
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3285601276
Short name T236
Test name
Test status
Simulation time 489500537712 ps
CPU time 196.08 seconds
Started Jul 11 05:49:50 PM PDT 24
Finished Jul 11 05:53:07 PM PDT 24
Peak memory 202092 kb
Host smart-09f47a6b-e7b5-4441-ac36-a6eed7bdcce9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285601276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3285601276
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3272235649
Short name T310
Test name
Test status
Simulation time 417157012398 ps
CPU time 449.36 seconds
Started Jul 11 05:49:53 PM PDT 24
Finished Jul 11 05:57:24 PM PDT 24
Peak memory 201904 kb
Host smart-d5d7d474-3037-4500-8f8f-1eddcb102279
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272235649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3272235649
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3729859111
Short name T618
Test name
Test status
Simulation time 608815643407 ps
CPU time 260.9 seconds
Started Jul 11 05:49:52 PM PDT 24
Finished Jul 11 05:54:14 PM PDT 24
Peak memory 201900 kb
Host smart-f2f92796-b69f-4cac-8328-1f6a01e5fbe3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729859111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3729859111
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.165894304
Short name T56
Test name
Test status
Simulation time 69749280463 ps
CPU time 292.97 seconds
Started Jul 11 05:49:55 PM PDT 24
Finished Jul 11 05:54:49 PM PDT 24
Peak memory 202260 kb
Host smart-fdb60966-10d1-4f85-b3d0-9ef4ad84c74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165894304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.165894304
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4238700273
Short name T605
Test name
Test status
Simulation time 28241697170 ps
CPU time 32.17 seconds
Started Jul 11 05:49:53 PM PDT 24
Finished Jul 11 05:50:26 PM PDT 24
Peak memory 201664 kb
Host smart-1df43799-928d-40f4-a7bb-12d6fb799a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238700273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4238700273
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3991791434
Short name T425
Test name
Test status
Simulation time 3655241160 ps
CPU time 4.62 seconds
Started Jul 11 05:49:59 PM PDT 24
Finished Jul 11 05:50:05 PM PDT 24
Peak memory 201696 kb
Host smart-a7d718cc-bb3c-4e60-abfe-a090197cfb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991791434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3991791434
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1829254410
Short name T613
Test name
Test status
Simulation time 6108515987 ps
CPU time 14.77 seconds
Started Jul 11 05:49:59 PM PDT 24
Finished Jul 11 05:50:15 PM PDT 24
Peak memory 201688 kb
Host smart-17633b36-7c69-4614-aed1-711a5f56b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829254410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1829254410
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3714014661
Short name T185
Test name
Test status
Simulation time 198299769248 ps
CPU time 88.85 seconds
Started Jul 11 05:49:52 PM PDT 24
Finished Jul 11 05:51:23 PM PDT 24
Peak memory 201852 kb
Host smart-2a7e422b-9b58-4d4c-be64-5e447100b93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714014661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3714014661
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3622241390
Short name T610
Test name
Test status
Simulation time 159171878451 ps
CPU time 166.53 seconds
Started Jul 11 05:49:59 PM PDT 24
Finished Jul 11 05:52:47 PM PDT 24
Peak memory 210588 kb
Host smart-48ca4160-60ac-457c-8386-7cf32dec658a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622241390 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3622241390
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.413955836
Short name T387
Test name
Test status
Simulation time 443715454 ps
CPU time 1.02 seconds
Started Jul 11 05:48:23 PM PDT 24
Finished Jul 11 05:48:29 PM PDT 24
Peak memory 201652 kb
Host smart-7a760706-2e7f-4d8c-a3b0-5764214c8044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413955836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.413955836
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2765307304
Short name T760
Test name
Test status
Simulation time 490292919233 ps
CPU time 569.47 seconds
Started Jul 11 05:48:34 PM PDT 24
Finished Jul 11 05:58:05 PM PDT 24
Peak memory 201916 kb
Host smart-b7272d2e-d9e0-48b5-87ef-d05d548c1cf7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765307304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2765307304
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2884900689
Short name T148
Test name
Test status
Simulation time 353639278166 ps
CPU time 772.42 seconds
Started Jul 11 05:48:20 PM PDT 24
Finished Jul 11 06:01:18 PM PDT 24
Peak memory 202004 kb
Host smart-43c59fcc-5c76-4dc7-b4e6-494689c78598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884900689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2884900689
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2558522363
Short name T629
Test name
Test status
Simulation time 334475190511 ps
CPU time 799.93 seconds
Started Jul 11 05:48:24 PM PDT 24
Finished Jul 11 06:01:49 PM PDT 24
Peak memory 201900 kb
Host smart-1de75e74-ef28-4884-abc1-2973b7b2192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558522363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2558522363
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.413336836
Short name T729
Test name
Test status
Simulation time 499329430632 ps
CPU time 433.12 seconds
Started Jul 11 05:48:20 PM PDT 24
Finished Jul 11 05:55:39 PM PDT 24
Peak memory 202116 kb
Host smart-fabf2faf-7b5c-429e-afb5-0e71b6b462c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=413336836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.413336836
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2005285311
Short name T727
Test name
Test status
Simulation time 159438136285 ps
CPU time 98.53 seconds
Started Jul 11 05:48:23 PM PDT 24
Finished Jul 11 05:50:07 PM PDT 24
Peak memory 201884 kb
Host smart-305c6840-60ea-40f1-bb23-b9d46959b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005285311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2005285311
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2426039062
Short name T590
Test name
Test status
Simulation time 167685418132 ps
CPU time 53.2 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 05:49:23 PM PDT 24
Peak memory 201892 kb
Host smart-5d3a93cf-78d9-43d7-9660-867f4168380b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426039062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2426039062
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1250361366
Short name T572
Test name
Test status
Simulation time 185394659368 ps
CPU time 189.52 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:51:53 PM PDT 24
Peak memory 201920 kb
Host smart-c8ac3ac0-5b58-4672-9352-737f49aed5df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250361366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1250361366
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4038125789
Short name T794
Test name
Test status
Simulation time 194900569526 ps
CPU time 57.03 seconds
Started Jul 11 05:48:29 PM PDT 24
Finished Jul 11 05:49:28 PM PDT 24
Peak memory 201872 kb
Host smart-a592508d-15df-4687-9832-878b49045d91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038125789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4038125789
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2485329804
Short name T481
Test name
Test status
Simulation time 77318563738 ps
CPU time 273.94 seconds
Started Jul 11 05:48:36 PM PDT 24
Finished Jul 11 05:53:12 PM PDT 24
Peak memory 202220 kb
Host smart-f538654f-edce-4546-8020-3bac3096e192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485329804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2485329804
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3575413489
Short name T528
Test name
Test status
Simulation time 47238949809 ps
CPU time 55.27 seconds
Started Jul 11 05:48:22 PM PDT 24
Finished Jul 11 05:49:22 PM PDT 24
Peak memory 201668 kb
Host smart-265bcc64-f30f-49db-bbdb-ddf90a999606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575413489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3575413489
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2627369649
Short name T500
Test name
Test status
Simulation time 3914561573 ps
CPU time 1.26 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:48:40 PM PDT 24
Peak memory 201716 kb
Host smart-2541eb60-8a7e-4924-9a99-7411896a203d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627369649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2627369649
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2474429244
Short name T69
Test name
Test status
Simulation time 7857191398 ps
CPU time 13.2 seconds
Started Jul 11 05:48:33 PM PDT 24
Finished Jul 11 05:48:48 PM PDT 24
Peak memory 218188 kb
Host smart-dbc9e0e4-f8bb-4295-8c79-18745e6d32ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474429244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2474429244
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3399474149
Short name T706
Test name
Test status
Simulation time 6147205710 ps
CPU time 14.14 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:48:52 PM PDT 24
Peak memory 201700 kb
Host smart-ad8a8e73-a1cf-485d-a659-17ff6e87c9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399474149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3399474149
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2641164916
Short name T755
Test name
Test status
Simulation time 359927512046 ps
CPU time 70.36 seconds
Started Jul 11 05:48:48 PM PDT 24
Finished Jul 11 05:50:02 PM PDT 24
Peak memory 201864 kb
Host smart-215c0a5b-9a4e-4eb5-ad88-56b98f59c39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641164916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2641164916
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.4127731955
Short name T95
Test name
Test status
Simulation time 520403056 ps
CPU time 0.91 seconds
Started Jul 11 05:49:58 PM PDT 24
Finished Jul 11 05:50:01 PM PDT 24
Peak memory 201632 kb
Host smart-14b0f4f1-2436-494a-bd3c-b2c23754f232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127731955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.4127731955
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.741044950
Short name T140
Test name
Test status
Simulation time 174504008753 ps
CPU time 77.49 seconds
Started Jul 11 05:49:58 PM PDT 24
Finished Jul 11 05:51:17 PM PDT 24
Peak memory 201912 kb
Host smart-d66d8864-ee16-45d5-9f11-3f38be72cc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741044950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.741044950
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3193909153
Short name T342
Test name
Test status
Simulation time 321765625238 ps
CPU time 761.42 seconds
Started Jul 11 05:50:00 PM PDT 24
Finished Jul 11 06:02:43 PM PDT 24
Peak memory 201880 kb
Host smart-45813992-b559-4dca-bdb3-ab96edfd2762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193909153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3193909153
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3852471566
Short name T25
Test name
Test status
Simulation time 332725926801 ps
CPU time 371.49 seconds
Started Jul 11 05:49:58 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 201884 kb
Host smart-8d8d9ce6-8782-4626-97e2-26ae3eff6117
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852471566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3852471566
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2649340040
Short name T681
Test name
Test status
Simulation time 337925939752 ps
CPU time 673.22 seconds
Started Jul 11 05:49:57 PM PDT 24
Finished Jul 11 06:01:11 PM PDT 24
Peak memory 201980 kb
Host smart-9e0feb5e-7336-4b15-91a5-d2827b2b72c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649340040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2649340040
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.532048818
Short name T686
Test name
Test status
Simulation time 165019052648 ps
CPU time 354.24 seconds
Started Jul 11 05:49:51 PM PDT 24
Finished Jul 11 05:55:47 PM PDT 24
Peak memory 201976 kb
Host smart-0ca1b9e8-2902-478b-9c30-ecad4e93f4c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=532048818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.532048818
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2301976209
Short name T351
Test name
Test status
Simulation time 176879729011 ps
CPU time 398.27 seconds
Started Jul 11 05:49:59 PM PDT 24
Finished Jul 11 05:56:39 PM PDT 24
Peak memory 201968 kb
Host smart-dac529de-080f-44ba-b1d4-b193669d99d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301976209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2301976209
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.818212612
Short name T446
Test name
Test status
Simulation time 201509406097 ps
CPU time 418.98 seconds
Started Jul 11 05:50:05 PM PDT 24
Finished Jul 11 05:57:07 PM PDT 24
Peak memory 201948 kb
Host smart-d695191f-4537-41e8-9960-96e85efb2894
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818212612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.818212612
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.4079481499
Short name T53
Test name
Test status
Simulation time 80580835229 ps
CPU time 264.28 seconds
Started Jul 11 05:50:03 PM PDT 24
Finished Jul 11 05:54:29 PM PDT 24
Peak memory 202220 kb
Host smart-e750f5f7-4a91-4da0-8a3a-5293efbbbd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079481499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.4079481499
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.403987483
Short name T559
Test name
Test status
Simulation time 28577836458 ps
CPU time 24.68 seconds
Started Jul 11 05:50:01 PM PDT 24
Finished Jul 11 05:50:26 PM PDT 24
Peak memory 201708 kb
Host smart-88b0e015-7c0a-4c13-babc-67cf72612738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403987483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.403987483
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3637124342
Short name T244
Test name
Test status
Simulation time 4443917717 ps
CPU time 3.07 seconds
Started Jul 11 05:50:02 PM PDT 24
Finished Jul 11 05:50:06 PM PDT 24
Peak memory 201708 kb
Host smart-a7c01eb1-5c43-4773-ac04-266714714f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637124342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3637124342
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2360144793
Short name T429
Test name
Test status
Simulation time 5965905245 ps
CPU time 11.96 seconds
Started Jul 11 05:49:54 PM PDT 24
Finished Jul 11 05:50:08 PM PDT 24
Peak memory 201704 kb
Host smart-c58a6755-f2df-45e3-ae6c-3e83ae5a5f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360144793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2360144793
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4055438516
Short name T51
Test name
Test status
Simulation time 89329486967 ps
CPU time 455.76 seconds
Started Jul 11 05:49:58 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 202216 kb
Host smart-754039cb-26a3-4b1a-9be6-e34bce52f3ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055438516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4055438516
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3995549859
Short name T418
Test name
Test status
Simulation time 506543300 ps
CPU time 1.22 seconds
Started Jul 11 05:50:06 PM PDT 24
Finished Jul 11 05:50:09 PM PDT 24
Peak memory 201640 kb
Host smart-91711356-d876-4fa6-a1c3-25d39b4885c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995549859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3995549859
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2418936149
Short name T305
Test name
Test status
Simulation time 515718280288 ps
CPU time 1035.27 seconds
Started Jul 11 05:50:04 PM PDT 24
Finished Jul 11 06:07:22 PM PDT 24
Peak memory 201892 kb
Host smart-beba3aa3-10fa-4178-b923-962a0a9f79f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418936149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2418936149
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2869997969
Short name T371
Test name
Test status
Simulation time 161185839022 ps
CPU time 80.83 seconds
Started Jul 11 05:50:06 PM PDT 24
Finished Jul 11 05:51:29 PM PDT 24
Peak memory 201864 kb
Host smart-641d2e8f-7e3b-493b-9287-5b723d1ded78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869997969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2869997969
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4124911781
Short name T406
Test name
Test status
Simulation time 483486164759 ps
CPU time 298.83 seconds
Started Jul 11 05:50:03 PM PDT 24
Finished Jul 11 05:55:03 PM PDT 24
Peak memory 201860 kb
Host smart-426c9f1d-20d8-44ac-b750-50041ef6f231
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124911781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4124911781
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2333843243
Short name T356
Test name
Test status
Simulation time 489195386730 ps
CPU time 1152.44 seconds
Started Jul 11 05:50:05 PM PDT 24
Finished Jul 11 06:09:20 PM PDT 24
Peak memory 201912 kb
Host smart-9c28e1b5-ec3d-4ba1-9066-7f233f51d263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333843243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2333843243
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1828314401
Short name T797
Test name
Test status
Simulation time 154940869958 ps
CPU time 74.26 seconds
Started Jul 11 05:50:11 PM PDT 24
Finished Jul 11 05:51:26 PM PDT 24
Peak memory 201788 kb
Host smart-f620d698-b579-438b-b42e-af73020bd815
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828314401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1828314401
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2776765690
Short name T518
Test name
Test status
Simulation time 195072234277 ps
CPU time 103.53 seconds
Started Jul 11 05:50:05 PM PDT 24
Finished Jul 11 05:51:51 PM PDT 24
Peak memory 201936 kb
Host smart-7efe8057-c7d3-4259-bc57-168a69e7ae23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776765690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2776765690
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2088985146
Short name T508
Test name
Test status
Simulation time 30560163430 ps
CPU time 7.24 seconds
Started Jul 11 05:50:09 PM PDT 24
Finished Jul 11 05:50:17 PM PDT 24
Peak memory 201708 kb
Host smart-f5fc09b1-6fc9-42a4-a3ab-b2ec88269cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088985146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2088985146
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3205066609
Short name T539
Test name
Test status
Simulation time 3376413571 ps
CPU time 4.01 seconds
Started Jul 11 05:50:05 PM PDT 24
Finished Jul 11 05:50:12 PM PDT 24
Peak memory 201720 kb
Host smart-f0adf04b-d390-4a92-9e53-61775e2256f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205066609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3205066609
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.716543733
Short name T444
Test name
Test status
Simulation time 5910157048 ps
CPU time 14.43 seconds
Started Jul 11 05:49:58 PM PDT 24
Finished Jul 11 05:50:14 PM PDT 24
Peak memory 201652 kb
Host smart-e2909432-c180-4dee-bed9-3f301f6f62c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716543733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.716543733
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3073977303
Short name T660
Test name
Test status
Simulation time 326647310881 ps
CPU time 224.06 seconds
Started Jul 11 05:50:07 PM PDT 24
Finished Jul 11 05:53:53 PM PDT 24
Peak memory 201952 kb
Host smart-7ba1f929-bee5-4271-b174-d523241e5274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073977303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3073977303
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2322827599
Short name T295
Test name
Test status
Simulation time 96526555190 ps
CPU time 153.21 seconds
Started Jul 11 05:50:08 PM PDT 24
Finished Jul 11 05:52:43 PM PDT 24
Peak memory 218372 kb
Host smart-8eecd567-4422-433c-9679-720395217ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322827599 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2322827599
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.145365815
Short name T115
Test name
Test status
Simulation time 288373243 ps
CPU time 0.95 seconds
Started Jul 11 05:50:20 PM PDT 24
Finished Jul 11 05:50:22 PM PDT 24
Peak memory 201648 kb
Host smart-66279f51-f45c-4583-8988-eeb9a95a1d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145365815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.145365815
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1649352548
Short name T768
Test name
Test status
Simulation time 516041257380 ps
CPU time 229.16 seconds
Started Jul 11 05:50:14 PM PDT 24
Finished Jul 11 05:54:04 PM PDT 24
Peak memory 201884 kb
Host smart-a535bd07-f4de-4467-bd8c-73f93772c6a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649352548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1649352548
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2964192768
Short name T693
Test name
Test status
Simulation time 528570449103 ps
CPU time 1259.87 seconds
Started Jul 11 05:50:15 PM PDT 24
Finished Jul 11 06:11:15 PM PDT 24
Peak memory 201984 kb
Host smart-e74ab486-908e-4d30-bea9-5ac725a37769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964192768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2964192768
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1316329889
Short name T329
Test name
Test status
Simulation time 160012536255 ps
CPU time 326.31 seconds
Started Jul 11 05:50:03 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 201964 kb
Host smart-5a106b96-5d02-45a5-9495-6e917b866466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316329889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1316329889
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1572644236
Short name T683
Test name
Test status
Simulation time 163355149757 ps
CPU time 379.98 seconds
Started Jul 11 05:50:04 PM PDT 24
Finished Jul 11 05:56:27 PM PDT 24
Peak memory 201880 kb
Host smart-be32a8db-b3d2-4160-b5bd-2c5bc8c359de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572644236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1572644236
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1235280503
Short name T656
Test name
Test status
Simulation time 324417524092 ps
CPU time 192.2 seconds
Started Jul 11 05:50:07 PM PDT 24
Finished Jul 11 05:53:21 PM PDT 24
Peak memory 201980 kb
Host smart-e044d654-6f0d-4d0f-bc47-b0d9c63ad1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235280503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1235280503
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3881112739
Short name T445
Test name
Test status
Simulation time 499974449069 ps
CPU time 1099.48 seconds
Started Jul 11 05:50:05 PM PDT 24
Finished Jul 11 06:08:28 PM PDT 24
Peak memory 201876 kb
Host smart-8416ce2c-71e1-44f1-b56a-666294bd4d0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881112739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3881112739
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.792775054
Short name T324
Test name
Test status
Simulation time 369796529566 ps
CPU time 812 seconds
Started Jul 11 06:00:31 PM PDT 24
Finished Jul 11 06:14:14 PM PDT 24
Peak memory 201912 kb
Host smart-64a10681-6d0f-445b-b8fc-f1ff23c9dde1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792775054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.792775054
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.72928266
Short name T663
Test name
Test status
Simulation time 388912032618 ps
CPU time 460.39 seconds
Started Jul 11 05:50:03 PM PDT 24
Finished Jul 11 05:57:45 PM PDT 24
Peak memory 201936 kb
Host smart-02ccfa1f-3f42-4fe5-bc00-cd1ccb1a88df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72928266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
dc_ctrl_filters_wakeup_fixed.72928266
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2046364053
Short name T530
Test name
Test status
Simulation time 79186901394 ps
CPU time 293.96 seconds
Started Jul 11 05:50:21 PM PDT 24
Finished Jul 11 05:55:16 PM PDT 24
Peak memory 202220 kb
Host smart-39dbc258-96b6-4b11-abad-a3e44f36e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046364053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2046364053
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.19503419
Short name T653
Test name
Test status
Simulation time 26573465418 ps
CPU time 64.15 seconds
Started Jul 11 05:50:14 PM PDT 24
Finished Jul 11 05:51:19 PM PDT 24
Peak memory 201708 kb
Host smart-27b5dc1c-db91-4312-b9a4-adfd890ef0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19503419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.19503419
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4141675376
Short name T506
Test name
Test status
Simulation time 4274642071 ps
CPU time 10.42 seconds
Started Jul 11 05:50:14 PM PDT 24
Finished Jul 11 05:50:25 PM PDT 24
Peak memory 201708 kb
Host smart-8eaf00f9-e3f6-4a53-9422-3e89cbea06b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141675376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4141675376
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3831771617
Short name T762
Test name
Test status
Simulation time 5569055654 ps
CPU time 4.03 seconds
Started Jul 11 05:50:04 PM PDT 24
Finished Jul 11 05:50:09 PM PDT 24
Peak memory 201580 kb
Host smart-58448c6f-73cb-43fa-8a88-ecd4f1c0f4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831771617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3831771617
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3248509927
Short name T649
Test name
Test status
Simulation time 175971777558 ps
CPU time 58.11 seconds
Started Jul 11 05:50:12 PM PDT 24
Finished Jul 11 05:51:11 PM PDT 24
Peak memory 201896 kb
Host smart-6e069d1f-6fce-465d-9ed7-bef691ec0437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248509927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3248509927
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1898221178
Short name T561
Test name
Test status
Simulation time 724262100043 ps
CPU time 200.29 seconds
Started Jul 11 05:50:09 PM PDT 24
Finished Jul 11 05:53:31 PM PDT 24
Peak memory 210820 kb
Host smart-1a48b62d-69d6-4d3a-b69d-2a925f8afc94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898221178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1898221178
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1891642574
Short name T751
Test name
Test status
Simulation time 490554842 ps
CPU time 1.64 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:50:49 PM PDT 24
Peak memory 201668 kb
Host smart-a6834452-2fe7-483f-874b-b61325747939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891642574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1891642574
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4284987763
Short name T181
Test name
Test status
Simulation time 326181257102 ps
CPU time 139.18 seconds
Started Jul 11 05:50:23 PM PDT 24
Finished Jul 11 05:52:43 PM PDT 24
Peak memory 201896 kb
Host smart-320b893e-a333-49bd-a2a7-50912e800317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284987763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4284987763
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2683023899
Short name T477
Test name
Test status
Simulation time 322305008926 ps
CPU time 361.75 seconds
Started Jul 11 05:50:50 PM PDT 24
Finished Jul 11 05:56:52 PM PDT 24
Peak memory 201844 kb
Host smart-93d0659d-7926-4e60-a021-b6a7b3ca459f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683023899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2683023899
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4283837754
Short name T184
Test name
Test status
Simulation time 484803991826 ps
CPU time 274.86 seconds
Started Jul 11 05:50:22 PM PDT 24
Finished Jul 11 05:54:58 PM PDT 24
Peak memory 201880 kb
Host smart-b73d17e1-04ae-4199-adbb-ce5f1ce9b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283837754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4283837754
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3327188124
Short name T177
Test name
Test status
Simulation time 324817357608 ps
CPU time 177.06 seconds
Started Jul 11 05:50:50 PM PDT 24
Finished Jul 11 05:53:48 PM PDT 24
Peak memory 201860 kb
Host smart-b60c966d-d21f-4caa-932b-cb6adffa26ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327188124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3327188124
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2550455921
Short name T665
Test name
Test status
Simulation time 182383616668 ps
CPU time 107.28 seconds
Started Jul 11 05:50:23 PM PDT 24
Finished Jul 11 05:52:11 PM PDT 24
Peak memory 201832 kb
Host smart-426ffa3d-28d9-4c72-9b58-81334614a994
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550455921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2550455921
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2147019448
Short name T699
Test name
Test status
Simulation time 604322134467 ps
CPU time 691.52 seconds
Started Jul 11 05:50:19 PM PDT 24
Finished Jul 11 06:01:52 PM PDT 24
Peak memory 202096 kb
Host smart-228992f0-7c74-496a-842a-e143d7f9241a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147019448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2147019448
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2088969592
Short name T456
Test name
Test status
Simulation time 58441448793 ps
CPU time 262.92 seconds
Started Jul 11 05:50:44 PM PDT 24
Finished Jul 11 05:55:08 PM PDT 24
Peak memory 202244 kb
Host smart-b257eb0e-e245-4af4-af0f-1ecb1d6809da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088969592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2088969592
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.431889317
Short name T505
Test name
Test status
Simulation time 31153007386 ps
CPU time 71.45 seconds
Started Jul 11 05:50:24 PM PDT 24
Finished Jul 11 05:51:36 PM PDT 24
Peak memory 201668 kb
Host smart-dceffd3c-12cb-4e7c-b9b1-50b8dcd39268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431889317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.431889317
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1026203843
Short name T636
Test name
Test status
Simulation time 5022895788 ps
CPU time 3.48 seconds
Started Jul 11 05:50:18 PM PDT 24
Finished Jul 11 05:50:22 PM PDT 24
Peak memory 201688 kb
Host smart-effbc270-eddd-421d-be68-39563b3fd8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026203843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1026203843
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3288209306
Short name T420
Test name
Test status
Simulation time 5929384855 ps
CPU time 14.69 seconds
Started Jul 11 05:50:20 PM PDT 24
Finished Jul 11 05:50:36 PM PDT 24
Peak memory 201696 kb
Host smart-ed7fe7d0-1533-4732-bd04-52768f8b5884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288209306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3288209306
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1179953038
Short name T376
Test name
Test status
Simulation time 334613522763 ps
CPU time 142.39 seconds
Started Jul 11 05:50:21 PM PDT 24
Finished Jul 11 05:52:44 PM PDT 24
Peak memory 201908 kb
Host smart-f587843e-42b7-41a5-aec9-0815e05a0f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179953038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1179953038
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1227575013
Short name T258
Test name
Test status
Simulation time 113700703949 ps
CPU time 149.81 seconds
Started Jul 11 05:50:24 PM PDT 24
Finished Jul 11 05:52:54 PM PDT 24
Peak memory 210588 kb
Host smart-d2b47c42-cd6f-474f-93d9-dd9899392d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227575013 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1227575013
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1382594628
Short name T384
Test name
Test status
Simulation time 513624930 ps
CPU time 1.76 seconds
Started Jul 11 05:50:30 PM PDT 24
Finished Jul 11 05:50:32 PM PDT 24
Peak memory 201668 kb
Host smart-aa52cec0-ef39-449a-96cd-a7fda9c26a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382594628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1382594628
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3465221979
Short name T297
Test name
Test status
Simulation time 367915762215 ps
CPU time 110.5 seconds
Started Jul 11 05:50:47 PM PDT 24
Finished Jul 11 05:52:39 PM PDT 24
Peak memory 201908 kb
Host smart-c8cde2f0-358e-415c-8512-8976e0832948
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465221979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3465221979
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3960753127
Short name T608
Test name
Test status
Simulation time 328824536379 ps
CPU time 197.92 seconds
Started Jul 11 05:50:32 PM PDT 24
Finished Jul 11 05:53:51 PM PDT 24
Peak memory 201912 kb
Host smart-46463aad-b6e6-491a-95f9-52ed3d6761ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960753127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3960753127
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1426661426
Short name T374
Test name
Test status
Simulation time 320900714820 ps
CPU time 381.82 seconds
Started Jul 11 05:50:50 PM PDT 24
Finished Jul 11 05:57:12 PM PDT 24
Peak memory 201772 kb
Host smart-2925b508-9a8b-40f0-be1c-bd8203828fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426661426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1426661426
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.67133006
Short name T468
Test name
Test status
Simulation time 326974793751 ps
CPU time 584.22 seconds
Started Jul 11 05:50:48 PM PDT 24
Finished Jul 11 06:00:34 PM PDT 24
Peak memory 201904 kb
Host smart-ecd6f09b-d480-433a-9d19-78dbdafc263b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=67133006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt
_fixed.67133006
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.876346823
Short name T188
Test name
Test status
Simulation time 496564647135 ps
CPU time 275.39 seconds
Started Jul 11 05:50:28 PM PDT 24
Finished Jul 11 05:55:04 PM PDT 24
Peak memory 201908 kb
Host smart-8f61acf6-2b99-48a7-b7f3-09a383811133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876346823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.876346823
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4192476714
Short name T597
Test name
Test status
Simulation time 168396501380 ps
CPU time 106.91 seconds
Started Jul 11 05:50:20 PM PDT 24
Finished Jul 11 05:52:08 PM PDT 24
Peak memory 201940 kb
Host smart-dc256f75-52c8-437f-81c0-ffe050590416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192476714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4192476714
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3365820185
Short name T601
Test name
Test status
Simulation time 542646800400 ps
CPU time 1150.73 seconds
Started Jul 11 05:50:35 PM PDT 24
Finished Jul 11 06:09:46 PM PDT 24
Peak memory 201884 kb
Host smart-d36e8449-fbad-499b-a255-b514ab8cbcb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365820185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3365820185
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2944814071
Short name T101
Test name
Test status
Simulation time 406361726723 ps
CPU time 195.84 seconds
Started Jul 11 05:50:36 PM PDT 24
Finished Jul 11 05:53:53 PM PDT 24
Peak memory 201876 kb
Host smart-22973a15-09e9-4cc4-b3fb-b86e09dd3589
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944814071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2944814071
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4155074987
Short name T798
Test name
Test status
Simulation time 114125609237 ps
CPU time 375.88 seconds
Started Jul 11 05:50:32 PM PDT 24
Finished Jul 11 05:56:49 PM PDT 24
Peak memory 202300 kb
Host smart-1def68e8-a666-435f-b342-3925752edd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155074987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4155074987
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3034149560
Short name T467
Test name
Test status
Simulation time 36555507718 ps
CPU time 22.61 seconds
Started Jul 11 05:50:36 PM PDT 24
Finished Jul 11 05:50:59 PM PDT 24
Peak memory 201708 kb
Host smart-0763e925-5626-4690-aef4-adbe47341763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034149560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3034149560
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.871989982
Short name T437
Test name
Test status
Simulation time 4277673575 ps
CPU time 4.04 seconds
Started Jul 11 05:50:37 PM PDT 24
Finished Jul 11 05:50:42 PM PDT 24
Peak memory 201644 kb
Host smart-36c3700c-c0dc-414a-8da0-b02e5e1fb978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871989982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.871989982
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.981762147
Short name T436
Test name
Test status
Simulation time 5896000176 ps
CPU time 3.82 seconds
Started Jul 11 05:50:22 PM PDT 24
Finished Jul 11 05:50:27 PM PDT 24
Peak memory 201692 kb
Host smart-122480e2-4e6a-4475-9c02-32bde8a8fca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981762147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.981762147
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3693447970
Short name T682
Test name
Test status
Simulation time 41315234347 ps
CPU time 58.21 seconds
Started Jul 11 05:50:37 PM PDT 24
Finished Jul 11 05:51:36 PM PDT 24
Peak memory 210548 kb
Host smart-4368a002-6987-4ac9-9b14-264c3b71a736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693447970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3693447970
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3637311640
Short name T784
Test name
Test status
Simulation time 348125856 ps
CPU time 1 seconds
Started Jul 11 05:50:36 PM PDT 24
Finished Jul 11 05:50:38 PM PDT 24
Peak memory 201656 kb
Host smart-23a3a6a5-1c1e-4cfe-9ca2-d4a70c1f2502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637311640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3637311640
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.4235099222
Short name T372
Test name
Test status
Simulation time 334472426258 ps
CPU time 773.36 seconds
Started Jul 11 05:50:31 PM PDT 24
Finished Jul 11 06:03:25 PM PDT 24
Peak memory 201956 kb
Host smart-8a2d5cd9-2d3b-456b-9d1c-82a02cbf238a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235099222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.4235099222
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1482198941
Short name T143
Test name
Test status
Simulation time 334682932395 ps
CPU time 830.32 seconds
Started Jul 11 05:50:27 PM PDT 24
Finished Jul 11 06:04:18 PM PDT 24
Peak memory 201892 kb
Host smart-9e980f42-3b6e-49d7-8d88-0addf0113cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482198941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1482198941
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1631678552
Short name T262
Test name
Test status
Simulation time 168606007008 ps
CPU time 185.6 seconds
Started Jul 11 05:50:30 PM PDT 24
Finished Jul 11 05:53:36 PM PDT 24
Peak memory 201916 kb
Host smart-af071edb-6348-4c72-bbd1-2cc0228ac7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631678552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1631678552
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2711735186
Short name T113
Test name
Test status
Simulation time 158970334687 ps
CPU time 24.53 seconds
Started Jul 11 05:50:27 PM PDT 24
Finished Jul 11 05:50:53 PM PDT 24
Peak memory 201852 kb
Host smart-d98d2f0c-9f5a-47c6-9a22-8b4221c4cf95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711735186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2711735186
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2285547980
Short name T359
Test name
Test status
Simulation time 159259945738 ps
CPU time 130.65 seconds
Started Jul 11 05:50:32 PM PDT 24
Finished Jul 11 05:52:44 PM PDT 24
Peak memory 201980 kb
Host smart-0bf481f6-7005-439c-905c-522dc040882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285547980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2285547980
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4194288893
Short name T494
Test name
Test status
Simulation time 164185898007 ps
CPU time 99.26 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:52:27 PM PDT 24
Peak memory 201944 kb
Host smart-7a3f7ce9-aa94-4c2b-b28e-4dd6aafdea17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194288893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4194288893
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.298893378
Short name T32
Test name
Test status
Simulation time 194252642809 ps
CPU time 445.15 seconds
Started Jul 11 05:50:36 PM PDT 24
Finished Jul 11 05:58:02 PM PDT 24
Peak memory 201884 kb
Host smart-d5b70bb1-1f96-4fea-9439-9114e56a01ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298893378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.298893378
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3347198749
Short name T546
Test name
Test status
Simulation time 605637831448 ps
CPU time 185.11 seconds
Started Jul 11 05:50:29 PM PDT 24
Finished Jul 11 05:53:35 PM PDT 24
Peak memory 201900 kb
Host smart-5dac9904-6134-4d0e-add5-acc098551c69
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347198749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3347198749
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1330741812
Short name T483
Test name
Test status
Simulation time 78934523053 ps
CPU time 295.15 seconds
Started Jul 11 05:50:35 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 202232 kb
Host smart-1b425e99-f204-485a-9cd3-8ee765e9ba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330741812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1330741812
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1455443992
Short name T674
Test name
Test status
Simulation time 31597427036 ps
CPU time 21.23 seconds
Started Jul 11 05:50:39 PM PDT 24
Finished Jul 11 05:51:01 PM PDT 24
Peak memory 201712 kb
Host smart-550fe99e-2157-4a68-a332-8e58722f2b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455443992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1455443992
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.124263739
Short name T790
Test name
Test status
Simulation time 2799992995 ps
CPU time 1.33 seconds
Started Jul 11 05:50:38 PM PDT 24
Finished Jul 11 05:50:41 PM PDT 24
Peak memory 201712 kb
Host smart-6164f60c-2128-4d6b-831f-889fdf0c723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124263739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.124263739
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4204427249
Short name T609
Test name
Test status
Simulation time 6027033429 ps
CPU time 13.73 seconds
Started Jul 11 05:50:31 PM PDT 24
Finished Jul 11 05:50:46 PM PDT 24
Peak memory 201720 kb
Host smart-b1e24afb-503e-47cd-95bc-d8c4ae5feed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204427249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4204427249
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3064947963
Short name T531
Test name
Test status
Simulation time 339580764 ps
CPU time 1 seconds
Started Jul 11 05:50:47 PM PDT 24
Finished Jul 11 05:50:50 PM PDT 24
Peak memory 201656 kb
Host smart-97d92e22-bf32-4318-b019-eb9b78e83478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064947963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3064947963
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1169077224
Short name T61
Test name
Test status
Simulation time 167301894160 ps
CPU time 311.97 seconds
Started Jul 11 05:50:44 PM PDT 24
Finished Jul 11 05:55:58 PM PDT 24
Peak memory 201152 kb
Host smart-5f89417a-6b65-4f1d-92bb-2eab90f3ba5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169077224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1169077224
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2915940289
Short name T278
Test name
Test status
Simulation time 335819391459 ps
CPU time 614.73 seconds
Started Jul 11 05:50:51 PM PDT 24
Finished Jul 11 06:01:07 PM PDT 24
Peak memory 201892 kb
Host smart-01e1ab49-d543-4c6f-9a9f-4da46a7807bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915940289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2915940289
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3129693594
Short name T728
Test name
Test status
Simulation time 160982704374 ps
CPU time 86 seconds
Started Jul 11 05:50:42 PM PDT 24
Finished Jul 11 05:52:09 PM PDT 24
Peak memory 201800 kb
Host smart-8d4890b9-9ecb-42cc-a96f-24fbb35c3389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129693594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3129693594
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2197458619
Short name T482
Test name
Test status
Simulation time 166952697613 ps
CPU time 375.68 seconds
Started Jul 11 05:50:42 PM PDT 24
Finished Jul 11 05:56:58 PM PDT 24
Peak memory 201780 kb
Host smart-3631df95-afdc-4987-b342-ff6a01905457
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197458619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2197458619
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3508164841
Short name T230
Test name
Test status
Simulation time 488905326534 ps
CPU time 279.49 seconds
Started Jul 11 05:50:41 PM PDT 24
Finished Jul 11 05:55:21 PM PDT 24
Peak memory 201964 kb
Host smart-8720f3c4-b47a-4945-9f1a-1efde8659700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508164841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3508164841
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1459307313
Short name T668
Test name
Test status
Simulation time 332179296096 ps
CPU time 321.9 seconds
Started Jul 11 05:50:39 PM PDT 24
Finished Jul 11 05:56:02 PM PDT 24
Peak memory 201828 kb
Host smart-cadbc334-89b5-41e0-8f71-4fdf317a1787
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459307313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1459307313
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1705992848
Short name T349
Test name
Test status
Simulation time 401788557260 ps
CPU time 810.72 seconds
Started Jul 11 05:50:44 PM PDT 24
Finished Jul 11 06:04:16 PM PDT 24
Peak memory 201080 kb
Host smart-478043f8-3da2-4a9f-9ebe-ad3d34375eb9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705992848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1705992848
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.95036769
Short name T774
Test name
Test status
Simulation time 135755063107 ps
CPU time 422.46 seconds
Started Jul 11 05:50:47 PM PDT 24
Finished Jul 11 05:57:51 PM PDT 24
Peak memory 202176 kb
Host smart-c91ce8cb-d247-40bc-8f8f-18cc337b0ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95036769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.95036769
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2982121416
Short name T480
Test name
Test status
Simulation time 21879961959 ps
CPU time 11.03 seconds
Started Jul 11 05:50:42 PM PDT 24
Finished Jul 11 05:50:54 PM PDT 24
Peak memory 201728 kb
Host smart-12a3d99e-7dc7-4064-9683-a9f87421ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982121416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2982121416
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2839632317
Short name T793
Test name
Test status
Simulation time 4623828157 ps
CPU time 10.71 seconds
Started Jul 11 05:50:44 PM PDT 24
Finished Jul 11 05:50:56 PM PDT 24
Peak memory 201700 kb
Host smart-aa526501-5aee-473f-89e7-788591a6d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839632317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2839632317
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1544944029
Short name T515
Test name
Test status
Simulation time 6118747231 ps
CPU time 15.45 seconds
Started Jul 11 05:50:39 PM PDT 24
Finished Jul 11 05:50:55 PM PDT 24
Peak memory 201636 kb
Host smart-5688d367-c843-4ff9-ab3c-63f9b7a56f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544944029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1544944029
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1718505837
Short name T600
Test name
Test status
Simulation time 96196679467 ps
CPU time 105.16 seconds
Started Jul 11 05:50:43 PM PDT 24
Finished Jul 11 05:52:29 PM PDT 24
Peak memory 210616 kb
Host smart-551e3603-b839-400e-8755-714a4a2009c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718505837 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1718505837
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2863752569
Short name T604
Test name
Test status
Simulation time 514502925 ps
CPU time 1.8 seconds
Started Jul 11 05:50:52 PM PDT 24
Finished Jul 11 05:50:55 PM PDT 24
Peak memory 201640 kb
Host smart-d3b130b3-2186-46ae-99df-6c62113dda20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863752569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2863752569
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4024952335
Short name T579
Test name
Test status
Simulation time 488052302907 ps
CPU time 221.21 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:54:28 PM PDT 24
Peak memory 201256 kb
Host smart-e854a122-7a9b-4400-bcf7-3cf65f4742a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024952335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4024952335
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3981703899
Short name T367
Test name
Test status
Simulation time 330984082025 ps
CPU time 226.66 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:54:34 PM PDT 24
Peak memory 201232 kb
Host smart-9e890199-854d-4691-9e00-78ce95947362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981703899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3981703899
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.736173032
Short name T549
Test name
Test status
Simulation time 483959596422 ps
CPU time 471.08 seconds
Started Jul 11 05:50:43 PM PDT 24
Finished Jul 11 05:58:36 PM PDT 24
Peak memory 201764 kb
Host smart-962b2d05-47f3-4b80-a1d7-92cfc7fefc7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=736173032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.736173032
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3605831652
Short name T217
Test name
Test status
Simulation time 321456315361 ps
CPU time 39.82 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:51:28 PM PDT 24
Peak memory 201792 kb
Host smart-d99c05eb-eb62-40da-b2d3-1793efcaa944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605831652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3605831652
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.4135989105
Short name T174
Test name
Test status
Simulation time 168860555408 ps
CPU time 178.2 seconds
Started Jul 11 05:50:47 PM PDT 24
Finished Jul 11 05:53:47 PM PDT 24
Peak memory 201756 kb
Host smart-6c2ae4bc-9833-4384-af89-89492f29ec09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135989105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.4135989105
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2834003194
Short name T311
Test name
Test status
Simulation time 278579900642 ps
CPU time 173.29 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:53:41 PM PDT 24
Peak memory 201516 kb
Host smart-e4688caf-360c-417c-883a-04164bf402c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834003194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2834003194
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2111518434
Short name T207
Test name
Test status
Simulation time 407572681421 ps
CPU time 287.81 seconds
Started Jul 11 05:50:43 PM PDT 24
Finished Jul 11 05:55:32 PM PDT 24
Peak memory 201876 kb
Host smart-ee37f9fb-fa11-4e13-982b-f79928d703f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111518434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2111518434
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.472068264
Short name T409
Test name
Test status
Simulation time 90257926105 ps
CPU time 455.19 seconds
Started Jul 11 05:50:49 PM PDT 24
Finished Jul 11 05:58:26 PM PDT 24
Peak memory 202108 kb
Host smart-de509113-5e28-40ad-8ec9-682243424d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472068264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.472068264
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.4075914692
Short name T469
Test name
Test status
Simulation time 41096273794 ps
CPU time 45.53 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:51:33 PM PDT 24
Peak memory 201708 kb
Host smart-6881e0b9-15f3-4f60-9135-7b3db85f8252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075914692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.4075914692
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3899486099
Short name T432
Test name
Test status
Simulation time 4784570182 ps
CPU time 6.1 seconds
Started Jul 11 05:50:46 PM PDT 24
Finished Jul 11 05:50:54 PM PDT 24
Peak memory 201724 kb
Host smart-01b8e1f1-b325-40bf-b0c1-923263e9b8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899486099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3899486099
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1736207493
Short name T388
Test name
Test status
Simulation time 5725289777 ps
CPU time 4.55 seconds
Started Jul 11 05:50:44 PM PDT 24
Finished Jul 11 05:50:50 PM PDT 24
Peak memory 201716 kb
Host smart-429da36f-a430-4229-ae6f-78fcf098a1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736207493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1736207493
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1036762194
Short name T15
Test name
Test status
Simulation time 246944813399 ps
CPU time 405.93 seconds
Started Jul 11 05:50:55 PM PDT 24
Finished Jul 11 05:57:43 PM PDT 24
Peak memory 217940 kb
Host smart-cb3c549b-7d05-4b0b-80a9-6afd34155756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036762194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1036762194
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.238466526
Short name T587
Test name
Test status
Simulation time 337747997 ps
CPU time 1.35 seconds
Started Jul 11 05:50:56 PM PDT 24
Finished Jul 11 05:50:59 PM PDT 24
Peak memory 201632 kb
Host smart-a5267f26-cc8a-41d3-b6df-87573809f47d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238466526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.238466526
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.162620534
Short name T344
Test name
Test status
Simulation time 334943906651 ps
CPU time 382.64 seconds
Started Jul 11 05:50:57 PM PDT 24
Finished Jul 11 05:57:21 PM PDT 24
Peak memory 201896 kb
Host smart-ca647ef8-104d-4efe-9dd2-13cb8a236c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162620534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.162620534
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2063719610
Short name T535
Test name
Test status
Simulation time 163747279246 ps
CPU time 389.54 seconds
Started Jul 11 05:50:53 PM PDT 24
Finished Jul 11 05:57:24 PM PDT 24
Peak memory 201880 kb
Host smart-d0c778ea-a15b-4636-9115-d757102531cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063719610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2063719610
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1640656708
Short name T461
Test name
Test status
Simulation time 328337199765 ps
CPU time 178.19 seconds
Started Jul 11 05:50:56 PM PDT 24
Finished Jul 11 05:53:55 PM PDT 24
Peak memory 201836 kb
Host smart-a81871d7-bdad-4aba-be3a-dc5294559902
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640656708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1640656708
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3929582356
Short name T201
Test name
Test status
Simulation time 325741319794 ps
CPU time 189.89 seconds
Started Jul 11 05:50:51 PM PDT 24
Finished Jul 11 05:54:02 PM PDT 24
Peak memory 201988 kb
Host smart-89b0b36d-8f1e-450a-9922-759afc9830ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929582356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3929582356
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2530513467
Short name T650
Test name
Test status
Simulation time 170133263252 ps
CPU time 97.49 seconds
Started Jul 11 05:50:56 PM PDT 24
Finished Jul 11 05:52:34 PM PDT 24
Peak memory 201832 kb
Host smart-fd73d1e1-a4df-454f-9907-3590f21e1df7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530513467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2530513467
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3056474999
Short name T49
Test name
Test status
Simulation time 535986475189 ps
CPU time 299.42 seconds
Started Jul 11 05:50:48 PM PDT 24
Finished Jul 11 05:55:49 PM PDT 24
Peak memory 201980 kb
Host smart-41db39f3-d6d3-4509-9120-4e8d3740a4b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056474999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3056474999
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1114874483
Short name T462
Test name
Test status
Simulation time 197232904301 ps
CPU time 468.97 seconds
Started Jul 11 05:50:50 PM PDT 24
Finished Jul 11 05:58:41 PM PDT 24
Peak memory 201816 kb
Host smart-ca958806-4f73-4a0d-9168-6af417d7f5eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114874483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1114874483
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.941914555
Short name T377
Test name
Test status
Simulation time 85064680007 ps
CPU time 305.25 seconds
Started Jul 11 05:50:51 PM PDT 24
Finished Jul 11 05:55:58 PM PDT 24
Peak memory 202340 kb
Host smart-8b814d73-33d6-4144-ae9a-05a0475ffb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941914555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.941914555
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1825763628
Short name T708
Test name
Test status
Simulation time 28877552081 ps
CPU time 49.94 seconds
Started Jul 11 05:50:52 PM PDT 24
Finished Jul 11 05:51:43 PM PDT 24
Peak memory 201628 kb
Host smart-748b6f9f-b886-4807-a718-fa9aad8f9388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825763628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1825763628
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1114305712
Short name T405
Test name
Test status
Simulation time 3418112377 ps
CPU time 8.1 seconds
Started Jul 11 05:50:54 PM PDT 24
Finished Jul 11 05:51:03 PM PDT 24
Peak memory 201728 kb
Host smart-f5f917b6-6861-426c-ae47-25d0067d3b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114305712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1114305712
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1583382317
Short name T633
Test name
Test status
Simulation time 5713317332 ps
CPU time 2.16 seconds
Started Jul 11 05:50:52 PM PDT 24
Finished Jul 11 05:50:55 PM PDT 24
Peak memory 201704 kb
Host smart-e4d468b2-d39c-4dc6-923e-53e7f48d3c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583382317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1583382317
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3909842587
Short name T296
Test name
Test status
Simulation time 203095582496 ps
CPU time 396.24 seconds
Started Jul 11 05:50:51 PM PDT 24
Finished Jul 11 05:57:28 PM PDT 24
Peak memory 201892 kb
Host smart-1cc5b8d9-243e-4083-b39f-367d918e3e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909842587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3909842587
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3784689250
Short name T557
Test name
Test status
Simulation time 332398493498 ps
CPU time 304.34 seconds
Started Jul 11 05:50:54 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 210544 kb
Host smart-a2f1dfe4-3a11-430d-addc-828b8c89c0c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784689250 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3784689250
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3355808682
Short name T628
Test name
Test status
Simulation time 375254928 ps
CPU time 1.45 seconds
Started Jul 11 05:51:00 PM PDT 24
Finished Jul 11 05:51:03 PM PDT 24
Peak memory 201656 kb
Host smart-8ab88e66-8bb8-4d1b-89b5-dda716e3d48f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355808682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3355808682
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.590488851
Short name T724
Test name
Test status
Simulation time 371247418410 ps
CPU time 426.3 seconds
Started Jul 11 05:51:00 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 201908 kb
Host smart-513ae41b-4c43-4131-962d-fcd64e7914ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590488851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.590488851
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1205375291
Short name T416
Test name
Test status
Simulation time 329366966003 ps
CPU time 657.46 seconds
Started Jul 11 05:51:00 PM PDT 24
Finished Jul 11 06:01:58 PM PDT 24
Peak memory 201812 kb
Host smart-6598a3b5-7bd6-4422-96d0-72c79e04509b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205375291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1205375291
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2442334057
Short name T158
Test name
Test status
Simulation time 495078901740 ps
CPU time 716.64 seconds
Started Jul 11 05:50:54 PM PDT 24
Finished Jul 11 06:02:52 PM PDT 24
Peak memory 201980 kb
Host smart-3fd8b84c-7404-44bc-8df3-ef87fdd587b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442334057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2442334057
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3475069118
Short name T153
Test name
Test status
Simulation time 487494485259 ps
CPU time 1110.66 seconds
Started Jul 11 05:50:55 PM PDT 24
Finished Jul 11 06:09:27 PM PDT 24
Peak memory 201836 kb
Host smart-4eded049-0ebe-4835-88e6-dcc26292bdbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475069118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3475069118
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3957686557
Short name T687
Test name
Test status
Simulation time 184375268901 ps
CPU time 404.56 seconds
Started Jul 11 05:50:56 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 201904 kb
Host smart-9f48504f-0bec-4892-b908-ed109f0948c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957686557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3957686557
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2137113578
Short name T638
Test name
Test status
Simulation time 203723809252 ps
CPU time 467.43 seconds
Started Jul 11 05:51:03 PM PDT 24
Finished Jul 11 05:58:52 PM PDT 24
Peak memory 201856 kb
Host smart-4f083654-f979-42a0-9caa-aea72e6c8423
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137113578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2137113578
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3796570446
Short name T379
Test name
Test status
Simulation time 117253544296 ps
CPU time 442.63 seconds
Started Jul 11 05:51:03 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 202212 kb
Host smart-fb5a131d-6995-49dd-8db1-73044af6151d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796570446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3796570446
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1615795057
Short name T634
Test name
Test status
Simulation time 43321612541 ps
CPU time 21.99 seconds
Started Jul 11 05:51:04 PM PDT 24
Finished Jul 11 05:51:27 PM PDT 24
Peak memory 201720 kb
Host smart-bb840db5-0553-429d-8ec8-2f391626e635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615795057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1615795057
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4146905442
Short name T566
Test name
Test status
Simulation time 4418970866 ps
CPU time 2.89 seconds
Started Jul 11 05:51:01 PM PDT 24
Finished Jul 11 05:51:06 PM PDT 24
Peak memory 201688 kb
Host smart-4a5b7c82-5cde-454a-bcf5-f456b36acd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146905442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4146905442
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.601144179
Short name T603
Test name
Test status
Simulation time 5781055006 ps
CPU time 4.23 seconds
Started Jul 11 05:50:59 PM PDT 24
Finished Jul 11 05:51:05 PM PDT 24
Peak memory 201692 kb
Host smart-50661b9c-d155-492f-aa11-5492537c5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601144179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.601144179
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1260015374
Short name T54
Test name
Test status
Simulation time 73842568231 ps
CPU time 294.32 seconds
Started Jul 11 05:51:04 PM PDT 24
Finished Jul 11 05:56:00 PM PDT 24
Peak memory 210404 kb
Host smart-80ba8ce3-3817-440f-9030-662979dc4562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260015374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1260015374
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3561111911
Short name T730
Test name
Test status
Simulation time 265254205255 ps
CPU time 44.92 seconds
Started Jul 11 05:51:03 PM PDT 24
Finished Jul 11 05:51:49 PM PDT 24
Peak memory 210228 kb
Host smart-bbb56f2d-6364-4038-bc41-dcbe186b1f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561111911 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3561111911
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2948060101
Short name T31
Test name
Test status
Simulation time 398578240 ps
CPU time 0.88 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:48:46 PM PDT 24
Peak memory 201652 kb
Host smart-6f14b7da-3f5e-4b6f-801b-186f22fd0ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948060101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2948060101
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3749785688
Short name T752
Test name
Test status
Simulation time 167138244147 ps
CPU time 93.59 seconds
Started Jul 11 05:48:33 PM PDT 24
Finished Jul 11 05:50:08 PM PDT 24
Peak memory 201972 kb
Host smart-61bcbe45-5d2c-4d01-b6c5-deec6ce013c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749785688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3749785688
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.642778702
Short name T523
Test name
Test status
Simulation time 512871585200 ps
CPU time 230.69 seconds
Started Jul 11 05:48:26 PM PDT 24
Finished Jul 11 05:52:21 PM PDT 24
Peak memory 201920 kb
Host smart-92d0b379-c512-4978-aff7-1e6b602dfefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642778702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.642778702
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1699634529
Short name T267
Test name
Test status
Simulation time 489131213758 ps
CPU time 1191.84 seconds
Started Jul 11 05:48:19 PM PDT 24
Finished Jul 11 06:08:17 PM PDT 24
Peak memory 201892 kb
Host smart-8c1d958f-e07e-44b6-b200-dcb0bd6cefdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699634529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1699634529
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.58206565
Short name T689
Test name
Test status
Simulation time 328193312276 ps
CPU time 98.98 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 05:50:09 PM PDT 24
Peak memory 201880 kb
Host smart-d316b86a-2cb9-4391-968b-0342876db388
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=58206565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_
fixed.58206565
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.251211532
Short name T779
Test name
Test status
Simulation time 165239942627 ps
CPU time 21.23 seconds
Started Jul 11 05:48:54 PM PDT 24
Finished Jul 11 05:49:21 PM PDT 24
Peak memory 201920 kb
Host smart-bb6dbe9e-451d-40da-ae44-2fb8816d76cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251211532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.251211532
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.4077925128
Short name T163
Test name
Test status
Simulation time 335467730426 ps
CPU time 189.23 seconds
Started Jul 11 05:49:11 PM PDT 24
Finished Jul 11 05:52:26 PM PDT 24
Peak memory 201920 kb
Host smart-7753057b-5815-401a-bc1b-878629860fd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077925128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.4077925128
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2806171172
Short name T325
Test name
Test status
Simulation time 564704772394 ps
CPU time 1270.02 seconds
Started Jul 11 05:48:23 PM PDT 24
Finished Jul 11 06:09:38 PM PDT 24
Peak memory 201896 kb
Host smart-2c91e41d-2f1b-4ebe-826d-22c5b617c651
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806171172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2806171172
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4220836110
Short name T424
Test name
Test status
Simulation time 196639714079 ps
CPU time 449.78 seconds
Started Jul 11 05:49:11 PM PDT 24
Finished Jul 11 05:56:46 PM PDT 24
Peak memory 201864 kb
Host smart-263c9617-d11d-4071-a852-451e04ccba90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220836110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4220836110
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2587665628
Short name T457
Test name
Test status
Simulation time 63925073536 ps
CPU time 281.79 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 05:53:12 PM PDT 24
Peak memory 202080 kb
Host smart-7c267675-c33f-446d-9d33-cbb31ce47af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587665628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2587665628
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1003838707
Short name T536
Test name
Test status
Simulation time 24959366849 ps
CPU time 52.54 seconds
Started Jul 11 05:48:33 PM PDT 24
Finished Jul 11 05:49:27 PM PDT 24
Peak memory 201612 kb
Host smart-10586131-cb86-438c-bd09-93266f52d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003838707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1003838707
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3773569013
Short name T619
Test name
Test status
Simulation time 2711173217 ps
CPU time 6.03 seconds
Started Jul 11 05:48:24 PM PDT 24
Finished Jul 11 05:48:35 PM PDT 24
Peak memory 201712 kb
Host smart-274f0121-342f-463c-a124-620577e6d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773569013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3773569013
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3359003310
Short name T85
Test name
Test status
Simulation time 8160839535 ps
CPU time 18.47 seconds
Started Jul 11 05:48:25 PM PDT 24
Finished Jul 11 05:48:48 PM PDT 24
Peak memory 218480 kb
Host smart-fb9211a1-d1c7-4cb5-acad-3648ebf03004
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359003310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3359003310
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1452459473
Short name T625
Test name
Test status
Simulation time 5770450437 ps
CPU time 14.31 seconds
Started Jul 11 05:48:23 PM PDT 24
Finished Jul 11 05:48:42 PM PDT 24
Peak memory 201708 kb
Host smart-0dfeb0fb-a7c9-4f3f-85d9-de973f73d2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452459473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1452459473
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4137044555
Short name T21
Test name
Test status
Simulation time 540618126964 ps
CPU time 695.67 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 06:00:06 PM PDT 24
Peak memory 210552 kb
Host smart-0830038a-7694-44b2-9e74-aee022aa735f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137044555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.4137044555
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.4072241637
Short name T389
Test name
Test status
Simulation time 483839054 ps
CPU time 0.8 seconds
Started Jul 11 05:51:09 PM PDT 24
Finished Jul 11 05:51:11 PM PDT 24
Peak memory 201572 kb
Host smart-e5886d90-814d-4c28-b7fa-9bcd132ac7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072241637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.4072241637
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3989238554
Short name T182
Test name
Test status
Simulation time 163513290204 ps
CPU time 92.5 seconds
Started Jul 11 05:51:05 PM PDT 24
Finished Jul 11 05:52:39 PM PDT 24
Peak memory 201928 kb
Host smart-ba4241e9-3580-49fb-89c5-897b4f0aef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989238554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3989238554
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3297732918
Short name T447
Test name
Test status
Simulation time 325712910530 ps
CPU time 389.71 seconds
Started Jul 11 05:51:06 PM PDT 24
Finished Jul 11 05:57:37 PM PDT 24
Peak memory 201880 kb
Host smart-82fd4c5a-a5cb-4cf8-8dbb-a7b7848c4bd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297732918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3297732918
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.592777795
Short name T291
Test name
Test status
Simulation time 477967631545 ps
CPU time 1023.09 seconds
Started Jul 11 05:51:08 PM PDT 24
Finished Jul 11 06:08:12 PM PDT 24
Peak memory 201920 kb
Host smart-1cc70a00-4550-4c6b-a1e7-1ca1e7bf04a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592777795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.592777795
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3876699521
Short name T521
Test name
Test status
Simulation time 163221381258 ps
CPU time 91.44 seconds
Started Jul 11 05:50:59 PM PDT 24
Finished Jul 11 05:52:32 PM PDT 24
Peak memory 201864 kb
Host smart-62dcc4cd-1cf2-4022-bd17-dc7dcfc04021
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876699521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3876699521
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3104053681
Short name T357
Test name
Test status
Simulation time 550064468525 ps
CPU time 1259.75 seconds
Started Jul 11 05:51:01 PM PDT 24
Finished Jul 11 06:12:02 PM PDT 24
Peak memory 201968 kb
Host smart-8025cae8-8467-42f3-969f-945397485f76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104053681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3104053681
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2701411136
Short name T465
Test name
Test status
Simulation time 401337058332 ps
CPU time 955.64 seconds
Started Jul 11 05:51:10 PM PDT 24
Finished Jul 11 06:07:08 PM PDT 24
Peak memory 201944 kb
Host smart-11b62385-7e3b-4cbc-82fb-3795b1484b8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701411136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2701411136
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4221767340
Short name T721
Test name
Test status
Simulation time 117246950645 ps
CPU time 371.86 seconds
Started Jul 11 05:51:07 PM PDT 24
Finished Jul 11 05:57:20 PM PDT 24
Peak memory 202300 kb
Host smart-ffa212cf-2ae4-44e8-aa5f-a32c39354f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221767340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4221767340
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3563567800
Short name T651
Test name
Test status
Simulation time 34200733944 ps
CPU time 20.94 seconds
Started Jul 11 05:51:14 PM PDT 24
Finished Jul 11 05:51:37 PM PDT 24
Peak memory 201700 kb
Host smart-8c9f07c3-ebb6-4c34-817f-3f3a39665a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563567800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3563567800
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1809932621
Short name T165
Test name
Test status
Simulation time 3649434743 ps
CPU time 8.49 seconds
Started Jul 11 05:51:11 PM PDT 24
Finished Jul 11 05:51:21 PM PDT 24
Peak memory 201612 kb
Host smart-b71a3049-c151-464f-bbd0-a8fc2bed2077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809932621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1809932621
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4088876165
Short name T430
Test name
Test status
Simulation time 5619346892 ps
CPU time 7.76 seconds
Started Jul 11 05:51:03 PM PDT 24
Finished Jul 11 05:51:12 PM PDT 24
Peak memory 201704 kb
Host smart-bc950f81-7d6f-478b-9d45-33d0628527a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088876165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4088876165
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1575116856
Short name T276
Test name
Test status
Simulation time 352554467608 ps
CPU time 769.68 seconds
Started Jul 11 05:51:07 PM PDT 24
Finished Jul 11 06:03:58 PM PDT 24
Peak memory 201892 kb
Host smart-938ba293-2706-42e8-93cd-6fdc0b4aec33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575116856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1575116856
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1835378387
Short name T694
Test name
Test status
Simulation time 470169022 ps
CPU time 1.72 seconds
Started Jul 11 05:51:21 PM PDT 24
Finished Jul 11 05:51:24 PM PDT 24
Peak memory 201656 kb
Host smart-45830024-b526-442c-9e14-ed583a9b909f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835378387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1835378387
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2411931054
Short name T160
Test name
Test status
Simulation time 356237646566 ps
CPU time 213.85 seconds
Started Jul 11 05:51:16 PM PDT 24
Finished Jul 11 05:54:51 PM PDT 24
Peak memory 201884 kb
Host smart-dbd4c6bc-7fb8-4ade-b923-3370c5ce579b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411931054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2411931054
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3304289326
Short name T214
Test name
Test status
Simulation time 496925317232 ps
CPU time 101.37 seconds
Started Jul 11 05:51:14 PM PDT 24
Finished Jul 11 05:52:57 PM PDT 24
Peak memory 201916 kb
Host smart-78a39cab-2272-4d9d-a124-1b087200bc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304289326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3304289326
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3667653915
Short name T269
Test name
Test status
Simulation time 163602078049 ps
CPU time 388.81 seconds
Started Jul 11 05:51:14 PM PDT 24
Finished Jul 11 05:57:44 PM PDT 24
Peak memory 201924 kb
Host smart-830d0295-bc31-42e6-82a3-28a13618f8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667653915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3667653915
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1888776933
Short name T399
Test name
Test status
Simulation time 328552953100 ps
CPU time 188.97 seconds
Started Jul 11 05:51:17 PM PDT 24
Finished Jul 11 05:54:27 PM PDT 24
Peak memory 201892 kb
Host smart-4c092850-235b-4a95-bdf7-ba112d8f7e51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888776933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1888776933
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3899355251
Short name T484
Test name
Test status
Simulation time 162266544584 ps
CPU time 74.42 seconds
Started Jul 11 05:51:06 PM PDT 24
Finished Jul 11 05:52:22 PM PDT 24
Peak memory 201924 kb
Host smart-daee67c4-9087-4c5b-b750-65d36f974d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899355251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3899355251
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3110060270
Short name T586
Test name
Test status
Simulation time 168296109983 ps
CPU time 86.12 seconds
Started Jul 11 05:51:06 PM PDT 24
Finished Jul 11 05:52:34 PM PDT 24
Peak memory 201860 kb
Host smart-83c9b44b-b36a-48aa-882f-bf5fbc534a65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110060270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3110060270
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3928689386
Short name T196
Test name
Test status
Simulation time 367427824427 ps
CPU time 87.51 seconds
Started Jul 11 05:51:16 PM PDT 24
Finished Jul 11 05:52:44 PM PDT 24
Peak memory 201876 kb
Host smart-107569a6-251e-46b7-95ec-8851338369da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928689386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3928689386
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3319699791
Short name T648
Test name
Test status
Simulation time 588057159873 ps
CPU time 1413.64 seconds
Started Jul 11 05:51:18 PM PDT 24
Finished Jul 11 06:14:52 PM PDT 24
Peak memory 201900 kb
Host smart-7c4a5dad-dc99-4c62-be6e-63fc21c40359
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319699791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3319699791
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2412847165
Short name T7
Test name
Test status
Simulation time 89181674263 ps
CPU time 321.58 seconds
Started Jul 11 05:51:23 PM PDT 24
Finished Jul 11 05:56:46 PM PDT 24
Peak memory 202240 kb
Host smart-8eba5e2d-3430-4d99-82c6-a4e5d5b8230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412847165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2412847165
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.179081959
Short name T705
Test name
Test status
Simulation time 34721273853 ps
CPU time 80.27 seconds
Started Jul 11 05:51:17 PM PDT 24
Finished Jul 11 05:52:38 PM PDT 24
Peak memory 201700 kb
Host smart-a1df0971-d572-427e-8a88-f1a5eff0f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179081959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.179081959
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2001943152
Short name T431
Test name
Test status
Simulation time 3484401249 ps
CPU time 4.64 seconds
Started Jul 11 05:51:15 PM PDT 24
Finished Jul 11 05:51:21 PM PDT 24
Peak memory 201704 kb
Host smart-afffbc4b-14c9-416e-9de0-5f973cff1352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001943152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2001943152
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3742664658
Short name T739
Test name
Test status
Simulation time 5633517556 ps
CPU time 3.12 seconds
Started Jul 11 05:51:07 PM PDT 24
Finished Jul 11 05:51:11 PM PDT 24
Peak memory 201692 kb
Host smart-44d29130-0048-47d4-90cb-b50c072af0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742664658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3742664658
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1381157663
Short name T34
Test name
Test status
Simulation time 469140504839 ps
CPU time 881.73 seconds
Started Jul 11 05:51:21 PM PDT 24
Finished Jul 11 06:06:04 PM PDT 24
Peak memory 210340 kb
Host smart-1c58f679-c4bc-4ffb-a34e-2af74dbd29e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381157663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1381157663
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2123895652
Short name T791
Test name
Test status
Simulation time 93671946722 ps
CPU time 155.06 seconds
Started Jul 11 05:51:22 PM PDT 24
Finished Jul 11 05:53:59 PM PDT 24
Peak memory 211560 kb
Host smart-33d3bb52-37a9-4adf-b51f-fb1c6d14e6f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123895652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2123895652
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2917514696
Short name T190
Test name
Test status
Simulation time 309595166 ps
CPU time 1.22 seconds
Started Jul 11 05:51:26 PM PDT 24
Finished Jul 11 05:51:29 PM PDT 24
Peak memory 201656 kb
Host smart-275daaec-f4b8-459d-8936-af761f34b37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917514696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2917514696
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3829325003
Short name T345
Test name
Test status
Simulation time 158969824791 ps
CPU time 173.71 seconds
Started Jul 11 05:51:23 PM PDT 24
Finished Jul 11 05:54:18 PM PDT 24
Peak memory 201916 kb
Host smart-1ed9f3fb-c399-4a0a-a7dc-96fe98051be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829325003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3829325003
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3810520890
Short name T737
Test name
Test status
Simulation time 326463318504 ps
CPU time 108.59 seconds
Started Jul 11 05:51:28 PM PDT 24
Finished Jul 11 05:53:19 PM PDT 24
Peak memory 201884 kb
Host smart-3ada8a96-a385-4ba6-945e-32f79d2f72fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810520890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3810520890
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2664210509
Short name T588
Test name
Test status
Simulation time 487771111996 ps
CPU time 541.58 seconds
Started Jul 11 05:51:25 PM PDT 24
Finished Jul 11 06:00:28 PM PDT 24
Peak memory 201756 kb
Host smart-1e329841-fdfd-4920-8b1e-4b565fc0952f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664210509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2664210509
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2001135052
Short name T340
Test name
Test status
Simulation time 331544699981 ps
CPU time 113.22 seconds
Started Jul 11 05:51:24 PM PDT 24
Finished Jul 11 05:53:19 PM PDT 24
Peak memory 201936 kb
Host smart-18712a24-daa5-419d-8546-68ecd062b670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001135052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2001135052
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4119673893
Short name T738
Test name
Test status
Simulation time 500073422606 ps
CPU time 512.48 seconds
Started Jul 11 05:51:21 PM PDT 24
Finished Jul 11 05:59:55 PM PDT 24
Peak memory 201888 kb
Host smart-e40473a3-2f50-49f6-bf4e-2c15f40b6e29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119673893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4119673893
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2251032069
Short name T347
Test name
Test status
Simulation time 536980984969 ps
CPU time 1113.86 seconds
Started Jul 11 05:51:24 PM PDT 24
Finished Jul 11 06:09:59 PM PDT 24
Peak memory 201960 kb
Host smart-cd4b7584-d8a6-43fb-aae6-b956ce1a0607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251032069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2251032069
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1767079382
Short name T712
Test name
Test status
Simulation time 611620130624 ps
CPU time 371.37 seconds
Started Jul 11 05:51:28 PM PDT 24
Finished Jul 11 05:57:42 PM PDT 24
Peak memory 201840 kb
Host smart-6711bc24-81c5-491c-8b65-5fd8dd7ac04f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767079382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1767079382
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2027829678
Short name T471
Test name
Test status
Simulation time 122522602949 ps
CPU time 395 seconds
Started Jul 11 05:51:25 PM PDT 24
Finished Jul 11 05:58:02 PM PDT 24
Peak memory 202288 kb
Host smart-9d12ded8-9c30-4563-ae7d-d72029f90f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027829678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2027829678
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.557266107
Short name T596
Test name
Test status
Simulation time 43443662766 ps
CPU time 23.38 seconds
Started Jul 11 05:51:30 PM PDT 24
Finished Jul 11 05:51:55 PM PDT 24
Peak memory 201640 kb
Host smart-a03fce2c-c363-4223-b6a1-d88baf68daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557266107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.557266107
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1179758218
Short name T690
Test name
Test status
Simulation time 4521145563 ps
CPU time 2.03 seconds
Started Jul 11 05:51:29 PM PDT 24
Finished Jul 11 05:51:33 PM PDT 24
Peak memory 201644 kb
Host smart-6cbfb1ef-006d-42f4-86d2-97d1378b710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179758218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1179758218
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.4222261626
Short name T455
Test name
Test status
Simulation time 6051949540 ps
CPU time 14.12 seconds
Started Jul 11 05:51:21 PM PDT 24
Finished Jul 11 05:51:36 PM PDT 24
Peak memory 201740 kb
Host smart-dd173544-3f9b-43c6-8730-36dc2e53c922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222261626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4222261626
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3984502713
Short name T627
Test name
Test status
Simulation time 653264787603 ps
CPU time 1146.5 seconds
Started Jul 11 05:51:27 PM PDT 24
Finished Jul 11 06:10:35 PM PDT 24
Peak memory 210368 kb
Host smart-4ca9bb76-1311-41b5-bb6f-7b04d978b1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984502713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3984502713
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.4025427050
Short name T20
Test name
Test status
Simulation time 274015122472 ps
CPU time 230.39 seconds
Started Jul 11 05:51:30 PM PDT 24
Finished Jul 11 05:55:22 PM PDT 24
Peak memory 210292 kb
Host smart-21834296-58a7-4376-ae5e-b63c58f030e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025427050 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.4025427050
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.252074785
Short name T433
Test name
Test status
Simulation time 515367344 ps
CPU time 1.63 seconds
Started Jul 11 05:51:37 PM PDT 24
Finished Jul 11 05:51:40 PM PDT 24
Peak memory 201668 kb
Host smart-b4e26dbc-82d6-4347-a75e-08aae5fc6026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252074785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.252074785
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3684896786
Short name T187
Test name
Test status
Simulation time 512977745759 ps
CPU time 180.87 seconds
Started Jul 11 05:51:32 PM PDT 24
Finished Jul 11 05:54:34 PM PDT 24
Peak memory 201908 kb
Host smart-f6043b03-c01d-4af8-88f9-5e59ea97f4ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684896786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3684896786
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.223348741
Short name T195
Test name
Test status
Simulation time 492804416730 ps
CPU time 98.04 seconds
Started Jul 11 05:51:37 PM PDT 24
Finished Jul 11 05:53:16 PM PDT 24
Peak memory 201912 kb
Host smart-3a7c1df8-e27b-4b39-ac6e-010ef4348c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223348741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.223348741
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1953376977
Short name T489
Test name
Test status
Simulation time 485914692967 ps
CPU time 1113.31 seconds
Started Jul 11 05:51:38 PM PDT 24
Finished Jul 11 06:10:13 PM PDT 24
Peak memory 201868 kb
Host smart-e757a473-38d5-494b-9e9c-a2ae7c8e8faa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953376977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1953376977
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2856703644
Short name T414
Test name
Test status
Simulation time 327320198698 ps
CPU time 93.29 seconds
Started Jul 11 05:51:29 PM PDT 24
Finished Jul 11 05:53:04 PM PDT 24
Peak memory 201908 kb
Host smart-a19888f1-ba00-467f-90f8-d69698bb977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856703644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2856703644
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1824303284
Short name T602
Test name
Test status
Simulation time 327725115897 ps
CPU time 377.43 seconds
Started Jul 11 05:51:30 PM PDT 24
Finished Jul 11 05:57:49 PM PDT 24
Peak memory 201888 kb
Host smart-fa00ee33-359b-4089-b207-f9d15b8be0d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824303284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1824303284
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3699228598
Short name T449
Test name
Test status
Simulation time 210118163618 ps
CPU time 115.39 seconds
Started Jul 11 05:51:38 PM PDT 24
Finished Jul 11 05:53:35 PM PDT 24
Peak memory 201888 kb
Host smart-8c406eba-704d-4e6b-8bd9-523926f02525
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699228598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3699228598
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1587857037
Short name T245
Test name
Test status
Simulation time 113468491054 ps
CPU time 580.9 seconds
Started Jul 11 05:51:31 PM PDT 24
Finished Jul 11 06:01:13 PM PDT 24
Peak memory 202280 kb
Host smart-9471079c-fbe1-43b1-aca5-e97e925b81d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587857037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1587857037
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2886884766
Short name T763
Test name
Test status
Simulation time 39810347341 ps
CPU time 10.1 seconds
Started Jul 11 05:51:28 PM PDT 24
Finished Jul 11 05:51:40 PM PDT 24
Peak memory 201692 kb
Host smart-a8e82888-2196-4bc4-8ed0-6baa395f7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886884766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2886884766
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.88523731
Short name T400
Test name
Test status
Simulation time 3334159052 ps
CPU time 8.38 seconds
Started Jul 11 05:51:31 PM PDT 24
Finished Jul 11 05:51:40 PM PDT 24
Peak memory 201708 kb
Host smart-86d599bf-4d83-4790-93f3-5997775ef65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88523731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.88523731
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.4046783179
Short name T5
Test name
Test status
Simulation time 5628336215 ps
CPU time 14.14 seconds
Started Jul 11 05:51:28 PM PDT 24
Finished Jul 11 05:51:44 PM PDT 24
Peak memory 201660 kb
Host smart-ff011a7d-358c-45a2-9b0e-8c0b53f743b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046783179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.4046783179
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2306202066
Short name T10
Test name
Test status
Simulation time 372125285030 ps
CPU time 123.82 seconds
Started Jul 11 05:51:33 PM PDT 24
Finished Jul 11 05:53:38 PM PDT 24
Peak memory 201912 kb
Host smart-5f8bb777-a713-4832-8f11-3d1a236b712c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306202066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2306202066
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2087232030
Short name T662
Test name
Test status
Simulation time 12685436479 ps
CPU time 32.87 seconds
Started Jul 11 05:51:29 PM PDT 24
Finished Jul 11 05:52:04 PM PDT 24
Peak memory 210644 kb
Host smart-01a5fac3-b646-4a3f-b322-d80f0e8e1ac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087232030 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2087232030
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2420453635
Short name T698
Test name
Test status
Simulation time 593765174 ps
CPU time 0.69 seconds
Started Jul 11 05:51:48 PM PDT 24
Finished Jul 11 05:51:51 PM PDT 24
Peak memory 201672 kb
Host smart-96e6efd2-6980-46bd-890c-7c656639534d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420453635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2420453635
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2413033481
Short name T695
Test name
Test status
Simulation time 161422697439 ps
CPU time 179.17 seconds
Started Jul 11 05:51:48 PM PDT 24
Finished Jul 11 05:54:48 PM PDT 24
Peak memory 201960 kb
Host smart-8319c511-07b1-4f9f-bc01-fe7de205e501
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413033481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2413033481
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2496066078
Short name T331
Test name
Test status
Simulation time 183752317058 ps
CPU time 204.97 seconds
Started Jul 11 05:51:45 PM PDT 24
Finished Jul 11 05:55:11 PM PDT 24
Peak memory 201916 kb
Host smart-6ab4b695-f13e-45d5-8ed4-ce3d245e8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496066078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2496066078
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1620912670
Short name T118
Test name
Test status
Simulation time 494713600114 ps
CPU time 1156.86 seconds
Started Jul 11 05:51:37 PM PDT 24
Finished Jul 11 06:10:56 PM PDT 24
Peak memory 201848 kb
Host smart-b76cdb32-afa9-42c3-be5a-ba9e79d0cf0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620912670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1620912670
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.439015211
Short name T215
Test name
Test status
Simulation time 332674606020 ps
CPU time 140.95 seconds
Started Jul 11 05:51:40 PM PDT 24
Finished Jul 11 05:54:02 PM PDT 24
Peak memory 201972 kb
Host smart-e4eb0649-f889-4394-a0ca-4048b2d4fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439015211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.439015211
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3401867612
Short name T684
Test name
Test status
Simulation time 328539156677 ps
CPU time 188.8 seconds
Started Jul 11 05:51:37 PM PDT 24
Finished Jul 11 05:54:47 PM PDT 24
Peak memory 201860 kb
Host smart-bdb0104a-cb91-40e9-be11-da68de8ee953
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401867612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3401867612
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1551960276
Short name T576
Test name
Test status
Simulation time 170999092211 ps
CPU time 387.35 seconds
Started Jul 11 05:51:36 PM PDT 24
Finished Jul 11 05:58:04 PM PDT 24
Peak memory 201924 kb
Host smart-a69dfef3-86ea-4101-a6ac-21b92d28899c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551960276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1551960276
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2140576065
Short name T442
Test name
Test status
Simulation time 408192990189 ps
CPU time 258.86 seconds
Started Jul 11 05:51:38 PM PDT 24
Finished Jul 11 05:55:58 PM PDT 24
Peak memory 201900 kb
Host smart-ac86ba5f-a17c-4b53-8503-0c7f91e3cd90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140576065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2140576065
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3045941828
Short name T503
Test name
Test status
Simulation time 94109754342 ps
CPU time 327.02 seconds
Started Jul 11 05:51:51 PM PDT 24
Finished Jul 11 05:57:19 PM PDT 24
Peak memory 202208 kb
Host smart-30f90d95-ff74-48c0-9da4-995fa2f48b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045941828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3045941828
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.919056318
Short name T743
Test name
Test status
Simulation time 34910793059 ps
CPU time 72.72 seconds
Started Jul 11 05:51:52 PM PDT 24
Finished Jul 11 05:53:06 PM PDT 24
Peak memory 201684 kb
Host smart-7a46a754-be2b-401a-9b28-3c571e3b69b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919056318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.919056318
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3136941928
Short name T107
Test name
Test status
Simulation time 3277806196 ps
CPU time 1.53 seconds
Started Jul 11 05:51:53 PM PDT 24
Finished Jul 11 05:51:55 PM PDT 24
Peak memory 201688 kb
Host smart-4fae6bf1-578b-4b49-a297-7d173bdd1675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136941928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3136941928
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3572899149
Short name T385
Test name
Test status
Simulation time 6080507849 ps
CPU time 1.54 seconds
Started Jul 11 05:51:37 PM PDT 24
Finished Jul 11 05:51:40 PM PDT 24
Peak memory 201704 kb
Host smart-a312aa83-ed26-422f-88de-4a643006ca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572899149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3572899149
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1586443396
Short name T320
Test name
Test status
Simulation time 360731017816 ps
CPU time 762.69 seconds
Started Jul 11 05:51:48 PM PDT 24
Finished Jul 11 06:04:32 PM PDT 24
Peak memory 201976 kb
Host smart-b3a03a67-efeb-45fa-ba09-d063a2d0c8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586443396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1586443396
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1190989074
Short name T274
Test name
Test status
Simulation time 306311628524 ps
CPU time 192.77 seconds
Started Jul 11 05:51:41 PM PDT 24
Finished Jul 11 05:54:55 PM PDT 24
Peak memory 210276 kb
Host smart-138b2c3f-3786-4984-afc5-26e72a78a83f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190989074 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1190989074
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3745838224
Short name T630
Test name
Test status
Simulation time 513890317 ps
CPU time 1.79 seconds
Started Jul 11 05:52:20 PM PDT 24
Finished Jul 11 05:52:22 PM PDT 24
Peak memory 201604 kb
Host smart-fcdc1504-a17e-403f-b7c6-3bd33620a089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745838224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3745838224
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2516632551
Short name T104
Test name
Test status
Simulation time 191176314416 ps
CPU time 387.17 seconds
Started Jul 11 05:51:54 PM PDT 24
Finished Jul 11 05:58:22 PM PDT 24
Peak memory 201916 kb
Host smart-26002682-83a1-4365-a847-ee3e1061a184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516632551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2516632551
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.4102665850
Short name T328
Test name
Test status
Simulation time 331280837460 ps
CPU time 782.78 seconds
Started Jul 11 05:51:49 PM PDT 24
Finished Jul 11 06:04:53 PM PDT 24
Peak memory 201908 kb
Host smart-053fef8c-5ba8-4f7f-bf3d-a505f0d9fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102665850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4102665850
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3584238986
Short name T672
Test name
Test status
Simulation time 498564500422 ps
CPU time 580.49 seconds
Started Jul 11 05:51:48 PM PDT 24
Finished Jul 11 06:01:30 PM PDT 24
Peak memory 201880 kb
Host smart-b85361db-37d0-449f-9b8c-4b3596ecb532
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584238986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3584238986
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3609489487
Short name T162
Test name
Test status
Simulation time 493959382283 ps
CPU time 281.78 seconds
Started Jul 11 05:51:52 PM PDT 24
Finished Jul 11 05:56:35 PM PDT 24
Peak memory 202068 kb
Host smart-16d2ad17-eb59-4bfd-98ee-1559321f151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609489487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3609489487
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.250439069
Short name T717
Test name
Test status
Simulation time 161188509867 ps
CPU time 69.18 seconds
Started Jul 11 05:51:48 PM PDT 24
Finished Jul 11 05:52:58 PM PDT 24
Peak memory 201880 kb
Host smart-65f9fc6a-38b7-4bb7-b75f-defbe4887a9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=250439069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.250439069
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3187014506
Short name T475
Test name
Test status
Simulation time 173133269730 ps
CPU time 370.65 seconds
Started Jul 11 05:51:48 PM PDT 24
Finished Jul 11 05:58:01 PM PDT 24
Peak memory 201972 kb
Host smart-cced5afd-9a26-4e0c-b737-0a9496b961e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187014506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3187014506
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1131826376
Short name T225
Test name
Test status
Simulation time 411417750589 ps
CPU time 479.95 seconds
Started Jul 11 05:51:58 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 201940 kb
Host smart-083aaf6a-58b2-4342-8121-0fff7b356956
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131826376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1131826376
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3885555904
Short name T780
Test name
Test status
Simulation time 88255369546 ps
CPU time 471.61 seconds
Started Jul 11 05:51:55 PM PDT 24
Finished Jul 11 05:59:49 PM PDT 24
Peak memory 202200 kb
Host smart-81843211-d651-4fc8-b773-ef89ccc4b533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885555904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3885555904
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3655151103
Short name T753
Test name
Test status
Simulation time 30839451318 ps
CPU time 36.2 seconds
Started Jul 11 05:51:58 PM PDT 24
Finished Jul 11 05:52:36 PM PDT 24
Peak memory 201712 kb
Host smart-9c1a323a-970a-441d-bf30-f2407f600dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655151103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3655151103
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3675693620
Short name T537
Test name
Test status
Simulation time 3177872490 ps
CPU time 7.91 seconds
Started Jul 11 05:52:01 PM PDT 24
Finished Jul 11 05:52:09 PM PDT 24
Peak memory 201612 kb
Host smart-d4ace36d-a6fc-47e9-a7b6-fae83293ac0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675693620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3675693620
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4131094719
Short name T592
Test name
Test status
Simulation time 5922758007 ps
CPU time 8.38 seconds
Started Jul 11 05:51:50 PM PDT 24
Finished Jul 11 05:52:00 PM PDT 24
Peak memory 201740 kb
Host smart-6b0c74b3-b51f-4833-a620-b0d189436e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131094719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4131094719
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1211034189
Short name T44
Test name
Test status
Simulation time 157619631459 ps
CPU time 157.49 seconds
Started Jul 11 05:52:08 PM PDT 24
Finished Jul 11 05:54:47 PM PDT 24
Peak memory 217956 kb
Host smart-e5147f03-68fd-48d6-aca7-06e405a8213f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211034189 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1211034189
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2955700005
Short name T647
Test name
Test status
Simulation time 483437380 ps
CPU time 1.7 seconds
Started Jul 11 05:52:09 PM PDT 24
Finished Jul 11 05:52:12 PM PDT 24
Peak memory 201672 kb
Host smart-f6dd3abe-c15f-48fe-8251-7daec8084026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955700005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2955700005
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3320744796
Short name T183
Test name
Test status
Simulation time 543471042622 ps
CPU time 622.25 seconds
Started Jul 11 05:52:20 PM PDT 24
Finished Jul 11 06:02:44 PM PDT 24
Peak memory 201904 kb
Host smart-b9d03946-e2ab-4459-bc0d-79fd14e23037
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320744796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3320744796
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2290257942
Short name T94
Test name
Test status
Simulation time 167051081398 ps
CPU time 194.47 seconds
Started Jul 11 05:52:20 PM PDT 24
Finished Jul 11 05:55:36 PM PDT 24
Peak memory 201868 kb
Host smart-e65bf742-55cf-4f8f-a488-fbda7aef5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290257942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2290257942
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4064844246
Short name T145
Test name
Test status
Simulation time 162907015340 ps
CPU time 102.87 seconds
Started Jul 11 05:52:02 PM PDT 24
Finished Jul 11 05:53:45 PM PDT 24
Peak memory 201980 kb
Host smart-76ea258b-407a-4f73-b823-843698558925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064844246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4064844246
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4148035558
Short name T795
Test name
Test status
Simulation time 495557255166 ps
CPU time 1189.1 seconds
Started Jul 11 05:52:04 PM PDT 24
Finished Jul 11 06:11:54 PM PDT 24
Peak memory 201860 kb
Host smart-fe1e1df3-4657-49df-909b-5b03d35241d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148035558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4148035558
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3429216977
Short name T679
Test name
Test status
Simulation time 172599950076 ps
CPU time 407.1 seconds
Started Jul 11 05:52:04 PM PDT 24
Finished Jul 11 05:58:52 PM PDT 24
Peak memory 201956 kb
Host smart-1d74ecf6-5316-46bf-91aa-d1934c25bc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429216977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3429216977
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2284826584
Short name T408
Test name
Test status
Simulation time 161464092938 ps
CPU time 349.49 seconds
Started Jul 11 05:52:20 PM PDT 24
Finished Jul 11 05:58:11 PM PDT 24
Peak memory 201824 kb
Host smart-b290d130-df20-452b-93f3-089d67def034
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284826584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2284826584
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1010871857
Short name T193
Test name
Test status
Simulation time 450584180141 ps
CPU time 959.26 seconds
Started Jul 11 05:52:20 PM PDT 24
Finished Jul 11 06:08:20 PM PDT 24
Peak memory 201864 kb
Host smart-5579dfe2-0583-4796-bdec-e912ec94da74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010871857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1010871857
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3680011811
Short name T744
Test name
Test status
Simulation time 200437307840 ps
CPU time 120.89 seconds
Started Jul 11 05:52:20 PM PDT 24
Finished Jul 11 05:54:22 PM PDT 24
Peak memory 201836 kb
Host smart-74419bb0-acd2-48f7-8c2c-2decb39ede09
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680011811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3680011811
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1094903558
Short name T578
Test name
Test status
Simulation time 77205007478 ps
CPU time 365.53 seconds
Started Jul 11 05:52:21 PM PDT 24
Finished Jul 11 05:58:27 PM PDT 24
Peak memory 202220 kb
Host smart-46ab4587-561e-4641-955d-1f20e3a2e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094903558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1094903558
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4089800498
Short name T427
Test name
Test status
Simulation time 30348842463 ps
CPU time 63.68 seconds
Started Jul 11 05:52:03 PM PDT 24
Finished Jul 11 05:53:08 PM PDT 24
Peak memory 201696 kb
Host smart-7b857b64-f74d-400f-a3b4-870d52bca8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089800498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4089800498
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2488797717
Short name T395
Test name
Test status
Simulation time 4553937742 ps
CPU time 3.1 seconds
Started Jul 11 05:52:20 PM PDT 24
Finished Jul 11 05:52:25 PM PDT 24
Peak memory 201656 kb
Host smart-4634cdb5-2ec7-4853-a72b-a14c03a506d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488797717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2488797717
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.774754132
Short name T692
Test name
Test status
Simulation time 5986956870 ps
CPU time 13.12 seconds
Started Jul 11 05:52:02 PM PDT 24
Finished Jul 11 05:52:16 PM PDT 24
Peak memory 201660 kb
Host smart-047e62c0-594e-4aec-b385-c22140c4e770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774754132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.774754132
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3746306016
Short name T309
Test name
Test status
Simulation time 329977539153 ps
CPU time 187.28 seconds
Started Jul 11 05:52:07 PM PDT 24
Finished Jul 11 05:55:15 PM PDT 24
Peak memory 201896 kb
Host smart-07a66508-b31c-46f7-9145-90db34c23a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746306016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3746306016
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2024191876
Short name T759
Test name
Test status
Simulation time 174445215325 ps
CPU time 263.33 seconds
Started Jul 11 05:52:01 PM PDT 24
Finished Jul 11 05:56:25 PM PDT 24
Peak memory 218340 kb
Host smart-f3dc6ee9-10f0-4583-a529-b368aefd24de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024191876 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2024191876
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1612776123
Short name T390
Test name
Test status
Simulation time 397967696 ps
CPU time 0.85 seconds
Started Jul 11 05:52:10 PM PDT 24
Finished Jul 11 05:52:12 PM PDT 24
Peak memory 201652 kb
Host smart-8c2a421d-2bb0-466a-b94f-6bf0d174cdbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612776123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1612776123
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.247589251
Short name T279
Test name
Test status
Simulation time 538895996820 ps
CPU time 194.65 seconds
Started Jul 11 05:52:05 PM PDT 24
Finished Jul 11 05:55:21 PM PDT 24
Peak memory 201968 kb
Host smart-932c3918-4bb2-4336-9531-976a744e5dae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247589251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.247589251
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1724278445
Short name T369
Test name
Test status
Simulation time 348142118386 ps
CPU time 242.66 seconds
Started Jul 11 05:52:09 PM PDT 24
Finished Jul 11 05:56:13 PM PDT 24
Peak memory 201928 kb
Host smart-8e31e105-9505-4599-916f-c344c1aff321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724278445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1724278445
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4079811306
Short name T560
Test name
Test status
Simulation time 499228268873 ps
CPU time 127.5 seconds
Started Jul 11 05:52:07 PM PDT 24
Finished Jul 11 05:54:15 PM PDT 24
Peak memory 201828 kb
Host smart-685e5ef0-35b0-4ce3-9935-b8ef48d72336
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079811306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4079811306
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2242530245
Short name T161
Test name
Test status
Simulation time 165486009235 ps
CPU time 78.22 seconds
Started Jul 11 05:52:08 PM PDT 24
Finished Jul 11 05:53:28 PM PDT 24
Peak memory 202000 kb
Host smart-a2f917ad-2804-4163-a1fe-c785c1822905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242530245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2242530245
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2025671184
Short name T641
Test name
Test status
Simulation time 158948247112 ps
CPU time 175.24 seconds
Started Jul 11 05:52:09 PM PDT 24
Finished Jul 11 05:55:05 PM PDT 24
Peak memory 201824 kb
Host smart-b06793a5-9565-4359-8b61-a24da8642292
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025671184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2025671184
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.558713430
Short name T453
Test name
Test status
Simulation time 406265745277 ps
CPU time 267.08 seconds
Started Jul 11 05:52:09 PM PDT 24
Finished Jul 11 05:56:37 PM PDT 24
Peak memory 201884 kb
Host smart-b5da0c33-a90a-491a-ba39-02fa0c3f8eac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558713430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.558713430
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3853889233
Short name T583
Test name
Test status
Simulation time 69271548311 ps
CPU time 266.65 seconds
Started Jul 11 05:52:16 PM PDT 24
Finished Jul 11 05:56:44 PM PDT 24
Peak memory 202232 kb
Host smart-5ab10eac-4c5c-4495-b80d-145295ecb14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853889233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3853889233
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.239568981
Short name T241
Test name
Test status
Simulation time 41109597935 ps
CPU time 25.11 seconds
Started Jul 11 05:52:11 PM PDT 24
Finished Jul 11 05:52:38 PM PDT 24
Peak memory 201580 kb
Host smart-415e987b-29bd-4027-a05a-e6a1f2fccdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239568981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.239568981
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2691710417
Short name T765
Test name
Test status
Simulation time 5138168988 ps
CPU time 12.09 seconds
Started Jul 11 05:52:13 PM PDT 24
Finished Jul 11 05:52:26 PM PDT 24
Peak memory 201720 kb
Host smart-38a80dc1-e1b8-457c-88e3-b913fdfb5d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691710417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2691710417
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1217367553
Short name T582
Test name
Test status
Simulation time 6064913924 ps
CPU time 3.8 seconds
Started Jul 11 05:52:08 PM PDT 24
Finished Jul 11 05:52:13 PM PDT 24
Peak memory 201704 kb
Host smart-788bc0db-533e-4795-aee3-16d116848a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217367553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1217367553
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3881618246
Short name T488
Test name
Test status
Simulation time 277028642426 ps
CPU time 625.53 seconds
Started Jul 11 05:52:12 PM PDT 24
Finished Jul 11 06:02:39 PM PDT 24
Peak memory 210404 kb
Host smart-61f69a8f-1fb9-4f3c-90b4-47ad37ec3e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881618246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3881618246
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1142904728
Short name T375
Test name
Test status
Simulation time 81036621784 ps
CPU time 161.3 seconds
Started Jul 11 05:52:21 PM PDT 24
Finished Jul 11 05:55:03 PM PDT 24
Peak memory 210488 kb
Host smart-5332baef-7410-4aec-a805-7720b848730c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142904728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1142904728
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.321288519
Short name T516
Test name
Test status
Simulation time 400697442 ps
CPU time 0.83 seconds
Started Jul 11 05:52:19 PM PDT 24
Finished Jul 11 05:52:20 PM PDT 24
Peak memory 201648 kb
Host smart-5b438b6c-3c34-47ef-9f47-5c7c969e1dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321288519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.321288519
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3058175959
Short name T776
Test name
Test status
Simulation time 163478068215 ps
CPU time 100.87 seconds
Started Jul 11 05:52:11 PM PDT 24
Finished Jul 11 05:53:53 PM PDT 24
Peak memory 201864 kb
Host smart-e94b1b1e-9412-4790-bfc4-498104adefb7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058175959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3058175959
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3521592502
Short name T315
Test name
Test status
Simulation time 324380611117 ps
CPU time 178.99 seconds
Started Jul 11 05:52:10 PM PDT 24
Finished Jul 11 05:55:10 PM PDT 24
Peak memory 201916 kb
Host smart-aa5f694c-1cf0-4f96-9471-a4e0b1bb9fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521592502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3521592502
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4215379884
Short name T631
Test name
Test status
Simulation time 168509839625 ps
CPU time 383.5 seconds
Started Jul 11 05:52:14 PM PDT 24
Finished Jul 11 05:58:38 PM PDT 24
Peak memory 201768 kb
Host smart-2adefcbd-c5f3-4fe7-93c4-a8c3221181f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215379884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4215379884
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2198546731
Short name T337
Test name
Test status
Simulation time 396467512653 ps
CPU time 831.83 seconds
Started Jul 11 05:52:16 PM PDT 24
Finished Jul 11 06:06:09 PM PDT 24
Peak memory 201896 kb
Host smart-064ed046-c720-4984-b05d-0b09f8929fae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198546731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2198546731
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3219029217
Short name T426
Test name
Test status
Simulation time 391888426613 ps
CPU time 234.93 seconds
Started Jul 11 05:52:14 PM PDT 24
Finished Jul 11 05:56:10 PM PDT 24
Peak memory 201920 kb
Host smart-214b9553-2db9-4c36-8af5-9585321d728b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219029217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3219029217
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1694240042
Short name T556
Test name
Test status
Simulation time 78415433457 ps
CPU time 394.15 seconds
Started Jul 11 05:52:17 PM PDT 24
Finished Jul 11 05:58:52 PM PDT 24
Peak memory 202224 kb
Host smart-4c750092-404e-4e6c-921b-22d6cda7eb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694240042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1694240042
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1316182296
Short name T392
Test name
Test status
Simulation time 33421749227 ps
CPU time 10.63 seconds
Started Jul 11 05:52:18 PM PDT 24
Finished Jul 11 05:52:30 PM PDT 24
Peak memory 201716 kb
Host smart-ff3ab941-1cdd-4ec0-8281-25ce2d742171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316182296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1316182296
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3317703884
Short name T581
Test name
Test status
Simulation time 3420515822 ps
CPU time 2.51 seconds
Started Jul 11 05:52:17 PM PDT 24
Finished Jul 11 05:52:21 PM PDT 24
Peak memory 201720 kb
Host smart-4ad98a54-b6a4-417d-aaec-d4e1ceef372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317703884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3317703884
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.481718093
Short name T218
Test name
Test status
Simulation time 6140405162 ps
CPU time 14.75 seconds
Started Jul 11 05:52:14 PM PDT 24
Finished Jul 11 05:52:30 PM PDT 24
Peak memory 201580 kb
Host smart-2d841107-c875-4d17-98a9-4020bdf7a493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481718093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.481718093
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.267172484
Short name T771
Test name
Test status
Simulation time 165782720706 ps
CPU time 345.64 seconds
Started Jul 11 05:52:19 PM PDT 24
Finished Jul 11 05:58:06 PM PDT 24
Peak memory 201928 kb
Host smart-fbe635c8-55c6-4510-9316-5658e53c7697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267172484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
267172484
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1767109267
Short name T29
Test name
Test status
Simulation time 208215266031 ps
CPU time 66.66 seconds
Started Jul 11 05:52:21 PM PDT 24
Finished Jul 11 05:53:29 PM PDT 24
Peak memory 210556 kb
Host smart-82c5f8e0-49b0-44f6-89ae-af0869cd2d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767109267 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1767109267
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2421195334
Short name T439
Test name
Test status
Simulation time 410038969 ps
CPU time 0.83 seconds
Started Jul 11 05:52:27 PM PDT 24
Finished Jul 11 05:52:28 PM PDT 24
Peak memory 201668 kb
Host smart-94e937df-f948-4575-8e41-94ae76741baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421195334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2421195334
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2235335118
Short name T360
Test name
Test status
Simulation time 329256052981 ps
CPU time 446.9 seconds
Started Jul 11 05:52:34 PM PDT 24
Finished Jul 11 06:00:01 PM PDT 24
Peak memory 201896 kb
Host smart-1b015627-a994-4722-8027-cc28055f463e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235335118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2235335118
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2568504041
Short name T545
Test name
Test status
Simulation time 540395751466 ps
CPU time 1169.12 seconds
Started Jul 11 05:52:34 PM PDT 24
Finished Jul 11 06:12:04 PM PDT 24
Peak memory 201936 kb
Host smart-836b1942-14cb-4b61-b219-878010a72814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568504041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2568504041
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1756653806
Short name T723
Test name
Test status
Simulation time 493058211617 ps
CPU time 552.28 seconds
Started Jul 11 05:52:34 PM PDT 24
Finished Jul 11 06:01:47 PM PDT 24
Peak memory 201936 kb
Host smart-c704985c-1fc9-409e-9d56-dfd93f23ce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756653806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1756653806
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1811052555
Short name T189
Test name
Test status
Simulation time 332480564880 ps
CPU time 379.8 seconds
Started Jul 11 05:52:30 PM PDT 24
Finished Jul 11 05:58:50 PM PDT 24
Peak memory 201796 kb
Host smart-d2cd3114-e382-4039-9bbd-7472dd9d0176
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811052555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1811052555
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3688474748
Short name T268
Test name
Test status
Simulation time 332643963179 ps
CPU time 342.14 seconds
Started Jul 11 05:52:23 PM PDT 24
Finished Jul 11 05:58:06 PM PDT 24
Peak memory 201912 kb
Host smart-b93e6da8-4fe7-492f-be63-a4de2feda5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688474748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3688474748
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.853816100
Short name T227
Test name
Test status
Simulation time 329239445866 ps
CPU time 192.05 seconds
Started Jul 11 05:52:21 PM PDT 24
Finished Jul 11 05:55:34 PM PDT 24
Peak memory 201972 kb
Host smart-0249bd40-7d67-4399-943d-e7a19617910b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=853816100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.853816100
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.94019524
Short name T688
Test name
Test status
Simulation time 545190027951 ps
CPU time 616.58 seconds
Started Jul 11 05:52:28 PM PDT 24
Finished Jul 11 06:02:45 PM PDT 24
Peak memory 201976 kb
Host smart-8b8fb586-6ae5-4a28-80f7-9264e6e5fa2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94019524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_w
akeup.94019524
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1586444156
Short name T725
Test name
Test status
Simulation time 382537163734 ps
CPU time 838.59 seconds
Started Jul 11 05:52:29 PM PDT 24
Finished Jul 11 06:06:28 PM PDT 24
Peak memory 201816 kb
Host smart-60cd9998-b33e-4b0b-bf05-8129b4817178
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586444156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1586444156
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3826707979
Short name T175
Test name
Test status
Simulation time 98699949038 ps
CPU time 475.03 seconds
Started Jul 11 05:52:28 PM PDT 24
Finished Jul 11 06:00:24 PM PDT 24
Peak memory 202228 kb
Host smart-499c5fc9-aa88-4303-8723-8301a1c2af62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826707979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3826707979
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.801748595
Short name T464
Test name
Test status
Simulation time 33111982281 ps
CPU time 18.51 seconds
Started Jul 11 05:52:33 PM PDT 24
Finished Jul 11 05:52:52 PM PDT 24
Peak memory 201712 kb
Host smart-8d321f48-2202-438d-888a-5d2e8a7e5aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801748595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.801748595
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.369053677
Short name T758
Test name
Test status
Simulation time 3909976665 ps
CPU time 5.04 seconds
Started Jul 11 05:52:34 PM PDT 24
Finished Jul 11 05:52:39 PM PDT 24
Peak memory 201708 kb
Host smart-22959094-9451-48c4-bd18-165684318c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369053677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.369053677
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.462187688
Short name T26
Test name
Test status
Simulation time 5765566006 ps
CPU time 14.82 seconds
Started Jul 11 05:52:23 PM PDT 24
Finished Jul 11 05:52:38 PM PDT 24
Peak memory 201624 kb
Host smart-b7475bfa-07b7-4d61-85c4-48f0a78e9b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462187688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.462187688
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.715695946
Short name T606
Test name
Test status
Simulation time 277038475321 ps
CPU time 282.38 seconds
Started Jul 11 05:52:34 PM PDT 24
Finished Jul 11 05:57:17 PM PDT 24
Peak memory 210424 kb
Host smart-5f53eb5d-fcc0-4b4a-8bb3-5aa8f68b9f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715695946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
715695946
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2164246153
Short name T23
Test name
Test status
Simulation time 65066017197 ps
CPU time 136.27 seconds
Started Jul 11 05:52:28 PM PDT 24
Finished Jul 11 05:54:45 PM PDT 24
Peak memory 202088 kb
Host smart-b40b3662-8086-41bb-bc06-e6613d425098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164246153 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2164246153
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1877683855
Short name T486
Test name
Test status
Simulation time 386910558 ps
CPU time 0.73 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:48:46 PM PDT 24
Peak memory 201608 kb
Host smart-8d332d5f-498e-48e0-b683-d83d04e19411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877683855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1877683855
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1903772430
Short name T213
Test name
Test status
Simulation time 511657838498 ps
CPU time 227.81 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 05:52:18 PM PDT 24
Peak memory 202164 kb
Host smart-e1fdd142-5a59-4469-897a-7f3ccb6dc870
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903772430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1903772430
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3678874123
Short name T352
Test name
Test status
Simulation time 340369518395 ps
CPU time 721 seconds
Started Jul 11 05:48:29 PM PDT 24
Finished Jul 11 06:00:32 PM PDT 24
Peak memory 201916 kb
Host smart-4941f970-e4a0-4449-802f-7bc27b9f8e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678874123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3678874123
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1206896658
Short name T333
Test name
Test status
Simulation time 333023994917 ps
CPU time 710.79 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 06:00:43 PM PDT 24
Peak memory 201872 kb
Host smart-05692646-b117-449b-906d-52ebb9d31170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206896658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1206896658
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3238305926
Short name T548
Test name
Test status
Simulation time 332807270524 ps
CPU time 204.88 seconds
Started Jul 11 05:48:38 PM PDT 24
Finished Jul 11 05:52:04 PM PDT 24
Peak memory 201876 kb
Host smart-e0c3b8bf-80fd-44d1-8b5e-180082297de4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238305926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3238305926
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1928701412
Short name T172
Test name
Test status
Simulation time 496474196638 ps
CPU time 437.31 seconds
Started Jul 11 05:48:36 PM PDT 24
Finished Jul 11 05:55:55 PM PDT 24
Peak memory 201916 kb
Host smart-f76c6124-459d-4f3c-8f8b-874379b47221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928701412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1928701412
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3793487343
Short name T27
Test name
Test status
Simulation time 327917880809 ps
CPU time 702.61 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 06:00:13 PM PDT 24
Peak memory 201792 kb
Host smart-8514406a-a028-45c9-b33a-d9f56902c21e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793487343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3793487343
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3917362722
Short name T661
Test name
Test status
Simulation time 405631905797 ps
CPU time 886.43 seconds
Started Jul 11 05:48:54 PM PDT 24
Finished Jul 11 06:03:46 PM PDT 24
Peak memory 201920 kb
Host smart-d7f48aa4-405e-4ee7-8137-e642a1c26606
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917362722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3917362722
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.96367945
Short name T417
Test name
Test status
Simulation time 390153064037 ps
CPU time 87.81 seconds
Started Jul 11 05:48:45 PM PDT 24
Finished Jul 11 05:50:16 PM PDT 24
Peak memory 201872 kb
Host smart-13dfe942-d06a-4638-869b-e02ae5d06353
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96367945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.ad
c_ctrl_filters_wakeup_fixed.96367945
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.276147740
Short name T252
Test name
Test status
Simulation time 93433695759 ps
CPU time 346.94 seconds
Started Jul 11 05:48:25 PM PDT 24
Finished Jul 11 05:54:16 PM PDT 24
Peak memory 202292 kb
Host smart-5e683ffa-34b7-44d1-a485-98c33d1f640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276147740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.276147740
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1695427414
Short name T507
Test name
Test status
Simulation time 35196937036 ps
CPU time 83 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:50:07 PM PDT 24
Peak memory 201640 kb
Host smart-668c6e51-123d-412c-9bb9-b52d7b8448f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695427414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1695427414
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1641403565
Short name T773
Test name
Test status
Simulation time 2986718350 ps
CPU time 4.19 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 05:48:34 PM PDT 24
Peak memory 201712 kb
Host smart-88b34a31-363c-4756-b087-b8c7dfc5191a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641403565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1641403565
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2615730243
Short name T117
Test name
Test status
Simulation time 5823550086 ps
CPU time 14.13 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 05:48:48 PM PDT 24
Peak memory 201708 kb
Host smart-09832133-ca31-430d-bf32-093a133010c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615730243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2615730243
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2901037451
Short name T33
Test name
Test status
Simulation time 168315588162 ps
CPU time 394.08 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:55:19 PM PDT 24
Peak memory 201948 kb
Host smart-cda465b0-0b96-4231-80ea-0ed3c6da1b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901037451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2901037451
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.349590364
Short name T198
Test name
Test status
Simulation time 220816102068 ps
CPU time 129.74 seconds
Started Jul 11 05:48:57 PM PDT 24
Finished Jul 11 05:51:15 PM PDT 24
Peak memory 210296 kb
Host smart-8b1bb3cc-e794-48d4-97aa-9142efcacc7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349590364 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.349590364
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2296588459
Short name T563
Test name
Test status
Simulation time 308434908 ps
CPU time 0.76 seconds
Started Jul 11 05:48:40 PM PDT 24
Finished Jul 11 05:48:42 PM PDT 24
Peak memory 201656 kb
Host smart-4b705764-dab1-483e-aafd-f8760ee1e8e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296588459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2296588459
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1977215729
Short name T152
Test name
Test status
Simulation time 325689286316 ps
CPU time 735.39 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 06:01:08 PM PDT 24
Peak memory 201852 kb
Host smart-8f4312df-34e6-4316-bd5b-12b20c72331a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977215729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1977215729
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4268518364
Short name T149
Test name
Test status
Simulation time 166735075388 ps
CPU time 49.68 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:49:35 PM PDT 24
Peak memory 201916 kb
Host smart-1fdecb15-8b24-49eb-9a08-b5c8e6c57ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268518364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4268518364
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3649061054
Short name T553
Test name
Test status
Simulation time 494338914448 ps
CPU time 92.72 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 05:50:06 PM PDT 24
Peak memory 201904 kb
Host smart-9b8c0e12-857b-4fc9-91c3-d690774f0323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649061054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3649061054
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.447953270
Short name T707
Test name
Test status
Simulation time 164394369408 ps
CPU time 26.22 seconds
Started Jul 11 05:48:27 PM PDT 24
Finished Jul 11 05:48:57 PM PDT 24
Peak memory 201900 kb
Host smart-748038fe-0db3-44f9-a807-ff8688672ff2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=447953270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.447953270
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3539762015
Short name T490
Test name
Test status
Simulation time 319433392953 ps
CPU time 717.8 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 06:00:31 PM PDT 24
Peak memory 201916 kb
Host smart-5f214ee0-1968-42b4-9e00-c41ec7ccff2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539762015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3539762015
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1000619517
Short name T607
Test name
Test status
Simulation time 164920287726 ps
CPU time 245.2 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:52:44 PM PDT 24
Peak memory 201904 kb
Host smart-b7e7526a-d3ec-4a6d-88a8-a4f6da0f0128
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000619517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1000619517
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1413497979
Short name T147
Test name
Test status
Simulation time 333389756428 ps
CPU time 388.56 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:55:08 PM PDT 24
Peak memory 201904 kb
Host smart-293a2300-621a-4ccc-8e65-621d6063a693
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413497979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1413497979
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1340929469
Short name T709
Test name
Test status
Simulation time 192494226192 ps
CPU time 217.61 seconds
Started Jul 11 05:48:46 PM PDT 24
Finished Jul 11 05:52:27 PM PDT 24
Peak memory 201860 kb
Host smart-c2df65cf-c1dd-4d20-858e-6b4ad95df137
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340929469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1340929469
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2865366599
Short name T704
Test name
Test status
Simulation time 114918406480 ps
CPU time 401.86 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:55:21 PM PDT 24
Peak memory 202204 kb
Host smart-50ddb628-931a-4280-9a91-c2fa9fdc523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865366599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2865366599
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1066307394
Short name T206
Test name
Test status
Simulation time 45767819632 ps
CPU time 101.72 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:50:27 PM PDT 24
Peak memory 201708 kb
Host smart-69ac02cd-ebc4-4098-97df-3d714e1dfd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066307394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1066307394
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3772735852
Short name T459
Test name
Test status
Simulation time 3009987264 ps
CPU time 6.8 seconds
Started Jul 11 05:48:45 PM PDT 24
Finished Jul 11 05:48:55 PM PDT 24
Peak memory 201708 kb
Host smart-b35371ef-f616-4e0a-adcb-b57de69f7f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772735852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3772735852
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2357413717
Short name T226
Test name
Test status
Simulation time 5839908797 ps
CPU time 14.98 seconds
Started Jul 11 05:48:54 PM PDT 24
Finished Jul 11 05:49:15 PM PDT 24
Peak memory 201704 kb
Host smart-5210989e-a817-4637-897c-318c25bc4dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357413717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2357413717
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.696761022
Short name T257
Test name
Test status
Simulation time 207341052026 ps
CPU time 411.51 seconds
Started Jul 11 05:48:44 PM PDT 24
Finished Jul 11 05:55:39 PM PDT 24
Peak memory 210548 kb
Host smart-4dfe7b91-7066-4b1c-a6bf-edfb60d10d02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696761022 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.696761022
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4243528339
Short name T585
Test name
Test status
Simulation time 530980729 ps
CPU time 1.71 seconds
Started Jul 11 05:48:35 PM PDT 24
Finished Jul 11 05:48:38 PM PDT 24
Peak memory 201652 kb
Host smart-0bf69e79-5464-41dc-98a6-310e1aab771c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243528339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4243528339
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3160455103
Short name T46
Test name
Test status
Simulation time 176791256902 ps
CPU time 202.39 seconds
Started Jul 11 05:48:39 PM PDT 24
Finished Jul 11 05:52:03 PM PDT 24
Peak memory 201928 kb
Host smart-b72487ac-1119-4026-a74a-4132680d8bc3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160455103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3160455103
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3527154028
Short name T513
Test name
Test status
Simulation time 489532759695 ps
CPU time 298.6 seconds
Started Jul 11 05:48:44 PM PDT 24
Finished Jul 11 05:53:46 PM PDT 24
Peak memory 201892 kb
Host smart-3b854c5f-4744-4b7c-b299-cf73379615ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527154028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3527154028
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3206572979
Short name T678
Test name
Test status
Simulation time 486791960454 ps
CPU time 484.37 seconds
Started Jul 11 05:48:35 PM PDT 24
Finished Jul 11 05:56:41 PM PDT 24
Peak memory 201868 kb
Host smart-0f12a398-f595-46da-9689-f07d54f1675f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206572979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3206572979
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.378696365
Short name T577
Test name
Test status
Simulation time 499728254419 ps
CPU time 285.59 seconds
Started Jul 11 05:48:40 PM PDT 24
Finished Jul 11 05:53:28 PM PDT 24
Peak memory 201904 kb
Host smart-44857a43-b8e8-4a85-8748-1c9b35feab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378696365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.378696365
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1698302333
Short name T229
Test name
Test status
Simulation time 321402118707 ps
CPU time 190.7 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:51:50 PM PDT 24
Peak memory 201888 kb
Host smart-e47eb923-085e-4af8-b58e-39fc550c9f13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698302333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1698302333
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.779265675
Short name T232
Test name
Test status
Simulation time 425542970318 ps
CPU time 928.69 seconds
Started Jul 11 05:48:36 PM PDT 24
Finished Jul 11 06:04:06 PM PDT 24
Peak memory 201824 kb
Host smart-6cb8d47c-419c-4da7-988e-241b36e4339b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779265675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.779265675
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3559248205
Short name T664
Test name
Test status
Simulation time 603114255565 ps
CPU time 350.65 seconds
Started Jul 11 05:48:33 PM PDT 24
Finished Jul 11 05:54:26 PM PDT 24
Peak memory 201876 kb
Host smart-64b0872a-5806-439b-9d55-bfccbd3eecdb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559248205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3559248205
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2273235417
Short name T677
Test name
Test status
Simulation time 36822999332 ps
CPU time 77.7 seconds
Started Jul 11 05:48:44 PM PDT 24
Finished Jul 11 05:50:05 PM PDT 24
Peak memory 201704 kb
Host smart-9eef1a00-6211-4141-bdde-d0e69ecece28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273235417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2273235417
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4080954912
Short name T474
Test name
Test status
Simulation time 4120205173 ps
CPU time 2.92 seconds
Started Jul 11 05:48:38 PM PDT 24
Finished Jul 11 05:48:43 PM PDT 24
Peak memory 201712 kb
Host smart-0f38af3a-57e7-4936-92c0-6c5eb73622b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080954912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4080954912
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3838597173
Short name T234
Test name
Test status
Simulation time 5625388435 ps
CPU time 7.47 seconds
Started Jul 11 05:48:42 PM PDT 24
Finished Jul 11 05:48:52 PM PDT 24
Peak memory 201708 kb
Host smart-002bf547-81c5-4bb1-8d0d-3a285db5b246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838597173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3838597173
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.4038467123
Short name T370
Test name
Test status
Simulation time 585799764098 ps
CPU time 555.62 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 05:58:08 PM PDT 24
Peak memory 209836 kb
Host smart-b5c27e5f-9eaa-43dc-96bf-181adcada7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038467123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
4038467123
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2667429557
Short name T599
Test name
Test status
Simulation time 368646168 ps
CPU time 1.52 seconds
Started Jul 11 05:48:40 PM PDT 24
Finished Jul 11 05:48:43 PM PDT 24
Peak memory 201648 kb
Host smart-64e24483-e078-40fd-afb0-5e0a90189cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667429557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2667429557
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1044130989
Short name T550
Test name
Test status
Simulation time 316436894047 ps
CPU time 428.58 seconds
Started Jul 11 05:48:45 PM PDT 24
Finished Jul 11 05:55:57 PM PDT 24
Peak memory 201888 kb
Host smart-9852b44e-5de5-4962-b645-63c87a26d3ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044130989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1044130989
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.802137092
Short name T740
Test name
Test status
Simulation time 176132414736 ps
CPU time 355.09 seconds
Started Jul 11 05:48:41 PM PDT 24
Finished Jul 11 05:54:37 PM PDT 24
Peak memory 201924 kb
Host smart-f9399792-c6c1-4ad9-b105-ab511ef2be12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802137092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.802137092
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2723503259
Short name T231
Test name
Test status
Simulation time 325165855185 ps
CPU time 199.9 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 05:51:53 PM PDT 24
Peak memory 201916 kb
Host smart-d6b8573c-29f8-43cd-b886-f80d243edefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723503259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2723503259
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1037060844
Short name T562
Test name
Test status
Simulation time 163264493784 ps
CPU time 105.14 seconds
Started Jul 11 05:48:34 PM PDT 24
Finished Jul 11 05:50:20 PM PDT 24
Peak memory 201880 kb
Host smart-f5646aef-dfd7-4b82-92ac-235f4aae45da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037060844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1037060844
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2977903569
Short name T571
Test name
Test status
Simulation time 489146760545 ps
CPU time 1158.17 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 06:08:04 PM PDT 24
Peak memory 201984 kb
Host smart-575e87b3-5ecf-4ab2-b447-916f3df643eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977903569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2977903569
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1207386645
Short name T510
Test name
Test status
Simulation time 323820693593 ps
CPU time 675.81 seconds
Started Jul 11 05:48:41 PM PDT 24
Finished Jul 11 05:59:59 PM PDT 24
Peak memory 201908 kb
Host smart-5044c9f9-bfa0-455d-aa8e-453305ab1950
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207386645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1207386645
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3851661821
Short name T652
Test name
Test status
Simulation time 359914435435 ps
CPU time 63.74 seconds
Started Jul 11 05:48:34 PM PDT 24
Finished Jul 11 05:49:39 PM PDT 24
Peak memory 201896 kb
Host smart-d8997ae3-2cda-4cab-b493-aa4b24d091e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851661821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3851661821
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.659975511
Short name T314
Test name
Test status
Simulation time 197244866830 ps
CPU time 100.32 seconds
Started Jul 11 05:48:37 PM PDT 24
Finished Jul 11 05:50:19 PM PDT 24
Peak memory 201864 kb
Host smart-5327f5e7-8722-403f-8a71-ed17b8530fc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659975511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.659975511
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3962992823
Short name T611
Test name
Test status
Simulation time 116671028252 ps
CPU time 470.64 seconds
Started Jul 11 05:48:39 PM PDT 24
Finished Jul 11 05:56:31 PM PDT 24
Peak memory 202280 kb
Host smart-0d642fdc-6124-40d0-9656-f66be22d8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962992823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3962992823
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2294022682
Short name T761
Test name
Test status
Simulation time 23277338901 ps
CPU time 51.66 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 05:49:44 PM PDT 24
Peak memory 201104 kb
Host smart-51eba4fa-f698-43c1-8100-210bd77cf771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294022682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2294022682
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3609558227
Short name T595
Test name
Test status
Simulation time 2962214532 ps
CPU time 8.14 seconds
Started Jul 11 05:48:35 PM PDT 24
Finished Jul 11 05:48:44 PM PDT 24
Peak memory 201588 kb
Host smart-1367ab9e-8928-468a-adb7-e570f65f25a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609558227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3609558227
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2482586993
Short name T93
Test name
Test status
Simulation time 6017706014 ps
CPU time 3.07 seconds
Started Jul 11 05:48:31 PM PDT 24
Finished Jul 11 05:48:37 PM PDT 24
Peak memory 201928 kb
Host smart-2b74f701-34fb-4c84-a203-00ccd8e4c5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482586993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2482586993
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4257788362
Short name T74
Test name
Test status
Simulation time 40549775530 ps
CPU time 21.46 seconds
Started Jul 11 05:49:28 PM PDT 24
Finished Jul 11 05:49:51 PM PDT 24
Peak memory 201680 kb
Host smart-a7beb003-0f8d-48ca-9d9f-d3cc492e4fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257788362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4257788362
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.147761585
Short name T298
Test name
Test status
Simulation time 150258436228 ps
CPU time 118.45 seconds
Started Jul 11 05:48:47 PM PDT 24
Finished Jul 11 05:50:49 PM PDT 24
Peak memory 217984 kb
Host smart-58da015b-830b-49ed-95eb-34c19cbf089d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147761585 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.147761585
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2545243923
Short name T380
Test name
Test status
Simulation time 523155718 ps
CPU time 1.8 seconds
Started Jul 11 05:48:48 PM PDT 24
Finished Jul 11 05:48:52 PM PDT 24
Peak memory 201592 kb
Host smart-d09b0fc9-7afe-45de-9692-c2fa20479b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545243923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2545243923
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2253610829
Short name T237
Test name
Test status
Simulation time 161734009928 ps
CPU time 41.78 seconds
Started Jul 11 05:48:41 PM PDT 24
Finished Jul 11 05:49:24 PM PDT 24
Peak memory 201920 kb
Host smart-e43df303-3b2a-4b83-800f-e1864673a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253610829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2253610829
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3336445033
Short name T718
Test name
Test status
Simulation time 167497311985 ps
CPU time 38.02 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 05:49:30 PM PDT 24
Peak memory 201832 kb
Host smart-e2acd2c0-081e-42c7-ad1d-c329b6995811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336445033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3336445033
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4133004359
Short name T509
Test name
Test status
Simulation time 165227348440 ps
CPU time 102.01 seconds
Started Jul 11 05:48:51 PM PDT 24
Finished Jul 11 05:50:38 PM PDT 24
Peak memory 201876 kb
Host smart-39ba8863-1f5f-4f3b-b3c4-404f492d294d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133004359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4133004359
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3319530559
Short name T287
Test name
Test status
Simulation time 166102524991 ps
CPU time 388.08 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:55:15 PM PDT 24
Peak memory 201952 kb
Host smart-f538cbe5-bd47-4530-9bbd-ac574d7df3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319530559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3319530559
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3211508868
Short name T440
Test name
Test status
Simulation time 502167055222 ps
CPU time 1113.8 seconds
Started Jul 11 05:48:49 PM PDT 24
Finished Jul 11 06:07:26 PM PDT 24
Peak memory 201908 kb
Host smart-27ea9378-a410-4338-ac4a-e58ac813f394
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211508868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3211508868
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2167574433
Short name T167
Test name
Test status
Simulation time 343177238580 ps
CPU time 776.49 seconds
Started Jul 11 05:48:45 PM PDT 24
Finished Jul 11 06:01:45 PM PDT 24
Peak memory 201852 kb
Host smart-567a34d0-d0d8-402c-bc61-22ee98f2bec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167574433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2167574433
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3841833734
Short name T438
Test name
Test status
Simulation time 387217613986 ps
CPU time 410.41 seconds
Started Jul 11 05:48:39 PM PDT 24
Finished Jul 11 05:55:31 PM PDT 24
Peak memory 201800 kb
Host smart-8cc5ad62-414e-4590-90c4-01c3c056593e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841833734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3841833734
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2952750287
Short name T714
Test name
Test status
Simulation time 88754591738 ps
CPU time 439.77 seconds
Started Jul 11 05:49:30 PM PDT 24
Finished Jul 11 05:56:51 PM PDT 24
Peak memory 202208 kb
Host smart-a91d7a95-fb1b-4864-8b2f-1a1333c13997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952750287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2952750287
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.653653329
Short name T654
Test name
Test status
Simulation time 30342885383 ps
CPU time 17.55 seconds
Started Jul 11 05:49:29 PM PDT 24
Finished Jul 11 05:49:48 PM PDT 24
Peak memory 201688 kb
Host smart-829a59b9-799c-4dbc-b454-0630b2eb40fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653653329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.653653329
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4202428811
Short name T524
Test name
Test status
Simulation time 5326024212 ps
CPU time 7.04 seconds
Started Jul 11 05:49:29 PM PDT 24
Finished Jul 11 05:49:37 PM PDT 24
Peak memory 201692 kb
Host smart-c0862975-2d4f-4cf5-a51b-4bfaf80fd8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202428811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4202428811
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3925553581
Short name T622
Test name
Test status
Simulation time 5760704705 ps
CPU time 2.97 seconds
Started Jul 11 05:48:38 PM PDT 24
Finished Jul 11 05:48:43 PM PDT 24
Peak memory 201704 kb
Host smart-e16b2534-38c8-43d9-a962-0a2c3ebda9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925553581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3925553581
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1284547799
Short name T170
Test name
Test status
Simulation time 496842084738 ps
CPU time 1400 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 06:12:07 PM PDT 24
Peak memory 210396 kb
Host smart-2922cbbf-6bdc-4443-8238-d8260a85e5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284547799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1284547799
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2976057191
Short name T551
Test name
Test status
Simulation time 83072356124 ps
CPU time 65.41 seconds
Started Jul 11 05:48:43 PM PDT 24
Finished Jul 11 05:49:51 PM PDT 24
Peak memory 210156 kb
Host smart-b5a9ccdb-9059-49a4-b4a3-578cea05282a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976057191 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2976057191
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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