Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7383	1			T2	61		T3	85		T6	48
testmodes[AdcCtrlTestmodeNormal]	5711	1			T1	3		T2	60		T3	47
testmodes[AdcCtrlTestmodeLowpower]	5880	1			T2	55		T3	35		T6	61
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3956	1			T2	21		T3	53		T6	8
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1853	1			T2	19		T3	17		T6	24
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1452	1			T2	20		T3	15		T6	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1884	1			T2	17		T3	20		T6	23
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2049	1			T1	2		T2	19		T3	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1450	1			T2	24		T3	11		T6	27
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1437	1			T2	23		T3	12		T6	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1464	1			T2	22		T3	14		T6	25
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2730	1			T2	10		T3	9		T6	18