Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23539

1

T1

29

T2

176

T3

164

auto[ADC_CTRL_FILTER_COND_OUT]

3701

1

T3

8

T5

1

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21229

1

T2

176

T3

172

T6

180

auto[1]

6011

1

T1

29

T5

1

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T207	1		-	-		-	-
values[0]	63	1			T208	10		T209	1		T210	23
values[1]	704	1			T3	8		T10	9		T46	10
values[2]	695	1			T39	10		T40	15		T140	1
values[3]	717	1			T5	1		T10	12		T40	28
values[4]	3023	1			T1	29		T8	14		T9	21
values[5]	684	1			T12	11		T39	30		T47	11
values[6]	671	1			T88	14		T31	16		T143	12
values[7]	733	1			T12	22		T28	1		T33	23
values[8]	646	1			T13	1		T40	9		T88	10
values[9]	1276	1			T10	11		T13	2		T28	10
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	961	1			T3	8		T46	10		T140	1
values[1]	733	1			T5	1		T10	9		T39	10
values[2]	610	1			T10	12		T40	28		T88	16
values[3]	3058	1			T1	29		T8	14		T9	21
values[4]	616	1			T12	11		T39	2		T31	24
values[5]	855	1			T88	14		T33	23		T48	9
values[6]	666	1			T12	22		T88	10		T28	1
values[7]	674	1			T10	11		T13	1		T40	9
values[8]	894	1			T13	2		T28	10		T49	13
values[9]	136	1			T163	1		T133	18		T16	4
minimum	18037	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T47	16		T143	1		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	3		T46	3		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	1		T134	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T39	10		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T88	1		T134	1		T153	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T40	13		T169	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T1	3		T8	14		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	13		T141	1		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	1		T146	1		T82	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T39	1		T31	24		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T33	13		T48	5		T37	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T88	1		T143	1		T37	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T211	10		T139	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	1		T88	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	1		T212	1		T142	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	1		T40	5		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	1		T213	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T13	1		T28	1		T49	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T133	11		T83	4		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T163	1		T16	1		T185	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17904	1			T2	176		T3	164		T6	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T143	2		T144	13		T42	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	5		T46	7		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	8		T134	7		T45	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	7		T213	6		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T88	15		T134	10		T153	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	11		T40	15		T169	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T1	26		T9	19		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	15		T153	9		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	10		T82	6		T20	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	1		T144	12		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T33	10		T48	4		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T88	13		T143	11		T184	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T12	7		T211	8		T87	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	13		T88	9		T20	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	10		T138	3		T82	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	4		T48	9		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T213	14		T136	10		T215	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T28	9		T41	1		T56	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T133	7		T216	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T16	3		T185	20		T217	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T207	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T208	10		T209	1		T210	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	1		T47	16		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	3		T46	3		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T141	1		T42	4		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T39	10		T40	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T88	1		T15	7		T134	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T10	1		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T1	3		T8	14		T9	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	2		T143	1		T169	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T47	11		T82	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T39	14		T31	8		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T146	1		T149	12		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T88	1		T31	16		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T33	13		T48	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T28	1		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T142	22		T137	1		T87	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T40	5		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T10	1		T13	1		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T13	1		T28	1		T48	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T210	11		T219	4		T220	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	8		T143	2		T144	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	5		T46	7		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T42	3		T45	5		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	7		T48	12		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T88	15		T15	4		T134	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	11		T40	15		T213	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T1	26		T9	19		T46	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T143	14		T169	16		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	10		T82	6		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	16		T153	9		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T149	11		T151	12		T171	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T88	13		T143	11		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	7		T33	10		T48	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	13		T136	6		T184	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T87	9		T152	11		T221	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	4		T88	9		T151	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	10		T213	14		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T28	9		T48	9		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T47	1		T143	3		T144	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	8		T46	8		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	9		T134	8		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T39	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T88	16		T134	11		T153	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	12		T40	16		T169	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T1	29		T8	1		T9	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T39	16		T141	1		T153	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	11		T146	1		T82	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T39	2		T31	2		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T33	11		T48	5		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T88	14		T143	12		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	8		T211	9		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	14		T88	10		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	11		T212	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T40	5		T48	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T213	15		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T13	1		T28	10		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T133	8		T83	1		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T163	1		T16	4		T185	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18028	1			T2	176		T3	164		T6	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T47	15		T42	2		T148	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	2		T48	12		T133	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T222	10		T223	9		T217	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	9		T40	7		T197	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T153	10		T162	16		T138	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	12		T169	15		T19	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T8	13		T46	2		T47	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	12		T153	8		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T82	6		T20	10		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T31	22		T226	2		T186	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	12		T48	4		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T37	1		T139	9		T20	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T211	9		T139	10		T87	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T142	10		T20	11		T227	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T142	21		T138	3		T82	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	4		T48	13		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T83	12		T215	4		T175	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T49	12		T41	1		T56	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T133	10		T83	3		T217	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T185	14		T217	5		T176	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T208	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T207	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T208	1		T209	1		T210	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	9		T47	1		T143	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	8		T46	8		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T141	1		T42	5		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	1		T40	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T88	16		T15	7		T134	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T10	12		T40	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T1	29		T8	1		T9	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T141	2		T143	15		T169	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	11		T47	1		T82	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	18		T31	1		T153	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T146	1		T149	12		T151	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T88	14		T31	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	8		T33	11		T48	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	14		T28	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T142	1		T137	1		T87	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	1		T40	5		T88	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T10	11		T13	1		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T13	1		T28	10		T48	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T208	9		T210	11		T219	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	15		T148	9		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	2		T133	10		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T42	2		T230	12		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	9		T40	7		T48	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	4		T153	10		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	12		T56	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T8	13		T46	2		T162	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T169	15		T224	7		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	10		T82	6		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	12		T31	7		T153	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T149	11		T151	11		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T31	15		T37	1		T175	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	12		T48	4		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T142	10		T139	9		T20	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T142	21		T87	10		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	4		T151	9		T227	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	3		T133	10		T82	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T48	13		T49	12		T41	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23815

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3425

1

T5

1

T10

12

T12

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20703

1

T2

171

T3

167

T6

165

auto[1]

6537

1

T1

29

T2

5

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	503	1			T2	5		T3	5		T6	15
values[0]	55	1			T221	28		T232	9		T233	8
values[1]	636	1			T3	8		T134	11		T49	13
values[2]	3140	1			T1	29		T8	14		T9	21
values[3]	809	1			T10	12		T12	22		T13	1
values[4]	652	1			T39	2		T46	10		T140	2
values[5]	604	1			T12	11		T39	28		T28	1
values[6]	768	1			T5	1		T10	20		T88	14
values[7]	721	1			T13	1		T40	28		T88	10
values[8]	699	1			T15	11		T31	8		T153	18
values[9]	1095	1			T13	1		T39	10		T40	15
minimum	17558	1			T2	171		T3	159		T6	165

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1011	1			T3	8		T47	16		T134	11
values[1]	3014	1			T1	29		T8	14		T9	21
values[2]	712	1			T12	14		T13	1		T40	9
values[3]	769	1			T10	12		T39	2		T46	10
values[4]	663	1			T5	1		T10	11		T12	11
values[5]	624	1			T10	9		T88	14		T47	11
values[6]	861	1			T13	1		T40	28		T88	10
values[7]	638	1			T13	1		T39	10		T15	11
values[8]	753	1			T40	15		T46	17		T31	16
values[9]	168	1			T48	25		T154	1		T41	2
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T3	3		T47	16		T49	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T134	1		T162	17		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T1	3		T8	14		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T141	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T40	5		T140	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T13	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	1		T46	3		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	1		T137	1		T169	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	1		T12	1		T39	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	1		T28	1		T48	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	1		T88	1		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	11		T143	1		T211	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	1		T88	1		T153	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T40	13		T197	10		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	10		T15	7		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	1		T31	8		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	8		T46	3		T31	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T33	13		T213	2		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T154	1		T155	1		T229	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T48	13		T41	2		T139	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	5		T161	8		T133	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	10		T234	15		T20	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T1	26		T9	19		T88	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	7		T144	12		T235	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	4		T28	9		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	13		T134	7		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	1		T46	7		T48	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	11		T169	16		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	10		T12	10		T39	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	9		T37	2		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	8		T88	13		T42	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	11		T211	8		T144	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T88	9		T153	6		T143	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	15		T197	11		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	4		T41	1		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T153	9		T138	17		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	7		T46	14		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T33	10		T213	20		T234	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T155	7		T229	8		T236	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T48	12		T221	9		T237	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T2	5		T3	5		T6	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T213	1		T221	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T233	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T221	13		T232	7		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	3		T49	13		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T134	1		T162	17		T83	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1662	1			T1	3		T8	14		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T141	1		T163	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	5		T88	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	1		T12	2		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	1		T46	3		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T141	1		T137	1		T169	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T39	13		T56	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	1		T48	14		T37	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	2		T88	1		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T47	11		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T88	1		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T40	13		T143	1		T197	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	7		T143	1		T45	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T31	8		T153	9		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T39	10		T40	8		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T13	1		T33	13		T48	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T2	171		T3	159		T6	165
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T213	14		T221	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T233	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T221	15		T232	2		T238	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	5		T161	8		T133	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T134	10		T234	15		T239	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T1	26		T9	19		T26	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T144	12		T235	12		T20	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	4		T88	15		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	11		T12	20		T134	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	1		T46	7		T48	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T169	16		T16	3		T240	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	10		T39	15		T56	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	9		T37	2		T211	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	18		T88	13		T175	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T42	1		T82	6		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T88	9		T153	6		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T40	15		T143	11		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	4		T143	2		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T153	9		T136	10		T138	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T40	7		T46	14		T161	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	10		T48	12		T213	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4