Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23946

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3294

1

T5

1

T10

32

T12

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21342

1

T2

176

T3

164

T6

180

auto[1]

5898

1

T1

29

T3

8

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	70	1			T235	15		T269	35		T306	13
values[0]	48	1			T47	11		T37	6		T166	12
values[1]	549	1			T10	11		T33	23		T161	9
values[2]	2957	1			T1	29		T8	14		T9	21
values[3]	875	1			T47	16		T28	10		T48	9
values[4]	681	1			T3	8		T10	9		T12	19
values[5]	765	1			T5	1		T12	14		T140	2
values[6]	796	1			T39	28		T15	11		T142	22
values[7]	684	1			T13	1		T48	25		T161	12
values[8]	687	1			T13	1		T39	12		T40	28
values[9]	1101	1			T10	12		T40	15		T28	1
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	719	1			T10	11		T88	14		T47	11
values[1]	3043	1			T1	29		T8	14		T9	21
values[2]	808	1			T3	8		T47	16		T48	9
values[3]	777	1			T10	9		T12	19		T40	9
values[4]	745	1			T5	1		T12	14		T39	28
values[5]	734	1			T142	22		T137	1		T211	18
values[6]	834	1			T39	2		T15	11		T48	25
values[7]	427	1			T10	12		T13	1		T40	28
values[8]	897	1			T13	1		T39	10		T40	15
values[9]	208	1			T143	3		T184	6		T228	21
minimum	18048	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T88	1		T33	13		T37	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	1		T47	11		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T1	3		T8	14		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	1		T41	2		T83	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	3		T47	16		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	5		T134	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T40	5		T31	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	1		T12	1		T88	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T140	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T39	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T211	10		T144	1		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T142	22		T137	1		T42	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T161	1		T144	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T39	1		T15	7		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T141	1		T163	1		T138	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T10	1		T13	1		T40	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	10		T134	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	1		T40	8		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T184	1		T228	21		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T143	1		T18	3		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T154	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T88	13		T33	10		T37	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	10		T161	8		T16	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T1	26		T9	19		T46	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T143	14		T229	8		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	5		T17	4		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	4		T134	7		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	7		T40	4		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	8		T12	10		T88	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	13		T134	10		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	15		T213	14		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T211	8		T144	13		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T42	3		T56	11		T239	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T161	11		T144	12		T234	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	1		T15	4		T48	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T138	3		T165	7		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	11		T40	15		T46	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T134	7		T153	6		T87	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T40	7		T138	14		T184	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T184	5		T221	9		T269	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T143	2		T18	3		T243	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	1		T32	1		T37	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T235	1		T269	18		T298	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T306	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T37	4		T166	12		T308	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T47	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	13		T137	1		T41	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	1		T161	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1646	1			T1	3		T8	14		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T143	1		T41	2		T229	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T47	16		T28	1		T212	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T48	5		T141	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	3		T12	1		T40	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	1		T12	1		T88	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T140	1		T31	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T140	1		T48	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T197	10		T211	10		T139	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T39	13		T15	7		T142	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T161	1		T144	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	1		T48	13		T37	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	10		T141	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	1		T39	1		T40	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T134	1		T153	11		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T10	1		T40	8		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T235	14		T269	17		T298	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T37	2		T237	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T33	10		T41	1		T170	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	10		T161	8		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T1	26		T9	19		T88	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T143	14		T229	8		T152	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	9		T17	4		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T48	4		T136	6		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	5		T12	7		T40	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	8		T12	10		T88	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	13		T134	10		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T48	9		T213	14		T138	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T197	11		T211	8		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T39	15		T15	4		T56	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T161	11		T144	13		T234	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T48	12		T42	3		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	3		T144	12		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T39	1		T40	15		T46	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T134	7		T153	6		T184	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T10	11		T40	7		T143	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T88	14		T33	11		T37	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	11		T47	1		T161	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T1	29		T8	1		T9	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T143	15		T41	2		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	8		T47	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T48	5		T134	8		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	8		T40	5		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	9		T12	11		T88	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	14		T140	1		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T39	16		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T211	9		T144	14		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T142	1		T137	1		T42	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T161	12		T144	13		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T39	2		T15	7		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T141	1		T163	1		T138	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	12		T13	1		T40	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T39	1		T134	8		T153	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	1		T40	8		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T184	6		T228	1		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T143	3		T18	6		T243	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18034	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T154	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	12		T41	1		T133	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	10		T157	15		T223	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T8	13		T46	2		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T83	3		T229	8		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T47	15		T17	4		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T48	4		T142	10		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T40	4		T31	15		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	13		T49	12		T83	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T153	8		T197	9		T169	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	12		T162	16		T138	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T211	9		T45	2		T185	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T142	21		T42	2		T56	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T185	5		T151	11		T215	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	4		T48	12		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T138	3		T250	5		T257	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T40	12		T46	2		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T39	9		T153	10		T87	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	7		T245	14		T175	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T228	20		T221	9		T269	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T208	9		T306	12		T309	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T166	11		T237	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T235	15		T269	18		T298	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T37	6		T166	1		T308	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T47	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T33	11		T137	1		T41	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	11		T161	9		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T1	29		T8	1		T9	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T143	15		T41	2		T229	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T47	1		T28	10		T212	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T48	5		T141	1		T136	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	8		T12	8		T40	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	9		T12	11		T88	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	14		T140	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	1		T140	1		T48	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T197	12		T211	9		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	16		T15	7		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T161	12		T144	14		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T48	13		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	1		T141	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T39	2		T40	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T134	8		T153	7		T184	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T10	12		T40	8		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T269	17		T298	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T306	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T166	11		T308	10		T237	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T47	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T33	12		T41	1		T171	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T157	15		T223	9		T225	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T8	13		T46	2		T241	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T229	8		T175	12		T172	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T47	15		T17	4		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	4		T139	10		T83	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	4		T228	7		T20	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T49	12		T142	10		T83	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T31	15		T153	8		T169	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	13		T138	12		T41	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T197	9		T211	9		T139	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T39	12		T15	4		T142	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T45	2		T185	9		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T48	12		T37	1		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	9		T138	3		T185	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	12		T46	2		T56	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T153	10		T87	10		T149	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	7		T31	7		T245	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23