Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23539

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3701

1

T5

1

T10

23

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21270

1

T2

176

T3

164

T5

1

auto[1]

5970

1

T1

29

T3

8

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	284	1			T39	2		T88	14		T141	1
values[0]	11	1			T255	1		T267	2		T273	8
values[1]	597	1			T13	1		T39	28		T140	1
values[2]	653	1			T12	11		T15	11		T28	1
values[3]	795	1			T46	17		T48	23		T134	8
values[4]	672	1			T5	1		T12	14		T28	10
values[5]	755	1			T39	10		T33	23		T212	1
values[6]	734	1			T10	23		T13	1		T40	43
values[7]	695	1			T143	12		T136	11		T137	1
values[8]	635	1			T13	1		T140	1		T48	25
values[9]	3382	1			T1	29		T3	8		T8	14
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	459	1			T13	1		T39	28		T140	1
values[1]	774	1			T12	11		T15	11		T28	1
values[2]	781	1			T5	1		T46	17		T31	8
values[3]	731	1			T12	14		T28	10		T141	1
values[4]	648	1			T39	10		T88	10		T33	23
values[5]	863	1			T10	23		T13	1		T40	43
values[6]	2957	1			T1	29		T8	14		T9	21
values[7]	663	1			T13	1		T140	1		T213	7
values[8]	982	1			T3	8		T10	9		T12	8
values[9]	153	1			T88	14		T171	21		T245	15
minimum	18229	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T140	1		T47	11		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	1		T39	13		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T15	7		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T28	1		T143	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T31	8		T48	14		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T46	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T141	1		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T28	1		T161	1		T37	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T39	10		T134	1		T142	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T88	1		T33	13		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T40	8		T136	1		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	2		T13	1		T40	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T1	3		T8	14		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T48	13		T137	1		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T213	1		T136	1		T138	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T140	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	3		T10	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T88	1		T47	16		T48	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T194	1		T217	9		T107	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T88	1		T171	11		T245	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17931	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T255	1		T263	1		T172	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T185	11		T248	4		T250	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T39	15		T37	2		T169	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	10		T15	4		T134	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T143	14		T41	4		T133	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	9		T161	11		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	14		T134	7		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	13		T153	9		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T28	9		T161	8		T138	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T134	10		T155	7		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T88	9		T33	10		T82	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	7		T136	10		T82	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T10	21		T40	15		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T1	26		T9	19		T26	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T48	12		T41	1		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T213	6		T136	6		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T153	6		T184	15		T87	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	5		T10	8		T12	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T88	15		T48	4		T138	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T194	7		T217	8		T107	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T88	13		T171	10		T310	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T263	2		T172	11		T105	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T39	1		T213	1		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T88	1		T141	1		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T273	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T255	1		T267	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T140	1		T47	11		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	1		T39	13		T37	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	1		T15	7		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T28	1		T143	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	14		T197	10		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T46	3		T134	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T31	8		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	1		T28	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T39	10		T134	1		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T33	13		T212	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	8		T82	8		T83	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	2		T13	1		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T143	1		T136	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T137	1		T41	2		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T136	1		T138	13		T56	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	1		T140	1		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1741	1			T1	3		T3	3		T8	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T88	1		T47	16		T48	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T39	1		T213	14		T194	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T88	13		T144	14		T171	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T267	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T185	11		T243	16		T248	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	15		T37	2		T169	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T12	10		T15	4		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T143	14		T41	4		T133	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	9		T197	11		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	14		T134	7		T143	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	13		T161	11		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	9		T161	8		T138	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T134	10		T153	9		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T33	10		T82	6		T269	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	7		T82	5		T18	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	21		T40	15		T88	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T143	11		T136	10		T184	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	1		T151	12		T270	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T136	6		T138	5		T56	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T48	12		T184	15		T87	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T1	26		T3	5		T9	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T88	15		T48	4		T153	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T140	1		T47	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T39	16		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	11		T15	7		T134	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T28	1		T143	15		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T31	1		T48	10		T161	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T46	15		T134	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	14		T141	1		T153	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T28	10		T161	9		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T39	1		T134	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T88	10		T33	11		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	8		T136	11		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T10	23		T13	1		T40	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T1	29		T8	1		T9	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T48	13		T137	1		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T213	7		T136	7		T138	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	1		T140	1		T153	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T3	8		T10	9		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T88	16		T47	1		T48	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T194	8		T217	9		T107	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T88	14		T171	11		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18065	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T255	1		T263	3		T172	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T47	10		T185	5		T248	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	12		T169	15		T157	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T15	4		T211	9		T139	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T41	5		T133	10		T56	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T31	7		T48	13		T197	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	2		T133	10		T83	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T153	8		T20	11		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	1		T138	3		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T39	9		T142	21		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T33	12		T142	10		T82	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	7		T82	7		T83	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	12		T49	12		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T8	13		T241	9		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	12		T41	1		T150	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T138	12		T56	11		T139	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T153	10		T162	16		T87	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	4		T46	2		T31	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T47	15		T48	4		T149	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T217	8		T107	7		T311	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T171	10		T245	14		T312	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T243	13		T313	1		T314	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T172	10		T92	11		T105	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T39	2		T213	15		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T88	14		T141	1		T144	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T273	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T255	1		T267	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T140	1		T47	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	1		T39	16		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	11		T15	7		T134	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T28	1		T143	15		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	10		T197	12		T211	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T46	15		T134	8		T143	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	14		T31	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T28	10		T161	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T39	1		T134	11		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T33	11		T212	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T40	8		T82	6		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	23		T13	1		T40	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T143	12		T136	11		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T137	1		T41	2		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	7		T138	6		T56	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T13	1		T140	1		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T1	29		T3	8		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T88	16		T47	1		T48	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T240	11		T92	6		T315	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T171	10		T245	14		T312	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T273	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T47	10		T185	5		T243	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T39	12		T169	15		T157	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T15	4		T139	5		T215	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T41	5		T133	10		T56	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	13		T197	9		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	2		T133	10		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T31	7		T226	2		T20	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	1		T138	3		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T39	9		T153	8		T142	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T33	12		T142	10		T82	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	7		T82	7		T83	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	12		T49	12		T185	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	9		T20	10		T175	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T41	1		T148	9		T150	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T138	12		T56	11		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	12		T162	16		T87	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T8	13		T40	4		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	15		T48	4		T153	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23