Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21158

1

T2

176

T3

164

T6

180

auto[ADC_CTRL_FILTER_COND_OUT]

6082

1

T1

29

T3

8

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21110

1

T2

176

T3

164

T5

1

auto[1]

6130

1

T1

29

T3

8

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	372	1			T47	11		T138	15		T169	32
values[0]	20	1			T290	19		T294	1		-	-
values[1]	620	1			T12	11		T13	1		T88	16
values[2]	843	1			T33	23		T48	23		T49	13
values[3]	721	1			T3	8		T12	8		T13	1
values[4]	529	1			T12	14		T48	25		T161	9
values[5]	615	1			T5	1		T46	17		T15	11
values[6]	563	1			T13	1		T88	14		T47	16
values[7]	739	1			T10	21		T140	1		T31	8
values[8]	904	1			T10	11		T40	15		T134	11
values[9]	3287	1			T1	29		T8	14		T9	21
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	719	1			T12	11		T88	16		T28	10
values[1]	3140	1			T1	29		T8	14		T9	21
values[2]	723	1			T3	8		T12	8		T13	1
values[3]	586	1			T5	1		T12	14		T40	9
values[4]	622	1			T15	11		T153	18		T161	12
values[5]	624	1			T13	1		T88	14		T47	16
values[6]	822	1			T10	21		T140	1		T162	17
values[7]	780	1			T10	11		T39	10		T40	43
values[8]	889	1			T142	22		T135	1		T163	1
values[9]	191	1			T88	10		T47	11		T138	15
minimum	18144	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	1		T28	1		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T88	1		T31	16		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	14		T154	1		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1632	1			T1	3		T8	14		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	1		T87	11		T228	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	3		T12	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T28	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	1		T40	5		T46	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	1		T42	4		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	7		T153	9		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T88	1		T47	16		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	1		T31	8		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	2		T140	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T162	17		T155	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T39	10		T40	13		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	1		T40	8		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T142	22		T163	1		T138	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T135	1		T41	2		T42	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T47	11		T169	16		T139	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T88	1		T138	1		T296	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17930	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T140	1		T164	1		T209	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	10		T28	9		T48	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T88	15		T153	6		T143	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	9		T223	10		T22	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1130	1			T1	26		T9	19		T26	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T87	9		T316	6		T257	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	5		T12	7		T39	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	13		T134	7		T161	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	4		T46	14		T48	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T42	3		T170	11		T243	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	4		T153	9		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T88	13		T134	7		T213	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T138	3		T133	12		T16	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	19		T144	14		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T155	10		T149	9		T226	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	15		T134	10		T155	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	10		T40	7		T143	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T138	5		T56	14		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	1		T42	1		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T169	16		T317	2		T289	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T88	9		T138	14		T296	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T164	7		T290	8		T237	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T47	11		T169	16		T56	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T138	1		T172	4		T296	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T294	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T290	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T13	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T88	1		T140	1		T31	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	14		T141	1		T37	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T33	13		T49	13		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T154	1		T228	21		T150	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	3		T12	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T161	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	13		T184	1		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	1		T134	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T46	3		T15	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T88	1		T47	16		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	1		T153	9		T138	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	2		T140	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T31	8		T162	17		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T134	1		T146	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T10	1		T40	8		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T39	10		T40	13		T142	33
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1697	1			T1	3		T8	14		T9	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T169	16		T56	14		T195	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T138	14		T172	6		T296	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T290	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	10		T28	9		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T88	15		T143	16		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	9		T194	7		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T33	10		T213	14		T153	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T95	12		T316	6		T257	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	5		T12	7		T39	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	13		T161	8		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	12		T184	5		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T134	7		T42	3		T170	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	14		T15	4		T161	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T88	13		T213	6		T56	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T153	9		T138	3		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	19		T134	7		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T155	10		T149	9		T226	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T134	10		T155	7		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	10		T40	7		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	15		T138	5		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1137	1			T1	26		T9	19		T88	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	11		T28	10		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T88	16		T31	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T48	10		T154	1		T37	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1475	1			T1	29		T8	1		T9	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	1		T87	10		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	8		T12	8		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	14		T28	1		T134	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	1		T40	5		T46	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T137	1		T42	5		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T15	7		T153	10		T161	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T88	14		T47	1		T134	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T31	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T10	21		T140	1		T144	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T162	1		T155	11		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T39	1		T40	16		T134	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	11		T40	8		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T142	1		T163	1		T138	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T135	1		T41	2		T42	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T47	1		T169	17		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T88	10		T138	15		T296	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18073	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T140	1		T164	8		T209	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T48	4		T151	9		T186	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	15		T153	10		T41	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	13		T37	1		T223	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1287	1			T8	13		T33	12		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T87	10		T228	20		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	12		T46	2		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T82	6		T215	6		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T40	4		T46	2		T48	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	2		T228	7		T248	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	4		T153	8		T234	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T47	15		T56	11		T82	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T31	7		T138	3		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T139	9		T229	8		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T162	16		T149	7		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	9		T40	12		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	7		T83	3		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T142	21		T138	12		T56	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	1		T83	12		T175	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T47	10		T169	15		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T296	1		T297	17		T318	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T319	2		T61	3		T320	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T292	11		T290	10		T237	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T47	1		T169	17		T56	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T138	15		T172	7		T296	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T294	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T290	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	11		T13	1		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T88	16		T140	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	10		T141	1		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T33	11		T49	1		T213	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T154	1		T228	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	8		T12	8		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	14		T161	9		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	13		T184	6		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T28	1		T134	8		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T46	15		T15	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T88	14		T47	1		T213	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	1		T153	10		T138	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T10	21		T140	1		T134	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	1		T162	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T134	11		T146	1		T155	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T10	11		T40	8		T143	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T39	1		T40	16		T142	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1503	1			T1	29		T8	1		T9	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T47	10		T169	15		T56	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T172	3		T296	1		T321	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T290	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	4		T151	9		T186	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T31	15		T292	11		T322	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	13		T37	1		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T33	12		T49	12		T153	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T228	20		T150	16		T295	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	12		T40	4		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T82	6		T87	10		T215	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T48	12		T149	11		T171	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T42	2		T228	7		T248	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	2		T15	4		T197	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T47	15		T56	11		T82	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T153	8		T138	3		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	4		T45	2		T185	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	7		T162	16		T149	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T139	9		T229	8		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T40	7		T83	3		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	9		T40	12		T142	31
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1331	1			T8	13		T241	9		T242	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23