Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23749

1

T1

29

T2

176

T3

164

auto[ADC_CTRL_FILTER_COND_OUT]

3491

1

T3

8

T10

23

T12

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20806

1

T2

176

T3

172

T6

180

auto[1]

6434

1

T1

29

T5

1

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	289	1			T162	17		T136	7		T218	1
values[0]	24	1			T41	2		T243	2		T266	1
values[1]	660	1			T140	2		T47	11		T28	10
values[2]	783	1			T13	1		T88	16		T143	3
values[3]	720	1			T10	11		T13	1		T88	14
values[4]	628	1			T40	28		T31	16		T134	11
values[5]	2981	1			T1	29		T8	14		T9	21
values[6]	759	1			T12	11		T39	2		T40	9
values[7]	777	1			T10	9		T12	14		T88	10
values[8]	490	1			T3	8		T39	28		T48	25
values[9]	1102	1			T5	1		T10	12		T40	15
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	552	1			T140	2		T33	23		T48	9
values[1]	857	1			T13	1		T88	30		T31	8
values[2]	600	1			T10	11		T13	1		T15	11
values[3]	3069	1			T1	29		T8	14		T9	21
values[4]	647	1			T13	1		T39	10		T46	10
values[5]	759	1			T12	11		T39	2		T40	9
values[6]	690	1			T10	9		T12	14		T39	28
values[7]	405	1			T3	8		T48	25		T153	18
values[8]	1131	1			T5	1		T10	12		T28	1
values[9]	186	1			T40	15		T133	23		T151	15
minimum	18344	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	1		T33	13		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T140	1		T154	1		T133	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T88	1		T31	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T88	1		T213	1		T139	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	7		T31	16		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T13	1		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T1	3		T8	14		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T40	13		T142	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	3		T47	16		T49	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T39	10		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T39	1		T46	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	5		T141	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	1		T141	1		T142	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	1		T39	13		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	9		T255	1		T186	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T3	3		T48	13		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	1		T28	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T10	1		T212	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T40	8		T151	10		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T133	11		T239	2		T315	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T47	11		T138	1		T41	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	10		T48	4		T197	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T133	7		T17	4		T185	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T88	15		T143	2		T37	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T88	13		T213	14		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	4		T161	11		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	10		T42	1		T243	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T1	26		T9	19		T26	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	7		T40	15		T169	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	7		T138	3		T155	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T143	11		T16	3		T87	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	10		T39	1		T46	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	4		T41	4		T82	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	8		T149	9		T171	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	13		T39	15		T88	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T153	9		T248	4		T270	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T3	5		T48	12		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T213	6		T161	8		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T10	11		T134	7		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T40	7		T151	5		T282	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T133	12		T239	2		T315	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T15	1		T28	9		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T138	14		T276	8		T323	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T162	17		T218	1		T174	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T136	1		T56	12		T231	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T243	1		T266	1		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T41	2		T276	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T140	1		T28	1		T33	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T140	1		T47	11		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	1		T88	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T133	11		T139	21		T83	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	7		T31	8		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T13	1		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	16		T134	1		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T40	13		T142	11		T169	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T1	3		T8	14		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T13	1		T39	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T39	1		T46	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T40	5		T141	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	1		T142	22		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T88	1		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	1		T153	9		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	3		T39	13		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	1		T40	8		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T10	1		T134	1		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T225	13		T282	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T136	6		T56	11		T324	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T243	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T276	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T28	9		T33	10		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T138	14		T17	4		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T88	15		T143	2		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T133	7		T234	15		T185	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	4		T161	11		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	10		T88	13		T213	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T134	10		T153	6		T184	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	15		T169	16		T224	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T1	26		T9	19		T26	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	7		T16	3		T87	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	10		T39	1		T46	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	4		T143	11		T41	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	8		T149	20		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	13		T88	9		T48	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T153	9		T247	1		T248	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	5		T39	15		T48	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T40	7		T213	6		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	11		T134	7		T144	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T140	1		T33	11		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T140	1		T154	1		T133	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	1		T88	16		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T88	14		T213	15		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	7		T31	1		T161	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	11		T13	1		T42	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T1	29		T8	1		T9	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	8		T40	16		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	8		T47	1		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	1		T39	1		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	11		T39	2		T46	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	5		T141	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	9		T141	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	14		T39	16		T88	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T153	10		T255	1		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	8		T48	13		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	1		T28	1		T213	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T10	12		T212	1		T134	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T40	8		T151	6		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T133	13		T239	4		T315	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18138	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T47	1		T138	15		T41	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T33	12		T48	4		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T133	10		T17	4		T185	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T31	7		T211	9		T249	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T139	19		T83	12		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	4		T31	15		T56	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T243	13		T287	9		T221	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T8	13		T153	10		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	12		T142	10		T169	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T46	2		T47	15		T49	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	9		T139	5		T87	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T46	2		T138	12		T229	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	4		T41	5		T82	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T142	21		T149	7		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	12		T48	13		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T153	8		T186	5		T248	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T48	12		T42	2		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T162	16		T185	5		T245	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T56	11		T228	7		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T40	7		T151	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T133	10		T315	9		T285	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T215	6		T244	14		T187	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T47	10		T228	20		T276	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T162	1		T218	1		T174	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T136	7		T56	12		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T243	2		T266	1		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T41	2		T276	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T140	1		T28	10		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T140	1		T47	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	1		T88	16		T143	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T133	8		T139	2		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	7		T31	1		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	11		T13	1		T88	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	1		T134	11		T153	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	16		T142	1		T169	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T1	29		T8	1		T9	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	8		T13	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	11		T39	2		T46	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	5		T141	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	9		T142	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	14		T88	10		T48	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T141	1		T153	10		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	8		T39	16		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T5	1		T40	8		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T10	12		T134	8		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T162	16		T225	1		T318	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T56	11		T231	10		T324	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T33	12		T48	4		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T47	10		T17	4		T228	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T197	9		T37	1		T211	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T133	10		T139	19		T83	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	4		T31	7		T250	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T243	13		T287	9		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	15		T153	10		T56	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	12		T142	10		T169	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T8	13		T49	12		T241	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	9		T87	10		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T46	4		T47	15		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	4		T41	5		T139	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T142	21		T149	18		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	13		T82	7		T186	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T153	8		T247	1		T186	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T39	12		T48	12		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	7		T185	5		T151	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T133	10		T228	7		T151	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23