interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
159 |
1 |
|
|
T88 |
1 |
|
T33 |
13 |
|
T37 |
4 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
134 |
1 |
|
|
T10 |
1 |
|
T47 |
11 |
|
T137 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1651 |
1 |
|
|
T1 |
3 |
|
T8 |
14 |
|
T9 |
2 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
131 |
1 |
|
|
T143 |
1 |
|
T41 |
2 |
|
T83 |
4 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
269 |
1 |
|
|
T3 |
3 |
|
T47 |
16 |
|
T28 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
189 |
1 |
|
|
T48 |
5 |
|
T134 |
1 |
|
T141 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
208 |
1 |
|
|
T12 |
1 |
|
T40 |
5 |
|
T31 |
16 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
214 |
1 |
|
|
T10 |
1 |
|
T12 |
1 |
|
T88 |
2 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
186 |
1 |
|
|
T12 |
1 |
|
T140 |
1 |
|
T134 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
197 |
1 |
|
|
T5 |
1 |
|
T140 |
1 |
|
T213 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
241 |
1 |
|
|
T211 |
10 |
|
T144 |
1 |
|
T170 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
232 |
1 |
|
|
T39 |
13 |
|
T142 |
22 |
|
T137 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
234 |
1 |
|
|
T161 |
1 |
|
T144 |
1 |
|
T156 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
192 |
1 |
|
|
T39 |
1 |
|
T15 |
7 |
|
T48 |
13 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
107 |
1 |
|
|
T141 |
1 |
|
T163 |
1 |
|
T138 |
4 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
128 |
1 |
|
|
T10 |
1 |
|
T13 |
1 |
|
T40 |
13 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
279 |
1 |
|
|
T39 |
10 |
|
T134 |
1 |
|
T153 |
11 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
251 |
1 |
|
|
T13 |
1 |
|
T40 |
8 |
|
T143 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
64 |
1 |
|
|
T184 |
1 |
|
T228 |
21 |
|
T269 |
18 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
34 |
1 |
|
|
T208 |
10 |
|
T306 |
13 |
|
T325 |
1 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17934 |
1 |
|
|
T2 |
176 |
|
T3 |
164 |
|
T6 |
180 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
54 |
1 |
|
|
T161 |
1 |
|
T154 |
1 |
|
T163 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
131 |
1 |
|
|
T88 |
13 |
|
T33 |
10 |
|
T37 |
2 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
107 |
1 |
|
|
T10 |
10 |
|
T16 |
3 |
|
T157 |
11 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1114 |
1 |
|
|
T1 |
26 |
|
T9 |
19 |
|
T46 |
14 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
146 |
1 |
|
|
T143 |
14 |
|
T229 |
8 |
|
T234 |
15 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
180 |
1 |
|
|
T3 |
5 |
|
T28 |
9 |
|
T17 |
4 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
171 |
1 |
|
|
T48 |
4 |
|
T134 |
7 |
|
T136 |
6 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
152 |
1 |
|
|
T12 |
7 |
|
T40 |
4 |
|
T143 |
11 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
204 |
1 |
|
|
T10 |
8 |
|
T12 |
10 |
|
T88 |
24 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
140 |
1 |
|
|
T12 |
13 |
|
T134 |
10 |
|
T153 |
9 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
191 |
1 |
|
|
T213 |
14 |
|
T138 |
5 |
|
T41 |
4 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
226 |
1 |
|
|
T211 |
8 |
|
T144 |
13 |
|
T170 |
11 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
112 |
1 |
|
|
T39 |
15 |
|
T42 |
3 |
|
T56 |
11 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
199 |
1 |
|
|
T161 |
11 |
|
T144 |
12 |
|
T234 |
1 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
171 |
1 |
|
|
T39 |
1 |
|
T15 |
4 |
|
T48 |
12 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
78 |
1 |
|
|
T138 |
3 |
|
T165 |
7 |
|
T250 |
2 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
130 |
1 |
|
|
T10 |
11 |
|
T40 |
15 |
|
T46 |
7 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
222 |
1 |
|
|
T134 |
7 |
|
T153 |
6 |
|
T87 |
9 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
205 |
1 |
|
|
T40 |
7 |
|
T143 |
2 |
|
T138 |
14 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
31 |
1 |
|
|
T184 |
5 |
|
T269 |
17 |
|
T24 |
1 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
5 |
1 |
|
|
T309 |
4 |
|
T232 |
1 |
|
- |
- |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
145 |
1 |
|
|
T15 |
1 |
|
T32 |
1 |
|
T37 |
4 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
92 |
1 |
|
|
T161 |
8 |
|
T155 |
10 |
|
T225 |
13 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
41 |
1 |
|
|
T87 |
11 |
|
T149 |
8 |
|
T303 |
1 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
56 |
1 |
|
|
T135 |
1 |
|
T174 |
1 |
|
T221 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
23 |
1 |
|
|
T166 |
12 |
|
T308 |
11 |
|
- |
- |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
13 |
1 |
|
|
T47 |
11 |
|
T225 |
2 |
|
- |
- |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
123 |
1 |
|
|
T33 |
13 |
|
T37 |
4 |
|
T137 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
124 |
1 |
|
|
T10 |
1 |
|
T161 |
1 |
|
T154 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1644 |
1 |
|
|
T1 |
3 |
|
T8 |
14 |
|
T9 |
2 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
107 |
1 |
|
|
T143 |
1 |
|
T137 |
1 |
|
T41 |
2 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
271 |
1 |
|
|
T47 |
16 |
|
T28 |
1 |
|
T141 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
233 |
1 |
|
|
T48 |
5 |
|
T141 |
1 |
|
T136 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
229 |
1 |
|
|
T3 |
3 |
|
T12 |
1 |
|
T40 |
5 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
155 |
1 |
|
|
T10 |
1 |
|
T12 |
1 |
|
T88 |
2 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
172 |
1 |
|
|
T12 |
1 |
|
T140 |
1 |
|
T134 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
195 |
1 |
|
|
T5 |
1 |
|
T140 |
1 |
|
T48 |
14 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
237 |
1 |
|
|
T197 |
10 |
|
T211 |
10 |
|
T139 |
6 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
288 |
1 |
|
|
T39 |
13 |
|
T142 |
22 |
|
T162 |
17 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
211 |
1 |
|
|
T161 |
1 |
|
T144 |
2 |
|
T156 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
150 |
1 |
|
|
T15 |
7 |
|
T48 |
13 |
|
T37 |
4 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
166 |
1 |
|
|
T39 |
10 |
|
T141 |
1 |
|
T163 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
206 |
1 |
|
|
T13 |
1 |
|
T39 |
1 |
|
T40 |
13 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
321 |
1 |
|
|
T134 |
1 |
|
T153 |
11 |
|
T184 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
229 |
1 |
|
|
T10 |
1 |
|
T13 |
1 |
|
T40 |
8 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17894 |
1 |
|
|
T2 |
176 |
|
T3 |
164 |
|
T6 |
180 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
55 |
1 |
|
|
T87 |
9 |
|
T149 |
9 |
|
T303 |
12 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
25 |
1 |
|
|
T293 |
2 |
|
T309 |
4 |
|
T267 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
13 |
1 |
|
|
T225 |
13 |
|
- |
- |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
112 |
1 |
|
|
T33 |
10 |
|
T37 |
2 |
|
T41 |
1 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
152 |
1 |
|
|
T10 |
10 |
|
T161 |
8 |
|
T16 |
3 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1097 |
1 |
|
|
T1 |
26 |
|
T9 |
19 |
|
T88 |
13 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
115 |
1 |
|
|
T143 |
14 |
|
T229 |
8 |
|
T152 |
11 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
193 |
1 |
|
|
T28 |
9 |
|
T17 |
4 |
|
T149 |
11 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
227 |
1 |
|
|
T48 |
4 |
|
T136 |
6 |
|
T234 |
15 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
165 |
1 |
|
|
T3 |
5 |
|
T12 |
7 |
|
T40 |
4 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
145 |
1 |
|
|
T10 |
8 |
|
T12 |
10 |
|
T88 |
24 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
141 |
1 |
|
|
T12 |
13 |
|
T134 |
10 |
|
T153 |
9 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
194 |
1 |
|
|
T48 |
9 |
|
T213 |
14 |
|
T138 |
5 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
175 |
1 |
|
|
T197 |
11 |
|
T211 |
8 |
|
T226 |
11 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
130 |
1 |
|
|
T39 |
15 |
|
T56 |
11 |
|
T171 |
10 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
204 |
1 |
|
|
T161 |
11 |
|
T144 |
25 |
|
T234 |
1 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
137 |
1 |
|
|
T15 |
4 |
|
T48 |
12 |
|
T136 |
10 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
134 |
1 |
|
|
T138 |
3 |
|
T165 |
7 |
|
T222 |
13 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
179 |
1 |
|
|
T39 |
1 |
|
T40 |
15 |
|
T46 |
7 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
209 |
1 |
|
|
T134 |
7 |
|
T153 |
6 |
|
T184 |
5 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
217 |
1 |
|
|
T10 |
11 |
|
T40 |
7 |
|
T143 |
2 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
133 |
1 |
|
|
T15 |
1 |
|
T32 |
1 |
|
T37 |
4 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
173 |
1 |
|
|
T88 |
14 |
|
T33 |
11 |
|
T37 |
6 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
128 |
1 |
|
|
T10 |
11 |
|
T47 |
1 |
|
T137 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1469 |
1 |
|
|
T1 |
29 |
|
T8 |
1 |
|
T9 |
21 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
177 |
1 |
|
|
T143 |
15 |
|
T41 |
2 |
|
T83 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
229 |
1 |
|
|
T3 |
8 |
|
T47 |
1 |
|
T28 |
10 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
212 |
1 |
|
|
T48 |
5 |
|
T134 |
8 |
|
T141 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
191 |
1 |
|
|
T12 |
8 |
|
T40 |
5 |
|
T31 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
246 |
1 |
|
|
T10 |
9 |
|
T12 |
11 |
|
T88 |
26 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
173 |
1 |
|
|
T12 |
14 |
|
T140 |
1 |
|
T134 |
11 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
236 |
1 |
|
|
T5 |
1 |
|
T140 |
1 |
|
T213 |
15 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
270 |
1 |
|
|
T211 |
9 |
|
T144 |
14 |
|
T170 |
12 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
146 |
1 |
|
|
T39 |
16 |
|
T142 |
1 |
|
T137 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
250 |
1 |
|
|
T161 |
12 |
|
T144 |
13 |
|
T156 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
218 |
1 |
|
|
T39 |
2 |
|
T15 |
7 |
|
T48 |
13 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
108 |
1 |
|
|
T141 |
1 |
|
T163 |
1 |
|
T138 |
4 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
161 |
1 |
|
|
T10 |
12 |
|
T13 |
1 |
|
T40 |
16 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
269 |
1 |
|
|
T39 |
1 |
|
T134 |
8 |
|
T153 |
7 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
265 |
1 |
|
|
T13 |
1 |
|
T40 |
8 |
|
T143 |
3 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
43 |
1 |
|
|
T184 |
6 |
|
T228 |
1 |
|
T269 |
18 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
10 |
1 |
|
|
T208 |
1 |
|
T306 |
1 |
|
T325 |
1 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
18049 |
1 |
|
|
T2 |
176 |
|
T3 |
164 |
|
T6 |
180 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
103 |
1 |
|
|
T161 |
9 |
|
T154 |
1 |
|
T163 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
117 |
1 |
|
|
T33 |
12 |
|
T41 |
1 |
|
T150 |
16 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
113 |
1 |
|
|
T47 |
10 |
|
T157 |
15 |
|
T175 |
12 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1296 |
1 |
|
|
T8 |
13 |
|
T46 |
2 |
|
T241 |
9 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
100 |
1 |
|
|
T83 |
3 |
|
T229 |
8 |
|
T234 |
16 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
220 |
1 |
|
|
T47 |
15 |
|
T17 |
4 |
|
T149 |
11 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
148 |
1 |
|
|
T48 |
4 |
|
T142 |
10 |
|
T139 |
10 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
169 |
1 |
|
|
T40 |
4 |
|
T31 |
15 |
|
T228 |
7 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
172 |
1 |
|
|
T48 |
13 |
|
T49 |
12 |
|
T83 |
12 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
153 |
1 |
|
|
T153 |
8 |
|
T197 |
9 |
|
T169 |
15 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
152 |
1 |
|
|
T162 |
16 |
|
T138 |
12 |
|
T41 |
5 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
197 |
1 |
|
|
T211 |
9 |
|
T185 |
9 |
|
T20 |
2 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
198 |
1 |
|
|
T39 |
12 |
|
T142 |
21 |
|
T42 |
2 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
183 |
1 |
|
|
T45 |
2 |
|
T185 |
5 |
|
T151 |
11 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
145 |
1 |
|
|
T15 |
4 |
|
T48 |
12 |
|
T37 |
1 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
77 |
1 |
|
|
T138 |
3 |
|
T250 |
5 |
|
T257 |
3 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
97 |
1 |
|
|
T40 |
12 |
|
T46 |
2 |
|
T31 |
7 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
232 |
1 |
|
|
T39 |
9 |
|
T153 |
10 |
|
T87 |
10 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
191 |
1 |
|
|
T40 |
7 |
|
T245 |
14 |
|
T175 |
10 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
52 |
1 |
|
|
T228 |
20 |
|
T269 |
17 |
|
T24 |
2 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
29 |
1 |
|
|
T208 |
9 |
|
T306 |
12 |
|
T309 |
8 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
30 |
1 |
|
|
T166 |
11 |
|
T92 |
1 |
|
T308 |
10 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
43 |
1 |
|
|
T225 |
1 |
|
T315 |
9 |
|
T317 |
12 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
69 |
1 |
|
|
T87 |
10 |
|
T149 |
10 |
|
T303 |
13 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
36 |
1 |
|
|
T135 |
1 |
|
T174 |
1 |
|
T221 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
2 |
1 |
|
|
T166 |
1 |
|
T308 |
1 |
|
- |
- |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
15 |
1 |
|
|
T47 |
1 |
|
T225 |
14 |
|
- |
- |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
153 |
1 |
|
|
T33 |
11 |
|
T37 |
6 |
|
T137 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
175 |
1 |
|
|
T10 |
11 |
|
T161 |
9 |
|
T154 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1442 |
1 |
|
|
T1 |
29 |
|
T8 |
1 |
|
T9 |
21 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
143 |
1 |
|
|
T143 |
15 |
|
T137 |
1 |
|
T41 |
2 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
248 |
1 |
|
|
T47 |
1 |
|
T28 |
10 |
|
T141 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
272 |
1 |
|
|
T48 |
5 |
|
T141 |
1 |
|
T136 |
7 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
210 |
1 |
|
|
T3 |
8 |
|
T12 |
8 |
|
T40 |
5 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
182 |
1 |
|
|
T10 |
9 |
|
T12 |
11 |
|
T88 |
26 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
172 |
1 |
|
|
T12 |
14 |
|
T140 |
1 |
|
T134 |
11 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
234 |
1 |
|
|
T5 |
1 |
|
T140 |
1 |
|
T48 |
10 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
215 |
1 |
|
|
T197 |
12 |
|
T211 |
9 |
|
T139 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
171 |
1 |
|
|
T39 |
16 |
|
T142 |
1 |
|
T162 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
248 |
1 |
|
|
T161 |
12 |
|
T144 |
27 |
|
T156 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
179 |
1 |
|
|
T15 |
7 |
|
T48 |
13 |
|
T37 |
3 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
179 |
1 |
|
|
T39 |
1 |
|
T141 |
1 |
|
T163 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
221 |
1 |
|
|
T13 |
1 |
|
T39 |
2 |
|
T40 |
16 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
259 |
1 |
|
|
T134 |
8 |
|
T153 |
7 |
|
T184 |
6 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
274 |
1 |
|
|
T10 |
12 |
|
T13 |
1 |
|
T40 |
8 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
18027 |
1 |
|
|
T2 |
176 |
|
T3 |
164 |
|
T6 |
180 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
27 |
1 |
|
|
T87 |
10 |
|
T149 |
7 |
|
T172 |
3 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
45 |
1 |
|
|
T306 |
12 |
|
T293 |
2 |
|
T309 |
8 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
21 |
1 |
|
|
T166 |
11 |
|
T308 |
10 |
|
- |
- |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
11 |
1 |
|
|
T47 |
10 |
|
T225 |
1 |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
82 |
1 |
|
|
T33 |
12 |
|
T41 |
1 |
|
T171 |
13 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
101 |
1 |
|
|
T157 |
15 |
|
T223 |
9 |
|
T316 |
12 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1299 |
1 |
|
|
T8 |
13 |
|
T46 |
2 |
|
T241 |
9 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
79 |
1 |
|
|
T229 |
8 |
|
T175 |
12 |
|
T172 |
10 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
216 |
1 |
|
|
T47 |
15 |
|
T17 |
4 |
|
T149 |
11 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
188 |
1 |
|
|
T48 |
4 |
|
T139 |
10 |
|
T83 |
3 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
184 |
1 |
|
|
T40 |
4 |
|
T31 |
15 |
|
T228 |
7 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
118 |
1 |
|
|
T49 |
12 |
|
T142 |
10 |
|
T83 |
12 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
141 |
1 |
|
|
T153 |
8 |
|
T169 |
15 |
|
T82 |
6 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
155 |
1 |
|
|
T48 |
13 |
|
T138 |
12 |
|
T41 |
5 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
197 |
1 |
|
|
T197 |
9 |
|
T211 |
9 |
|
T139 |
5 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
247 |
1 |
|
|
T39 |
12 |
|
T142 |
21 |
|
T162 |
16 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
167 |
1 |
|
|
T45 |
2 |
|
T185 |
5 |
|
T151 |
11 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
108 |
1 |
|
|
T15 |
4 |
|
T48 |
12 |
|
T37 |
1 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
121 |
1 |
|
|
T39 |
9 |
|
T138 |
3 |
|
T222 |
10 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
164 |
1 |
|
|
T40 |
12 |
|
T46 |
2 |
|
T31 |
7 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
271 |
1 |
|
|
T153 |
10 |
|
T228 |
20 |
|
T150 |
16 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
172 |
1 |
|
|
T40 |
7 |
|
T245 |
14 |
|
T175 |
10 |