Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23576

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3664

1

T10

23

T12

22

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20562

1

T2

171

T3

167

T6

165

auto[1]

6678

1

T1

29

T2

5

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	654	1			T2	5		T3	5		T6	15
values[0]	96	1			T162	17		T221	28		T289	24
values[1]	647	1			T3	8		T134	11		T49	13
values[2]	3093	1			T1	29		T8	14		T9	21
values[3]	760	1			T10	12		T12	22		T13	1
values[4]	724	1			T39	2		T46	10		T140	2
values[5]	653	1			T12	11		T39	28		T28	1
values[6]	685	1			T5	1		T10	20		T88	14
values[7]	722	1			T13	1		T40	28		T88	10
values[8]	680	1			T15	11		T31	8		T141	1
values[9]	968	1			T13	1		T39	10		T40	15
minimum	17558	1			T2	171		T3	159		T6	165

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	724	1			T3	8		T47	16		T49	13
values[1]	3027	1			T1	29		T8	14		T9	21
values[2]	775	1			T10	12		T12	14		T40	9
values[3]	703	1			T39	2		T46	10		T140	1
values[4]	675	1			T5	1		T10	11		T12	11
values[5]	642	1			T10	9		T88	14		T47	11
values[6]	810	1			T13	1		T40	28		T88	10
values[7]	649	1			T13	1		T39	10		T15	11
values[8]	801	1			T40	15		T46	17		T31	16
values[9]	140	1			T48	25		T154	1		T155	8
minimum	18294	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	3		T47	16		T49	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T142	22		T235	1		T247	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T1	3		T8	14		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T13	1		T163	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T88	1		T140	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	1		T12	1		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T39	1		T46	3		T48	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T140	1		T169	16		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T5	1		T12	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	1		T39	13		T48	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	1		T88	1		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T143	1		T144	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T153	11		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T40	13		T88	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	10		T15	7		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T31	8		T153	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	8		T46	3		T31	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T33	13		T213	2		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T154	1		T155	1		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T48	13		T139	10		T246	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17959	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T134	1		T162	17		T155	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	5		T161	8		T133	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T235	12		T247	1		T22	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T1	26		T9	19		T26	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	7		T45	5		T235	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T88	15		T28	9		T136	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	11		T12	13		T40	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	1		T46	7		T48	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T169	16		T16	3		T249	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	10		T56	11		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	10		T39	15		T48	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	8		T88	13		T184	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T143	11		T144	14		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T153	6		T143	14		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	15		T88	9		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	4		T138	3		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T153	9		T197	11		T138	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T40	7		T46	14		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	10		T213	20		T87	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T155	7		T221	9		T262	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T48	12		T246	6		T237	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T134	10		T155	10		T239	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	536	1			T2	5		T3	5		T6	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T213	1		T139	10		T295	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T289	10		T232	7		T233	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T162	17		T221	13		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	3		T49	13		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T134	1		T155	1		T83	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T1	3		T8	14		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T142	22		T163	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T88	1		T28	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	1		T12	2		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T39	1		T46	3		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T140	1		T137	1		T169	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T28	1		T37	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T39	13		T48	14		T37	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T10	1		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	1		T143	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	1		T153	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T40	13		T88	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	7		T141	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T31	8		T153	9		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T39	10		T40	8		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T13	1		T33	13		T48	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T2	171		T3	159		T6	165
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T161	11		T221	9		T236	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T213	14		T283	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T289	14		T232	2		T233	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T221	15		T238	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	5		T161	8		T133	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T134	10		T155	10		T239	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T1	26		T9	19		T26	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T45	5		T235	12		T247	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T88	15		T28	9		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	11		T12	20		T40	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T39	1		T46	7		T48	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T169	16		T16	3		T249	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	10		T56	11		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	15		T48	9		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	8		T88	13		T277	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	10		T143	11		T211	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T153	6		T143	14		T144	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T40	15		T88	9		T144	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	4		T136	10		T138	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T153	9		T143	2		T197	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T40	7		T46	14		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T33	10		T48	12		T213	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	8		T47	1		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T142	1		T235	13		T247	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T1	29		T8	1		T9	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	8		T13	1		T163	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T88	16		T140	1		T28	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	12		T12	14		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	2		T46	8		T48	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T140	1		T169	17		T16	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	1		T12	11		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T10	11		T39	16		T48	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	9		T88	14		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T143	12		T144	15		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	1		T153	7		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	16		T88	10		T143	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T39	1		T15	7		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T31	1		T153	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	8		T46	15		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T33	11		T213	22		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T154	1		T155	8		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T48	13		T139	1		T246	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18119	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T134	11		T162	1		T155	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T47	15		T49	12		T133	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T142	21		T247	1		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T8	13		T241	9		T242	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T151	9		T175	12		T217	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	12		T149	2		T185	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	4		T228	2		T243	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	2		T48	4		T41	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T169	15		T148	9		T231	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T142	10		T37	1		T56	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T39	12		T48	13		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T47	10		T244	14		T96	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T133	10		T82	6		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T153	10		T42	2		T17	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	12		T149	11		T150	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	9		T15	4		T138	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T31	7		T153	8		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	7		T46	2		T31	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T33	12		T87	10		T157	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T221	9		T262	11		T236	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T48	12		T139	9		T246	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T20	10		T222	10		T309	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T162	16		T83	3		T186	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	521	1			T2	5		T3	5		T6	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T213	15		T139	1		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T289	15		T232	3		T233	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T162	1		T221	16		T238	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	8		T49	1		T161	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T134	11		T155	11		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T1	29		T8	1		T9	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T142	1		T163	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T88	16		T28	10		T136	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	12		T12	22		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T39	2		T46	8		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T140	1		T137	1		T169	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	11		T28	1		T37	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	16		T48	10		T37	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T10	9		T88	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	11		T143	12		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T153	7		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T40	16		T88	10		T144	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	7		T141	1		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T31	1		T153	10		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T39	1		T40	8		T46	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T13	1		T33	11		T48	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	171		T3	159		T6	165
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T221	9		T312	6		T236	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T139	9		T295	12		T283	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T289	9		T232	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T162	16		T221	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	12		T133	10		T234	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T83	3		T186	17		T217	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T8	13		T47	15		T241	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T142	21		T247	1		T175	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T138	12		T56	15		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T40	4		T151	9		T243	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	2		T48	4		T41	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T169	15		T148	9		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T37	1		T56	11		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	12		T48	13		T224	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	10		T142	10		T244	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T211	9		T82	6		T83	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T153	10		T42	2		T17	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	12		T133	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	4		T138	3		T41	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	7		T153	8		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T39	9		T40	7		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T33	12		T48	12		T87	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23