Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23972

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3268

1

T10

23

T12

22

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21161

1

T2

176

T3

172

T6

180

auto[1]

6079

1

T1

29

T5

1

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	363	1			T154	1		T37	4		T137	1
values[0]	74	1			T149	23		T278	5		T280	27
values[1]	701	1			T5	1		T10	11		T12	8
values[2]	613	1			T39	2		T88	10		T31	8
values[3]	581	1			T10	12		T39	10		T47	16
values[4]	757	1			T3	8		T46	17		T47	11
values[5]	634	1			T10	9		T12	11		T39	28
values[6]	651	1			T40	28		T46	10		T142	22
values[7]	640	1			T13	1		T88	14		T33	23
values[8]	2965	1			T1	29		T8	14		T9	21
values[9]	1234	1			T12	14		T13	1		T88	16
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	652	1			T5	1		T10	11		T12	8
values[1]	616	1			T39	2		T88	10		T31	8
values[2]	681	1			T10	12		T39	10		T47	16
values[3]	747	1			T3	8		T46	17		T47	11
values[4]	559	1			T10	9		T12	11		T39	28
values[5]	675	1			T13	1		T40	28		T88	14
values[6]	3048	1			T1	29		T8	14		T9	21
values[7]	526	1			T40	15		T28	10		T141	1
values[8]	1325	1			T12	14		T13	1		T88	16
values[9]	130	1			T143	3		T229	17		T164	8
minimum	18281	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T13	1		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	1		T12	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T88	1		T31	8		T134	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	1		T49	13		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	10		T47	16		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	1		T15	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	3		T46	3		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	11		T156	1		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	1		T12	1		T39	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T40	5		T156	1		T96	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T88	1		T46	3		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	1		T40	13		T142	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T1	3		T8	14		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T33	13		T37	4		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T28	1		T141	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	8		T213	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T88	1		T140	1		T56	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T12	1		T13	1		T48	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T143	1		T229	9		T175	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T164	1		T204	1		T246	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17959	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T212	1		T56	12		T150	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	4		T144	13		T42	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	10		T12	7		T134	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T88	9		T134	17		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	1		T197	11		T82	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	3		T215	7		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	11		T15	4		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	5		T46	14		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T170	11		T175	12		T230	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	8		T12	10		T39	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T40	4		T89	7		T108	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T88	13		T46	7		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	15		T138	3		T41	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T1	26		T9	19		T26	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T33	10		T37	2		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T28	9		T213	6		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T40	7		T213	14		T153	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T88	15		T56	14		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T12	13		T48	9		T169	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T143	2		T229	8		T175	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T164	7		T246	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T15	1		T32	1		T161	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T56	11		T260	9		T293	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T229	9		T149	8		T186	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T154	1		T37	4		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T278	5		T280	11		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	12		T279	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T13	1		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T12	1		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T88	1		T31	8		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	1		T49	13		T197	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	10		T47	16		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	1		T15	7		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	3		T46	3		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T47	11		T143	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T10	1		T12	1		T39	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T40	5		T156	1		T277	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T46	3		T218	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	13		T142	22		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T88	1		T48	13		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	1		T33	13		T37	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T1	3		T8	14		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T40	8		T213	1		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T88	1		T140	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T12	1		T13	1		T48	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T229	8		T149	9		T186	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T296	1		T327	12		T195	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T280	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T149	11		T279	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T48	4		T161	8		T144	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	10		T12	7		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T88	9		T134	10		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T39	1		T197	11		T82	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T134	7		T143	14		T194	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	11		T15	4		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	5		T46	14		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T143	11		T136	10		T41	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	8		T12	10		T39	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T40	4		T277	2		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T46	7		T184	5		T82	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	15		T41	1		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T88	13		T48	12		T136	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T33	10		T37	2		T138	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T1	26		T9	19		T26	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T40	7		T213	14		T153	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T88	15		T28	9		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T12	13		T48	9		T169	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T13	1		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	11		T12	8		T134	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T88	10		T31	1		T134	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	2		T49	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	1		T47	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	12		T15	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	8		T46	15		T211	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	1		T156	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	9		T12	11		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T40	5		T156	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T88	14		T46	8		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	1		T40	16		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T1	29		T8	1		T9	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T33	11		T37	6		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	10		T141	1		T213	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T40	8		T213	15		T153	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T88	16		T140	1		T56	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T12	14		T13	1		T48	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T143	3		T229	9		T175	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T164	8		T204	1		T246	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18137	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T212	1		T56	12		T150	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	4		T42	2		T234	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T133	10		T149	11		T22	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T31	7		T138	12		T295	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T49	12		T197	9		T82	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	9		T47	15		T215	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	4		T142	10		T41	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	2		T211	9		T139	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	10		T148	9		T175	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	12		T31	15		T162	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T40	4		T96	6		T89	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T46	2		T149	2		T19	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T40	12		T142	21		T138	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T8	13		T48	12		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T33	12		T150	16		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T153	8		T228	2		T221	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	7		T153	10		T139	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T56	15		T149	7		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T48	13		T37	1		T169	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T229	8		T175	10		T315	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T246	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T20	2		T306	10		T292	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T56	11		T150	16		T260	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T229	9		T149	10		T186	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T154	1		T37	3		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T278	1		T280	17		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T149	12		T279	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	1		T13	1		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	11		T12	8		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T88	10		T31	1		T134	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	2		T49	1		T197	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	1		T47	1		T134	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	12		T15	7		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	8		T46	15		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T47	1		T143	12		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	9		T12	11		T39	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T40	5		T156	1		T277	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T46	8		T218	1		T184	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	16		T142	1		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T88	14		T48	13		T136	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T33	11		T37	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T1	29		T8	1		T9	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	8		T213	15		T153	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T88	16		T140	1		T28	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T12	14		T13	1		T48	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T229	8		T149	7		T186	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T37	1		T296	1		T327	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T278	4		T280	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T149	11		T279	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	4		T42	2		T234	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T133	10		T56	11		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	7		T138	12		T224	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T49	12		T197	9		T82	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	9		T47	15		T245	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T15	4		T142	10		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	2		T139	9		T215	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T47	10		T41	5		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T39	12		T31	15		T162	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T40	4		T221	12		T96	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T46	2		T82	6		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	12		T142	21		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T48	12		T228	7		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T33	12		T138	3		T150	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T8	13		T153	8		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	7		T153	10		T83	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T56	15		T226	2		T185	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T48	13		T169	15		T133	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23