Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T3	8		T47	1		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T134	11		T162	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T1	29		T8	1		T9	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	8		T141	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	5		T140	1		T28	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	14		T13	1		T134	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	2		T46	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	12		T137	1		T169	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	11		T12	11		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T28	1		T48	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	9		T88	14		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	1		T143	12		T211	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T88	10		T153	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T40	16		T197	12		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	1		T15	7		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	1		T31	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T40	8		T46	15		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	11		T213	22		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T154	1		T155	8		T229	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T48	13		T41	2		T139	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T47	15		T49	12		T142	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T162	16		T83	3		T234	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T8	13		T241	9		T242	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T151	9		T175	12		T22	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T40	4		T138	12		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T228	2		T243	13		T166	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	2		T48	4		T41	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T169	15		T148	9		T231	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	12		T142	10		T56	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	13		T37	1		T83	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T42	2		T171	13		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T47	10		T211	9		T82	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T153	10		T133	10		T17	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T40	12		T197	9		T149	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	9		T15	4		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T31	7		T153	8		T138	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	7		T46	2		T31	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T33	12		T157	15		T245	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T229	8		T236	6		T246	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T48	12		T139	19		T221	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T2	5		T3	5		T6	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T213	15		T221	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T233	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T221	16		T232	3		T238	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	8		T49	1		T161	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T134	11		T162	1		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T1	29		T8	1		T9	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T141	1		T163	1		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T40	5		T88	16		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	12		T12	22		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T39	2		T46	8		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T141	1		T137	1		T169	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	11		T39	16		T56	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	1		T48	10		T37	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	20		T88	14		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T47	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	1		T88	10		T153	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T40	16		T143	12		T197	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	7		T143	3		T45	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T31	1		T153	10		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T39	1		T40	8		T46	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T33	11		T48	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17558	1			T2	171		T3	159		T6	165
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T221	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T221	12		T232	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	12		T133	10		T20	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T162	16		T83	3		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T8	13		T47	15		T142	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T228	20		T20	2		T247	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	4		T138	12		T56	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T151	9		T243	13		T166	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	2		T48	4		T41	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T169	15		T148	9		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	12		T56	11		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T48	13		T37	1		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T142	10		T175	10		T248	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T47	10		T82	6		T83	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T153	10		T41	1		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	12		T197	9		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	4		T45	2		T19	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T31	7		T153	8		T138	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T39	9		T40	7		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T33	12		T48	12		T139	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23