Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23534

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3706

1

T10

11

T12

19

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21296

1

T2

176

T3

164

T5

1

auto[1]

5944

1

T1

29

T3

8

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T139	6		T89	3		-	-
values[0]	28	1			T3	8		T45	6		T249	1
values[1]	813	1			T10	11		T40	24		T46	10
values[2]	750	1			T13	1		T28	10		T134	8
values[3]	613	1			T5	1		T12	14		T142	11
values[4]	578	1			T40	28		T137	1		T211	18
values[5]	2994	1			T1	29		T8	14		T9	21
values[6]	790	1			T88	14		T46	17		T140	1
values[7]	793	1			T10	12		T13	1		T39	2
values[8]	594	1			T13	1		T161	12		T163	1
values[9]	1251	1			T10	9		T39	38		T28	1
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1027	1			T3	8		T10	11		T13	1
values[1]	722	1			T12	14		T46	10		T28	10
values[2]	595	1			T5	1		T142	11		T136	11
values[3]	2986	1			T1	29		T8	14		T9	21
values[4]	629	1			T88	16		T140	1		T47	11
values[5]	845	1			T12	11		T88	14		T46	17
values[6]	677	1			T10	12		T13	1		T39	2
values[7]	631	1			T13	1		T161	12		T163	1
values[8]	994	1			T10	9		T39	38		T28	1
values[9]	88	1			T41	2		T82	13		T164	12
minimum	18046	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T3	3		T40	13		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	1		T13	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T46	3		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T134	1		T16	2		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T136	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T142	11		T41	8		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T1	3		T8	14		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T40	13		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T212	1		T143	1		T231	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T88	1		T140	1		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	13		T141	1		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T12	1		T88	1		T46	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	1		T48	14		T17	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T39	1		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T163	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T161	1		T184	1		T83	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	1		T39	23		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T134	2		T49	13		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T82	8		T250	6		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T41	2		T164	1		T252	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T45	1		T18	3		T253	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T3	5		T40	11		T48	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	10		T197	11		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	13		T46	7		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	7		T16	3		T185	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T136	10		T56	11		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	5		T184	5		T45	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T1	26		T9	19		T26	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	7		T40	15		T211	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T143	14		T186	8		T215	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T88	15		T33	10		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T48	12		T153	9		T42	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T12	10		T88	13		T46	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	11		T48	9		T17	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	1		T88	9		T15	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T144	13		T133	12		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T161	11		T184	15		T175	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	8		T39	15		T56	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T134	17		T213	6		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T82	5		T250	2		T89	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T164	11		T252	5		T216	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T45	5		T18	3		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T139	6		T89	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T3	3		T249	1		T254	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T45	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T40	13		T46	3		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T141	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T28	1		T143	1		T162	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T134	1		T197	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	1		T12	1		T136	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T142	11		T41	2		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T139	11		T255	1		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	13		T137	1		T211	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T1	3		T8	14		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	2		T88	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T212	1		T141	1		T42	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T88	1		T46	3		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	1		T48	27		T153	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	1		T39	1		T88	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	1		T163	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T161	1		T42	2		T169	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T10	1		T39	23		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	412	1			T134	2		T49	13		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T89	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T3	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T45	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T40	11		T46	7		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	10		T170	11		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T28	9		T143	11		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T134	7		T197	11		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	13		T136	16		T56	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	1		T184	5		T221	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T243	1		T165	7		T256	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	15		T211	8		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1100	1			T1	26		T9	19		T26	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	17		T88	15		T243	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T42	3		T226	11		T215	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T88	13		T46	14		T33	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	11		T48	21		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	1		T88	9		T15	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T144	13		T133	12		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T161	11		T42	1		T169	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	8		T39	15		T56	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T134	17		T213	6		T143	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T3	8		T40	13		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	11		T13	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	14		T46	8		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T134	8		T16	5		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T136	11		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T142	1		T41	7		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T1	29		T8	1		T9	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	8		T40	16		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T212	1		T143	15		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T88	16		T140	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	13		T141	1		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T12	11		T88	14		T46	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	12		T48	10		T17	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T39	2		T88	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T163	1		T144	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T161	12		T184	16		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	9		T39	17		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T134	19		T49	1		T213	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T82	6		T250	3		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T41	2		T164	12		T252	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T45	6		T18	6		T253	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T40	11		T48	4		T142	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T197	9		T18	1		T171	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	2		T162	16		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T139	9		T185	9		T20	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T56	11		T215	6		T221	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T142	10		T41	6		T45	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T8	13		T241	9		T242	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	12		T211	9		T20	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T231	10		T186	12		T215	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T47	10		T31	15		T33	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	12		T153	8		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	2		T31	7		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	13		T17	4		T151	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T47	15		T15	4		T169	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	10		T82	6		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T83	12		T150	16		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	21		T56	15		T139	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T49	12		T133	10		T234	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T82	7		T250	5		T89	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T252	2		T216	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T253	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T139	1		T89	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T3	8		T249	1		T254	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T45	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T40	13		T46	8		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	11		T141	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	10		T143	12		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	1		T134	8		T197	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T12	14		T136	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T142	1		T41	2		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T139	1		T255	1		T243	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T40	16		T137	1		T211	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T1	29		T8	1		T9	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	19		T88	16		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T212	1		T141	1		T42	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T88	14		T46	15		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	12		T48	23		T153	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	1		T39	2		T88	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	1		T163	1		T144	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T161	12		T42	3		T169	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T10	9		T39	17		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T134	19		T49	1		T213	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T139	5		T89	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T254	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T40	11		T46	2		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T171	10		T227	16		T257	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T162	16		T149	7		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T197	9		T139	9		T45	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T56	11		T149	2		T186	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T142	10		T41	1		T221	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T139	10		T258	9		T22	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	12		T211	9		T41	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T8	13		T241	9		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T243	13		T259	13		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T42	2		T83	3		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T46	2		T47	10		T31	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	25		T153	8		T151	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	15		T15	4		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T133	10		T82	6		T17	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T169	15		T83	12		T217	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	21		T56	15		T82	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T49	12		T133	10		T234	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23