Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23542

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3698

1

T5

1

T10

32

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21422

1

T2

176

T3

164

T5

1

auto[1]

5818

1

T1

29

T3

8

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T104	1		T261	9		-	-
values[0]	55	1			T47	11		T255	1		T243	30
values[1]	515	1			T13	1		T39	28		T140	1
values[2]	716	1			T12	11		T15	11		T28	1
values[3]	726	1			T46	17		T48	23		T134	8
values[4]	730	1			T5	1		T12	14		T28	10
values[5]	763	1			T39	10		T33	23		T134	11
values[6]	706	1			T10	23		T13	1		T40	43
values[7]	636	1			T143	12		T136	11		T41	3
values[8]	694	1			T13	1		T140	1		T48	25
values[9]	3662	1			T1	29		T3	8		T8	14
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	642	1			T13	1		T39	28		T140	1
values[1]	825	1			T12	11		T15	11		T28	1
values[2]	742	1			T5	1		T46	17		T31	8
values[3]	699	1			T12	14		T28	10		T141	1
values[4]	680	1			T39	10		T40	28		T88	10
values[5]	826	1			T10	23		T13	1		T40	15
values[6]	2939	1			T1	29		T8	14		T9	21
values[7]	660	1			T13	1		T140	1		T213	7
values[8]	926	1			T3	8		T10	9		T12	8
values[9]	238	1			T88	14		T144	15		T171	21
minimum	18063	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T140	1		T47	11		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	1		T39	13		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T15	7		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T28	1		T143	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T31	8		T48	14		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T46	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T153	9		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	1		T141	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T39	10		T134	1		T142	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	13		T88	1		T33	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	8		T136	1		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	2		T13	1		T49	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T1	3		T8	14		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	13		T137	1		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T136	1		T41	2		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T140	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	3		T12	1		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	1		T39	1		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T194	1		T217	9		T262	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T88	1		T144	1		T171	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T263	1		T92	12		T264	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T185	11		T243	16		T248	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	15		T37	2		T169	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	10		T15	4		T134	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T143	14		T41	4		T56	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T48	9		T161	11		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T46	14		T134	7		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	13		T153	9		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T28	9		T161	8		T138	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T134	10		T155	7		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T40	15		T88	9		T33	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T40	7		T136	10		T20	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	21		T82	5		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T1	26		T9	19		T26	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T48	12		T41	1		T151	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T136	6		T184	15		T265	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T213	6		T153	6		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	5		T12	7		T40	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	8		T39	1		T88	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T194	7		T217	8		T262	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T88	13		T144	14		T171	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T263	2		T264	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T104	1		T261	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T47	11		T243	14		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T255	1		T267	1		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T140	1		T141	1		T185	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	1		T39	13		T37	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T15	7		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T28	1		T154	1		T41	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	14		T197	10		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T46	3		T134	1		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T31	8		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	1		T28	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T39	10		T134	1		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T33	13		T142	11		T82	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	8		T18	3		T20	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	2		T13	1		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T143	1		T136	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T41	2		T83	1		T150	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T136	1		T171	14		T187	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	1		T140	1		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1780	1			T1	3		T3	3		T8	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T10	1		T39	1		T88	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T261	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T243	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T267	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T185	11		T248	4		T250	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	15		T37	2		T169	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	10		T15	4		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T41	4		T56	14		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T48	9		T197	11		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	14		T134	7		T143	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	13		T161	11		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	9		T161	8		T138	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T134	10		T153	9		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T33	10		T82	6		T269	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	7		T18	3		T20	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	21		T40	15		T88	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T143	11		T136	10		T184	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T41	1		T151	12		T270	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T136	6		T171	5		T36	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T48	12		T138	5		T56	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T1	26		T3	5		T9	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T10	8		T39	1		T88	28
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T140	1		T47	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T39	16		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	11		T15	7		T134	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T28	1		T143	15		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T31	1		T48	10		T161	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	1		T46	15		T134	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	14		T153	10		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	10		T141	1		T161	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T39	1		T134	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	16		T88	10		T33	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T40	8		T136	11		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	23		T13	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T1	29		T8	1		T9	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	13		T137	1		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T136	7		T41	2		T184	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T13	1		T140	1		T213	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T3	8		T12	8		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	9		T39	2		T88	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T194	8		T217	9		T262	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T88	14		T144	15		T171	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T263	3		T92	1		T264	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T47	10		T185	5		T243	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	12		T169	15		T157	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	4		T211	9		T133	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T41	5		T56	15		T149	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T31	7		T48	13		T197	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	2		T133	10		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	8		T20	11		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	1		T138	3		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T39	9		T142	21		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	12		T33	12		T142	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	7		T20	12		T231	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	12		T82	7		T83	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T8	13		T241	9		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T48	12		T41	1		T150	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T139	9		T187	13		T96	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T153	10		T138	12		T56	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	4		T46	2		T31	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	15		T48	4		T162	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T217	8		T107	7		T271	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T171	10		T245	14		T272	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T92	11		T264	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T104	1		T261	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T47	1		T243	17		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T255	1		T267	2		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T140	1		T141	1		T185	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T39	16		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	11		T15	7		T134	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T28	1		T154	1		T41	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	10		T197	12		T211	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T46	15		T134	8		T143	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	14		T31	1		T161	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T28	10		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T39	1		T134	11		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T33	11		T142	1		T82	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	8		T18	6		T20	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	23		T13	1		T40	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T143	12		T136	11		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T41	2		T83	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	7		T171	6		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	1		T140	1		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1665	1			T1	29		T3	8		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T10	9		T39	2		T88	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T261	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T47	10		T243	13		T273	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T185	5		T248	6		T250	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	12		T169	15		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	4		T133	10		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T41	5		T56	15		T149	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	13		T197	9		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	2		T37	1		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	7		T83	3		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T138	3		T42	2		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T39	9		T153	8		T142	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T33	12		T142	10		T82	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T40	7		T20	2		T231	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	12		T49	12		T82	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	10		T175	12		T221	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	1		T150	16		T151	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T171	13		T187	13		T36	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T48	12		T162	16		T138	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T8	13		T40	4		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T47	15		T48	4		T153	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23