Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24009

1

T1

29

T2

176

T3

172

auto[ADC_CTRL_FILTER_COND_OUT]

3231

1

T10

23

T12

22

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21092

1

T2

176

T3

172

T6

180

auto[1]

6148

1

T1

29

T5

1

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T175	21		-	-		-	-
values[0]	95	1			T149	23		T20	19		T274	2
values[1]	631	1			T5	1		T10	11		T12	8
values[2]	669	1			T39	2		T88	10		T31	8
values[3]	566	1			T10	12		T39	10		T15	11
values[4]	768	1			T3	8		T46	17		T47	27
values[5]	632	1			T10	9		T12	11		T39	28
values[6]	713	1			T40	37		T46	10		T33	23
values[7]	563	1			T13	1		T88	14		T48	25
values[8]	3024	1			T1	29		T8	14		T9	21
values[9]	1531	1			T12	14		T13	1		T88	16
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	889	1			T5	1		T10	11		T12	8
values[1]	635	1			T39	2		T88	10		T28	1
values[2]	607	1			T10	12		T39	10		T47	16
values[3]	829	1			T3	8		T46	17		T47	11
values[4]	567	1			T10	9		T12	11		T39	28
values[5]	633	1			T13	1		T40	28		T88	14
values[6]	3010	1			T1	29		T8	14		T9	21
values[7]	599	1			T40	15		T28	10		T141	1
values[8]	1224	1			T12	14		T13	1		T88	16
values[9]	203	1			T143	3		T229	17		T164	8
minimum	18044	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	1		T13	1		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	1		T12	1		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T88	1		T31	8		T134	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	1		T28	1		T49	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	10		T47	16		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	1		T15	7		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	3		T46	3		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T47	11		T156	1		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	1		T12	1		T39	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T40	5		T156	1		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T88	1		T138	1		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T40	13		T142	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T1	3		T8	14		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	13		T163	1		T150	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	1		T141	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	8		T213	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T88	1		T140	1		T149	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T12	1		T13	1		T48	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T143	1		T229	9		T175	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T164	1		T271	13		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T150	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T48	4		T161	8		T144	27
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	10		T12	7		T134	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T88	9		T134	17		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T39	1		T197	11		T82	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T215	7		T194	7		T276	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	11		T15	4		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	5		T46	14		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T170	11		T247	1		T175	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	8		T12	10		T39	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T40	4		T151	12		T277	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T88	13		T138	14		T184	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	15		T37	2		T138	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T1	26		T9	19		T26	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T33	10		T256	12		T250	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T28	9		T213	6		T56	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T40	7		T213	14		T153	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T88	15		T149	9		T226	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T12	13		T48	9		T169	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T143	2		T229	8		T175	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T164	7		T271	14		T275	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T175	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T20	5		T274	1		T278	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	12		T279	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	1		T13	1		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	1		T12	1		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T88	1		T31	8		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	1		T134	1		T49	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	10		T134	2		T142	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	1		T15	7		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	3		T46	3		T47	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T47	11		T143	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	1		T12	1		T39	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T156	1		T175	13		T277	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	3		T136	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T40	18		T33	13		T142	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T88	1		T48	13		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T37	4		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T1	3		T8	14		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	8		T153	11		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	479	1			T88	1		T140	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T12	1		T13	1		T48	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T175	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T20	14		T274	1		T280	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T149	11		T279	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	4		T161	8		T144	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	10		T12	7		T133	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T88	9		T138	5		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	1		T134	7		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T134	17		T143	14		T16	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	11		T15	4		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	5		T46	14		T211	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T143	11		T136	10		T41	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	8		T12	10		T39	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T175	12		T277	2		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T46	7		T136	6		T184	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	19		T33	10		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T88	13		T48	12		T138	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T37	2		T138	3		T41	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T1	26		T9	19		T26	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	7		T153	6		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T88	15		T28	9		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T12	13		T48	9		T213	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T5	1		T13	1		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	11		T12	8		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T88	10		T31	1		T134	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T39	2		T28	1		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	1		T47	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	12		T15	7		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	8		T46	15		T211	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T47	1		T156	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	9		T12	11		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T40	5		T156	1		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T88	14		T138	15		T184	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	1		T40	16		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T1	29		T8	1		T9	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T33	11		T163	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	10		T141	1		T213	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	8		T213	15		T153	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T88	16		T140	1		T149	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T12	14		T13	1		T48	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T143	3		T229	9		T175	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T164	8		T271	15		T275	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T150	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	4		T42	2		T234	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	10		T56	11		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T31	7		T138	12		T224	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T49	12		T197	9		T82	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T39	9		T47	15		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	4		T41	5		T228	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	2		T211	9		T139	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T47	10		T148	9		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T39	12		T46	2		T31	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T40	4		T151	11		T89	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T149	2		T19	1		T208	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T40	12		T142	21		T138	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T8	13		T48	12		T153	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T33	12		T150	16		T258	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T56	15		T228	2		T221	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	7		T153	10		T139	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T149	7		T226	2		T185	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T48	13		T37	1		T169	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T229	8		T175	10		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T271	12		T246	7		T281	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T150	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T175	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T20	17		T274	2		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T149	12		T279	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T13	1		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	11		T12	8		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T88	10		T31	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	2		T134	8		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	1		T134	19		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	12		T15	7		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	8		T46	15		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T47	1		T143	12		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	9		T12	11		T39	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T156	1		T175	13		T277	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T46	8		T136	7		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T40	21		T33	11		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T88	14		T48	13		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	1		T37	6		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T1	29		T8	1		T9	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	8		T153	7		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	406	1			T88	16		T140	1		T28	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T12	14		T13	1		T48	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T175	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T20	2		T278	4		T280	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T149	11		T279	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T48	4		T42	2		T157	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T133	10		T56	11		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T31	7		T138	12		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T49	12		T197	9		T82	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	9		T142	10		T139	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T15	4		T45	2		T228	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	2		T47	15		T211	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T47	10		T41	5		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T39	12		T31	15		T162	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T175	12		T221	12		T96	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T46	2		T149	2		T227	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T40	16		T33	12		T142	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T48	12		T82	6		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T138	3		T41	1		T186	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T8	13		T153	8		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	7		T153	10		T83	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	395	1			T56	15		T229	8		T149	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T48	13		T37	1		T169	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23