Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23791

1

T1

29

T2

176

T3

164

auto[ADC_CTRL_FILTER_COND_OUT]

3449

1

T3

8

T10

23

T12

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20851

1

T2

176

T3

172

T6

180

auto[1]

6389

1

T1

29

T5

1

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T282	7		-	-		-	-
values[0]	65	1			T138	15		T243	2		T276	18
values[1]	633	1			T88	16		T140	2		T47	11
values[2]	761	1			T13	1		T143	3		T197	21
values[3]	694	1			T10	11		T13	1		T88	14
values[4]	662	1			T40	28		T31	16		T134	11
values[5]	2985	1			T1	29		T8	14		T9	21
values[6]	789	1			T12	11		T39	12		T40	9
values[7]	699	1			T10	9		T12	14		T88	10
values[8]	555	1			T3	8		T39	28		T48	25
values[9]	1363	1			T5	1		T10	12		T40	15
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	845	1			T140	2		T47	11		T28	10
values[1]	850	1			T10	11		T13	1		T88	30
values[2]	608	1			T15	11		T31	16		T163	1
values[3]	3079	1			T1	29		T8	14		T9	21
values[4]	666	1			T13	1		T39	12		T46	10
values[5]	795	1			T12	11		T40	9		T46	17
values[6]	597	1			T10	9		T12	14		T39	28
values[7]	535	1			T3	8		T48	25		T153	18
values[8]	1026	1			T5	1		T10	12		T28	1
values[9]	194	1			T40	15		T161	9		T133	23
minimum	18045	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T140	1		T28	1		T33	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T140	1		T47	11		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T88	1		T31	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T10	1		T88	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	7		T31	16		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T42	2		T16	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T1	3		T8	14		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T13	1		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	1		T46	3		T47	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	1		T39	10		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T46	3		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T40	5		T141	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	1		T141	1		T142	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T39	13		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T153	9		T255	1		T186	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	3		T48	13		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	1		T28	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T10	1		T212	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T40	8		T161	1		T151	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T133	11		T239	2		T103	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T28	9		T33	10		T48	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T138	14		T133	7		T17	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T88	15		T143	2		T161	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	10		T88	13		T213	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	4		T144	13		T184	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T42	1		T243	16		T277	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T1	26		T9	19		T26	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	7		T40	15		T169	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	1		T46	7		T138	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T143	11		T16	3		T87	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	10		T46	14		T229	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	4		T41	4		T82	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	8		T149	9		T171	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	13		T39	15		T88	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T153	9		T248	4		T270	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T3	5		T48	12		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T213	6		T170	11		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	11		T134	7		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T40	7		T161	8		T151	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T133	12		T239	2		T252	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T276	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T243	1		T263	1		T283	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T138	1		T276	10		T261	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T88	1		T140	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T140	1		T47	11		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	1		T143	1		T197	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T133	11		T139	11		T83	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	7		T31	8		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	1		T13	1		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	16		T134	1		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	13		T142	11		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T1	3		T8	14		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T13	1		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T39	1		T46	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	10		T40	5		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	1		T142	22		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T88	1		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T141	1		T153	9		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	3		T39	13		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T5	1		T40	8		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	483	1			T10	1		T134	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T282	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T243	1		T283	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T138	14		T276	8		T261	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T88	15		T28	9		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T17	4		T194	7		T284	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T143	2		T197	11		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T133	7		T234	15		T185	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	4		T161	11		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	10		T88	13		T213	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T134	10		T153	6		T184	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T40	15		T169	16		T224	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T1	26		T9	19		T46	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	7		T16	3		T234	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	10		T39	1		T46	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	4		T143	11		T87	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	8		T149	9		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	13		T88	9		T48	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T153	9		T170	11		T247	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	5		T39	15		T48	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T40	7		T213	6		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T10	11		T134	7		T136	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T140	1		T28	10		T33	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	1		T47	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	1		T88	16		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	11		T88	14		T213	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	7		T31	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	3		T16	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T1	29		T8	1		T9	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	8		T13	1		T40	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T39	2		T46	8		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T39	1		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	11		T46	15		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T40	5		T141	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	9		T141	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	14		T39	16		T88	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T153	10		T255	1		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	8		T48	13		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	1		T28	1		T213	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T10	12		T212	1		T134	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T40	8		T161	9		T151	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T133	13		T239	4		T103	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T33	12		T48	4		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	10		T133	10		T17	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	7		T211	9		T249	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T139	19		T83	12		T234	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	4		T31	15		T56	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T243	13		T221	9		T36	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T8	13		T153	10		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	12		T142	10		T169	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T46	2		T47	15		T49	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	9		T87	10		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	2		T229	8		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T40	4		T41	5		T139	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T142	21		T149	7		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T39	12		T48	13		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T153	8		T186	5		T248	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T48	12		T42	2		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T162	16		T185	5		T245	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T56	11		T228	7		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T40	7		T151	9		T285	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T133	10		T252	2		T286	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T282	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T243	2		T263	1		T283	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T138	15		T276	9		T261	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T88	16		T140	1		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T140	1		T47	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	1		T143	3		T197	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T133	8		T139	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	7		T31	1		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	11		T13	1		T88	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T31	1		T134	11		T153	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	16		T142	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T1	29		T8	1		T9	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	8		T13	1		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	11		T39	2		T46	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T39	1		T40	5		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	9		T142	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	14		T88	10		T48	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T141	1		T153	10		T255	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	8		T39	16		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T5	1		T40	8		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T10	12		T134	8		T136	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T283	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T276	9		T261	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T33	12		T48	4		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T47	10		T139	9		T17	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T197	9		T37	1		T211	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T133	10		T139	10		T83	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	4		T31	7		T250	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T243	13		T287	9		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T31	15		T153	10		T56	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	12		T142	10		T169	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T8	13		T46	2		T47	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T228	2		T18	1		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	2		T138	12		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T39	9		T40	4		T139	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T142	21		T149	7		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	13		T41	5		T82	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T153	8		T247	1		T186	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T39	12		T48	12		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T40	7		T162	16		T185	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T133	10		T56	11		T228	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23