Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23706

1

T1

29

T2

176

T3

164

auto[ADC_CTRL_FILTER_COND_OUT]

3534

1

T3

8

T10

11

T12

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21316

1

T2

176

T3

164

T5

1

auto[1]

5924

1

T1

29

T3

8

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T134	11		T49	13		T143	3
values[0]	5	1			T95	5		-	-		-	-
values[1]	781	1			T3	8		T10	11		T40	24
values[2]	813	1			T13	1		T28	10		T134	8
values[3]	632	1			T12	14		T142	11		T136	7
values[4]	572	1			T5	1		T40	28		T136	11
values[5]	3021	1			T1	29		T8	14		T9	21
values[6]	719	1			T12	11		T88	14		T140	2
values[7]	779	1			T10	12		T13	1		T39	2
values[8]	612	1			T13	1		T161	12		T163	1
values[9]	1008	1			T10	9		T39	38		T28	1
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	839	1			T3	8		T10	11		T13	1
values[1]	777	1			T28	10		T134	8		T143	12
values[2]	575	1			T5	1		T12	14		T142	11
values[3]	3013	1			T1	29		T8	14		T9	21
values[4]	627	1			T88	16		T47	11		T31	16
values[5]	822	1			T12	11		T13	1		T88	14
values[6]	681	1			T10	12		T39	2		T88	10
values[7]	615	1			T13	1		T161	12		T163	1
values[8]	1033	1			T10	9		T39	38		T28	1
values[9]	60	1			T82	13		T224	12		T164	12
minimum	18198	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T40	13		T46	3		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	3		T10	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	1		T162	17		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T28	1		T134	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T12	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T142	11		T41	2		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T1	3		T8	14		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T40	13		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T143	1		T229	9		T185	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T88	1		T47	11		T31	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T48	13		T141	1		T153	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T13	1		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	1		T48	14		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T39	1		T88	1		T46	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T163	1		T144	1		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	1		T161	1		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T10	1		T39	23		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T134	2		T49	13		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T82	8		T164	1		T250	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T224	8		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17983	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T18	3		T256	1		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T40	11		T46	7		T48	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	5		T10	10		T197	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T143	11		T136	6		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T28	9		T134	7		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	13		T41	4		T56	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T41	1		T184	5		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T1	26		T9	19		T26	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	7		T40	15		T211	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T143	14		T229	8		T185	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T88	15		T33	10		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	12		T153	15		T161	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	10		T88	13		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	11		T48	9		T213	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	1		T88	9		T46	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T144	13		T133	12		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T161	11		T184	15		T171	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	8		T39	15		T56	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T134	17		T213	6		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T82	5		T164	11		T250	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T224	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T18	3		T300	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T56	16		T139	6		T82	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T134	1		T49	13		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T95	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T40	13		T46	3		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	3		T10	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T143	1		T162	17		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	1		T28	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T136	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T142	11		T41	2		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	1		T136	1		T41	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T40	13		T137	1		T211	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T1	3		T8	14		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T88	1		T243	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T141	1		T161	1		T42	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T88	1		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T48	27		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T39	1		T88	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T163	1		T144	1		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	1		T161	1		T42	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	1		T39	23		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T134	1		T213	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T56	14		T82	5		T250	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T134	10		T143	2		T224	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T95	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T40	11		T46	7		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T3	5		T10	10		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T143	11		T149	9		T185	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T28	9		T134	7		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	13		T136	6		T56	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	1		T184	5		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T136	10		T41	4		T243	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	15		T211	8		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T1	26		T9	19		T26	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	7		T88	15		T243	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T161	8		T42	3		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	10		T88	13		T33	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	11		T48	21		T213	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	1		T88	9		T46	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T144	13		T133	12		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T161	11		T42	1		T169	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	8		T39	15		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T134	7		T213	6		T144	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T40	13		T46	8		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	8		T10	11		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T143	12		T162	1		T136	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T28	10		T134	8		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T12	14		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T142	1		T41	2		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T1	29		T8	1		T9	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	8		T40	16		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T143	15		T229	9		T185	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T88	16		T47	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	13		T141	1		T153	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	11		T13	1		T88	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	12		T48	10		T213	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T39	2		T88	10		T46	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T163	1		T144	14		T133	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T161	12		T184	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T10	9		T39	17		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T134	19		T49	1		T213	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T82	6		T164	12		T250	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T224	5		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18087	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T18	6		T256	1		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	11		T46	2		T48	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T197	9		T171	10		T257	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T162	16		T149	7		T228	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T139	9		T149	2		T45	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T41	5		T56	11		T221	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T142	10		T41	1		T150	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T8	13		T241	9		T242	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T40	12		T211	9		T20	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T229	8		T185	5		T215	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T47	10		T31	15		T33	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	12		T153	18		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T31	7		T37	1		T20	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	13		T17	4		T151	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T46	2		T47	15		T15	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T133	10		T82	6		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T83	12		T150	16		T171	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T39	21		T56	15		T139	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	12		T133	10		T234	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T82	7		T250	5		T301	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T224	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T142	21		T230	12		T276	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T300	8		T253	6		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T56	15		T139	1		T82	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T134	11		T49	1		T143	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T95	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T40	13		T46	8		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	8		T10	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T143	12		T162	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	1		T28	10		T134	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	14		T136	7		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T142	1		T41	2		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T136	11		T41	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	16		T137	1		T211	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T1	29		T8	1		T9	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	8		T88	16		T243	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T141	1		T161	9		T42	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	11		T88	14		T140	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	12		T48	23		T213	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	1		T39	2		T88	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T163	1		T144	14		T133	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T161	12		T42	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T10	9		T39	17		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T134	8		T213	7		T144	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T56	15		T139	5		T82	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T49	12		T224	7		T302	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T40	11		T46	2		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T197	9		T257	3		T254	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T162	16		T149	7		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T139	9		T149	2		T171	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T56	11		T221	12		T217	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T142	10		T41	1		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T41	5		T139	10		T172	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	12		T211	9		T150	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T8	13		T241	9		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T243	13		T231	10		T259	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	2		T83	3		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	10		T31	22		T33	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	25		T153	18		T17	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	2		T47	15		T15	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T133	10		T82	6		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T169	15		T83	12		T247	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	21		T244	14		T97	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T133	10		T234	16		T228	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23