Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27240

1

T1

29

T2

176

T3

172

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23544

1

T1

29

T2

176

T3

164

auto[ADC_CTRL_FILTER_COND_OUT]

3696

1

T3

8

T5

1

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21165

1

T2

176

T3

172

T6

180

auto[1]

6075

1

T1

29

T5

1

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23088

1

T1

3

T2

176

T3

167

auto[1]

4152

1

T1

26

T3

5

T9

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	253	1			T28	10		T163	1		T56	30
values[0]	33	1			T208	10		T209	1		T220	22
values[1]	782	1			T3	8		T10	9		T46	10
values[2]	597	1			T39	10		T40	15		T140	1
values[3]	748	1			T5	1		T10	12		T40	28
values[4]	3057	1			T1	29		T8	14		T9	21
values[5]	584	1			T12	11		T39	30		T47	11
values[6]	853	1			T88	14		T31	16		T33	23
values[7]	631	1			T12	22		T28	1		T48	9
values[8]	686	1			T13	1		T40	9		T88	10
values[9]	989	1			T10	11		T13	2		T48	23
minimum	18027	1			T2	176		T3	164		T6	180

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T3	8		T10	9		T140	1
values[1]	678	1			T5	1		T39	10		T40	15
values[2]	637	1			T10	12		T40	28		T88	16
values[3]	3066	1			T1	29		T8	14		T9	21
values[4]	560	1			T12	11		T39	2		T31	24
values[5]	906	1			T88	14		T33	23		T48	9
values[6]	699	1			T12	22		T40	9		T88	10
values[7]	622	1			T10	11		T13	1		T48	23
values[8]	919	1			T13	2		T28	10		T49	13
values[9]	139	1			T163	1		T16	4		T83	4
minimum	18183	1			T2	176		T3	164		T6	180

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

4114

1

T8

13

T39

21

T40

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T10	1		T47	16		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	3		T140	1		T48	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T134	1		T141	1		T218	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	1		T39	10		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T88	1		T134	1		T153	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	1		T40	13		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T1	3		T8	14		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	13		T141	1		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	1		T82	7		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	1		T31	24		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T33	13		T48	5		T37	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T88	1		T143	1		T37	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T211	10		T139	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	1		T40	5		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T212	1		T142	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T48	14		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T213	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T13	1		T28	1		T49	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T83	4		T214	1		T175	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T163	1		T16	1		T185	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17960	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T46	3		T234	1		T257	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	8		T143	2		T144	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	5		T48	12		T134	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T134	7		T45	5		T243	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T40	7		T213	6		T197	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T88	15		T134	10		T153	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	11		T40	15		T161	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T1	26		T9	19		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	15		T153	9		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	10		T82	6		T20	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	1		T42	1		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T33	10		T48	4		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T88	13		T143	11		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	7		T211	8		T87	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	13		T40	4		T88	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	10		T82	5		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T48	9		T235	12		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T213	14		T136	10		T138	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	9		T41	1		T56	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T175	10		T216	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T16	3		T185	11		T303	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	1		T32	1		T37	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T46	7		T234	1		T257	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T83	4		T214	1		T172	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T28	1		T163	1		T56	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T208	10		T209	1		T220	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	1		T47	16		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	3		T46	3		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T141	1		T42	4		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T39	10		T40	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T88	1		T134	2		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	1		T10	1		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T1	3		T8	14		T9	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T141	2		T143	1		T169	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T47	11		T82	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	14		T31	8		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T33	13		T146	1		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T88	1		T31	16		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T48	5		T37	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T28	1		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T142	22		T137	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	1		T40	5		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	1		T13	1		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T13	1		T48	14		T49	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17894	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T172	9		T304	12		T305	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T28	9		T56	14		T170	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T220	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	8		T143	2		T144	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	5		T46	7		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	3		T45	5		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	7		T48	12		T197	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T88	15		T134	17		T153	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	11		T40	15		T213	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T1	26		T9	19		T46	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T143	14		T169	16		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	10		T82	6		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	16		T153	9		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T33	10		T149	11		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T88	13		T143	11		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	7		T48	4		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	13		T136	6		T184	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T82	5		T87	9		T171	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	4		T88	9		T151	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	10		T213	14		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T48	9		T41	1		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T32	1		T37	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	9		T47	1		T143	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	8		T140	1		T48	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T134	8		T141	1		T218	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T39	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T88	16		T134	11		T153	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	12		T40	16		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T1	29		T8	1		T9	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T39	16		T141	1		T153	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	11		T82	7		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	2		T31	2		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T33	11		T48	5		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T88	14		T143	12		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	8		T211	9		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	14		T40	5		T88	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	11		T212	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	1		T48	10		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	1		T213	15		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T13	1		T28	10		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T83	1		T214	1		T175	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T163	1		T16	4		T185	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18069	1			T2	176		T3	164		T6	180
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T46	8		T234	2		T257	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	15		T42	2		T148	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	12		T133	10		T229	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T222	10		T223	9		T217	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	9		T40	7		T197	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T153	10		T162	16		T138	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	12		T169	15		T56	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T8	13		T46	2		T47	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	12		T153	8		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T82	6		T20	10		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	22		T226	2		T186	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	12		T48	4		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T37	1		T139	9		T20	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T211	9		T139	10		T87	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	4		T142	10		T20	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T142	21		T82	7		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T48	13		T151	9		T260	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	3		T133	10		T83	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T49	12		T41	1		T56	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T83	3		T175	10		T216	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T185	5		T306	10		T92	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T150	16		T208	9		T295	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T46	2		T257	3		T307	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T83	1		T214	1		T172	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T28	10		T163	1		T56	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T208	1		T209	1		T220	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	9		T47	1		T143	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	8		T46	8		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T141	1		T42	5		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T39	1		T40	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T88	16		T134	19		T153	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T10	12		T40	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T1	29		T8	1		T9	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T141	2		T143	15		T169	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	11		T47	1		T82	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	18		T31	1		T153	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T33	11		T146	1		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T88	14		T31	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	8		T48	5		T37	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	14		T28	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T142	1		T137	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T40	5		T88	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	11		T13	1		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T13	1		T48	10		T49	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18027	1			T2	176		T3	164		T6	180
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T83	3		T172	10		T96	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T56	15		T185	5		T290	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T208	9		T220	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	15		T148	9		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T46	2		T133	10		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T42	2		T230	12		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	9		T40	7		T48	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T153	10		T162	16		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	12		T56	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T8	13		T46	2		T15	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T169	15		T175	12		T240	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T47	10		T82	6		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	12		T31	7		T153	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T33	12		T149	11		T228	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	15		T37	1		T243	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T48	4		T211	9		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T142	10		T139	9		T20	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T142	21		T82	7		T87	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	4		T151	9		T227	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T138	3		T133	10		T83	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T48	13		T49	12		T41	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23126

1

T1

29

T2

176

T3

172

auto[1]

auto[0]

4114

1

T8

13

T39

21

T40

23