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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.19


Total test records in report: 919
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T797 /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1992675101 Jul 13 06:48:18 PM PDT 24 Jul 13 06:49:35 PM PDT 24 36858413665 ps
T273 /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2410320350 Jul 13 06:46:54 PM PDT 24 Jul 13 06:57:11 PM PDT 24 530124251882 ps
T798 /workspace/coverage/default/39.adc_ctrl_lowpower_counter.484664944 Jul 13 06:49:57 PM PDT 24 Jul 13 06:51:28 PM PDT 24 42008732139 ps
T799 /workspace/coverage/default/22.adc_ctrl_poweron_counter.1307726347 Jul 13 06:47:37 PM PDT 24 Jul 13 06:47:42 PM PDT 24 3408991039 ps
T62 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2335992773 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:43 PM PDT 24 531987245 ps
T800 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.346279866 Jul 13 06:44:50 PM PDT 24 Jul 13 06:44:52 PM PDT 24 508438003 ps
T55 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2606270009 Jul 13 06:44:40 PM PDT 24 Jul 13 06:44:42 PM PDT 24 398390352 ps
T52 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3933878346 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:50 PM PDT 24 5181344745 ps
T73 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3603673593 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:42 PM PDT 24 458230116 ps
T801 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3898119516 Jul 13 06:44:57 PM PDT 24 Jul 13 06:44:59 PM PDT 24 545723785 ps
T53 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.69108383 Jul 13 06:44:25 PM PDT 24 Jul 13 06:44:33 PM PDT 24 5582768691 ps
T802 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1550140687 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:51 PM PDT 24 350444357 ps
T72 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.912690576 Jul 13 06:44:51 PM PDT 24 Jul 13 06:44:54 PM PDT 24 371651268 ps
T112 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3057860354 Jul 13 06:44:37 PM PDT 24 Jul 13 06:44:39 PM PDT 24 1299393093 ps
T67 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3515847612 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:45 PM PDT 24 1324437495 ps
T803 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3193305951 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:51 PM PDT 24 520705385 ps
T804 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2951689942 Jul 13 06:44:54 PM PDT 24 Jul 13 06:44:56 PM PDT 24 302601026 ps
T127 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3245265590 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:49 PM PDT 24 512285173 ps
T132 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.565888089 Jul 13 06:44:34 PM PDT 24 Jul 13 06:44:36 PM PDT 24 673522951 ps
T57 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3460559052 Jul 13 06:44:29 PM PDT 24 Jul 13 06:44:34 PM PDT 24 4478779071 ps
T68 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3135515263 Jul 13 06:44:43 PM PDT 24 Jul 13 06:44:48 PM PDT 24 375877644 ps
T128 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3287091714 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:52 PM PDT 24 2580397842 ps
T805 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2223620484 Jul 13 06:44:50 PM PDT 24 Jul 13 06:44:53 PM PDT 24 487300526 ps
T806 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1068792576 Jul 13 06:44:50 PM PDT 24 Jul 13 06:44:53 PM PDT 24 530129664 ps
T129 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.313624611 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:49 PM PDT 24 565570050 ps
T69 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2779633009 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:46 PM PDT 24 453265491 ps
T807 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2155110254 Jul 13 06:44:49 PM PDT 24 Jul 13 06:44:52 PM PDT 24 389826732 ps
T99 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2703087369 Jul 13 06:44:26 PM PDT 24 Jul 13 06:44:29 PM PDT 24 470616770 ps
T100 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2738660972 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:45 PM PDT 24 518847262 ps
T90 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3674206819 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:42 PM PDT 24 625091464 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.349884758 Jul 13 06:44:33 PM PDT 24 Jul 13 06:44:35 PM PDT 24 1262104729 ps
T58 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3624957210 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:48 PM PDT 24 4436756533 ps
T114 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.442829249 Jul 13 06:44:40 PM PDT 24 Jul 13 06:44:43 PM PDT 24 430548478 ps
T808 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4007390805 Jul 13 06:44:37 PM PDT 24 Jul 13 06:44:40 PM PDT 24 438320799 ps
T809 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3551712975 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:44 PM PDT 24 404787181 ps
T115 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.415525998 Jul 13 06:44:25 PM PDT 24 Jul 13 06:44:30 PM PDT 24 859511815 ps
T810 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1692222743 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:01 PM PDT 24 507132037 ps
T811 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.153926128 Jul 13 06:44:26 PM PDT 24 Jul 13 06:44:28 PM PDT 24 373500706 ps
T59 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.827617967 Jul 13 06:44:38 PM PDT 24 Jul 13 06:44:44 PM PDT 24 8703648403 ps
T812 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3610995747 Jul 13 06:44:38 PM PDT 24 Jul 13 06:44:39 PM PDT 24 445139811 ps
T130 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1482955903 Jul 13 06:44:44 PM PDT 24 Jul 13 06:44:47 PM PDT 24 381017243 ps
T54 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3625374149 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:48 PM PDT 24 4597806086 ps
T116 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3508616196 Jul 13 06:44:49 PM PDT 24 Jul 13 06:44:52 PM PDT 24 592314865 ps
T74 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.385639111 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:49 PM PDT 24 8765130556 ps
T131 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4081315763 Jul 13 06:44:36 PM PDT 24 Jul 13 06:44:38 PM PDT 24 437289257 ps
T813 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2118504628 Jul 13 06:44:49 PM PDT 24 Jul 13 06:44:52 PM PDT 24 568950570 ps
T117 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2573872845 Jul 13 06:44:44 PM PDT 24 Jul 13 06:44:47 PM PDT 24 331056159 ps
T814 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1591905794 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:52 PM PDT 24 2661147204 ps
T815 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3769312617 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:46 PM PDT 24 1310929272 ps
T816 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2955926816 Jul 13 06:45:01 PM PDT 24 Jul 13 06:45:03 PM PDT 24 351138795 ps
T817 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.63300998 Jul 13 06:44:54 PM PDT 24 Jul 13 06:44:56 PM PDT 24 475181080 ps
T328 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1731513858 Jul 13 06:44:42 PM PDT 24 Jul 13 06:45:04 PM PDT 24 8338578892 ps
T818 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1270606373 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:44 PM PDT 24 407485297 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.295851630 Jul 13 06:44:33 PM PDT 24 Jul 13 06:44:35 PM PDT 24 347668949 ps
T119 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3598151737 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:50 PM PDT 24 438964233 ps
T819 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3202249057 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:50 PM PDT 24 509707876 ps
T820 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2986893347 Jul 13 06:44:49 PM PDT 24 Jul 13 06:44:53 PM PDT 24 586634345 ps
T70 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1736627810 Jul 13 06:44:59 PM PDT 24 Jul 13 06:45:03 PM PDT 24 753648622 ps
T821 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.820206884 Jul 13 06:44:52 PM PDT 24 Jul 13 06:44:54 PM PDT 24 505798060 ps
T329 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3042620180 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:52 PM PDT 24 8866157050 ps
T822 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1582021803 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:48 PM PDT 24 352965315 ps
T823 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2517461851 Jul 13 06:44:27 PM PDT 24 Jul 13 06:44:29 PM PDT 24 336275799 ps
T824 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.191290527 Jul 13 06:44:48 PM PDT 24 Jul 13 06:44:52 PM PDT 24 444790478 ps
T825 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2025950148 Jul 13 06:44:31 PM PDT 24 Jul 13 06:44:33 PM PDT 24 524944260 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.700673810 Jul 13 06:44:44 PM PDT 24 Jul 13 06:44:48 PM PDT 24 517988252 ps
T827 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.358114278 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:51 PM PDT 24 415783092 ps
T828 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2603824936 Jul 13 06:44:46 PM PDT 24 Jul 13 06:44:51 PM PDT 24 5392399438 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3532897976 Jul 13 06:44:44 PM PDT 24 Jul 13 06:44:49 PM PDT 24 460456152 ps
T830 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1338629717 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:49 PM PDT 24 413693782 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1189145579 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:43 PM PDT 24 430689993 ps
T832 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.178803908 Jul 13 06:44:40 PM PDT 24 Jul 13 06:44:42 PM PDT 24 406208334 ps
T833 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.932916951 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:48 PM PDT 24 505497847 ps
T834 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.133178188 Jul 13 06:44:25 PM PDT 24 Jul 13 06:44:28 PM PDT 24 508037960 ps
T835 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3557070345 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:45 PM PDT 24 316651823 ps
T120 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3955173647 Jul 13 06:44:43 PM PDT 24 Jul 13 06:44:46 PM PDT 24 463467272 ps
T836 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.422530384 Jul 13 06:44:27 PM PDT 24 Jul 13 06:44:30 PM PDT 24 500156972 ps
T837 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2435573033 Jul 13 06:44:54 PM PDT 24 Jul 13 06:44:57 PM PDT 24 455391713 ps
T838 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3770755441 Jul 13 06:44:46 PM PDT 24 Jul 13 06:44:54 PM PDT 24 2570123400 ps
T75 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2561654912 Jul 13 06:44:33 PM PDT 24 Jul 13 06:44:45 PM PDT 24 4147163220 ps
T125 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.786206713 Jul 13 06:44:40 PM PDT 24 Jul 13 06:44:43 PM PDT 24 492879194 ps
T121 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3390162126 Jul 13 06:44:26 PM PDT 24 Jul 13 06:44:28 PM PDT 24 536616302 ps
T839 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4113300775 Jul 13 06:44:30 PM PDT 24 Jul 13 06:44:32 PM PDT 24 485841849 ps
T122 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1223520048 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:41 PM PDT 24 441218583 ps
T840 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2698272232 Jul 13 06:44:51 PM PDT 24 Jul 13 06:44:54 PM PDT 24 504496609 ps
T841 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.74540859 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:50 PM PDT 24 396387533 ps
T842 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.136031498 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:43 PM PDT 24 750064759 ps
T843 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4272916720 Jul 13 06:44:49 PM PDT 24 Jul 13 06:44:52 PM PDT 24 343909152 ps
T844 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2326651042 Jul 13 06:44:48 PM PDT 24 Jul 13 06:44:51 PM PDT 24 328837877 ps
T845 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3711495996 Jul 13 06:44:43 PM PDT 24 Jul 13 06:44:47 PM PDT 24 1199473115 ps
T846 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1567057970 Jul 13 06:44:43 PM PDT 24 Jul 13 06:44:47 PM PDT 24 670876684 ps
T847 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1996288372 Jul 13 06:44:28 PM PDT 24 Jul 13 06:44:31 PM PDT 24 1349378326 ps
T848 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1006071628 Jul 13 06:44:46 PM PDT 24 Jul 13 06:44:49 PM PDT 24 393541810 ps
T330 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.80522179 Jul 13 06:44:37 PM PDT 24 Jul 13 06:44:45 PM PDT 24 8872886766 ps
T849 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4024171404 Jul 13 06:44:46 PM PDT 24 Jul 13 06:44:57 PM PDT 24 4289326711 ps
T850 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.779631067 Jul 13 06:44:53 PM PDT 24 Jul 13 06:44:55 PM PDT 24 321828301 ps
T851 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2478412133 Jul 13 06:44:43 PM PDT 24 Jul 13 06:45:01 PM PDT 24 4442935832 ps
T852 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1839126911 Jul 13 06:44:46 PM PDT 24 Jul 13 06:44:59 PM PDT 24 4173339465 ps
T853 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4012648702 Jul 13 06:44:48 PM PDT 24 Jul 13 06:44:51 PM PDT 24 478240633 ps
T854 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3570990956 Jul 13 06:44:37 PM PDT 24 Jul 13 06:44:45 PM PDT 24 2401132393 ps
T855 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4012850541 Jul 13 06:44:52 PM PDT 24 Jul 13 06:44:55 PM PDT 24 291329221 ps
T856 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.60835383 Jul 13 06:44:43 PM PDT 24 Jul 13 06:44:53 PM PDT 24 2037841705 ps
T123 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.428032688 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:46 PM PDT 24 792471577 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2274101045 Jul 13 06:44:26 PM PDT 24 Jul 13 06:44:28 PM PDT 24 1052131472 ps
T858 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.967558322 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:41 PM PDT 24 424370307 ps
T124 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.180992573 Jul 13 06:44:44 PM PDT 24 Jul 13 06:44:48 PM PDT 24 567199225 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.766245524 Jul 13 06:44:37 PM PDT 24 Jul 13 06:44:39 PM PDT 24 386640415 ps
T860 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.379290444 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:45 PM PDT 24 352817305 ps
T861 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.712390846 Jul 13 06:44:43 PM PDT 24 Jul 13 06:44:47 PM PDT 24 444745474 ps
T126 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1374812525 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:49 PM PDT 24 419328781 ps
T862 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.286127763 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:42 PM PDT 24 408848777 ps
T863 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1295221948 Jul 13 06:44:34 PM PDT 24 Jul 13 06:44:40 PM PDT 24 4675946968 ps
T864 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.689603153 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:43 PM PDT 24 357926599 ps
T865 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.398319457 Jul 13 06:44:53 PM PDT 24 Jul 13 06:44:58 PM PDT 24 5535339351 ps
T866 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3384073063 Jul 13 06:44:43 PM PDT 24 Jul 13 06:45:01 PM PDT 24 4780204945 ps
T867 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4041027342 Jul 13 06:44:52 PM PDT 24 Jul 13 06:44:54 PM PDT 24 298159154 ps
T868 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2739750771 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:01 PM PDT 24 539371535 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3846437386 Jul 13 06:44:30 PM PDT 24 Jul 13 06:44:33 PM PDT 24 574723897 ps
T870 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.67324904 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:45 PM PDT 24 2155614252 ps
T871 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2392410666 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:43 PM PDT 24 452835136 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2924452786 Jul 13 06:44:32 PM PDT 24 Jul 13 06:44:47 PM PDT 24 4454239310 ps
T873 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2929499754 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:51 PM PDT 24 4216666768 ps
T874 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.56452425 Jul 13 06:44:46 PM PDT 24 Jul 13 06:44:50 PM PDT 24 495394738 ps
T875 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.670227145 Jul 13 06:44:54 PM PDT 24 Jul 13 06:44:56 PM PDT 24 2155048097 ps
T876 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2285292481 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:51 PM PDT 24 515637147 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4158229846 Jul 13 06:44:31 PM PDT 24 Jul 13 06:44:34 PM PDT 24 4399808691 ps
T878 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2353130024 Jul 13 06:44:46 PM PDT 24 Jul 13 06:44:50 PM PDT 24 356258961 ps
T879 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1663282500 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:51 PM PDT 24 448961009 ps
T880 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.271191612 Jul 13 06:44:46 PM PDT 24 Jul 13 06:45:10 PM PDT 24 8192338537 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1896040849 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:44 PM PDT 24 2492210245 ps
T76 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1002317328 Jul 13 06:44:46 PM PDT 24 Jul 13 06:45:11 PM PDT 24 8186293420 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1218840738 Jul 13 06:44:40 PM PDT 24 Jul 13 06:44:43 PM PDT 24 413791667 ps
T883 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1825185177 Jul 13 06:44:54 PM PDT 24 Jul 13 06:45:06 PM PDT 24 4270728801 ps
T331 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2402033063 Jul 13 06:44:36 PM PDT 24 Jul 13 06:44:59 PM PDT 24 8680640490 ps
T884 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2406729933 Jul 13 06:44:44 PM PDT 24 Jul 13 06:44:49 PM PDT 24 897857619 ps
T885 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3842512192 Jul 13 06:44:38 PM PDT 24 Jul 13 06:44:41 PM PDT 24 422435960 ps
T886 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1353088453 Jul 13 06:44:27 PM PDT 24 Jul 13 06:44:47 PM PDT 24 9430980589 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2385628597 Jul 13 06:44:40 PM PDT 24 Jul 13 06:44:42 PM PDT 24 529841862 ps
T888 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.815846832 Jul 13 06:44:48 PM PDT 24 Jul 13 06:44:52 PM PDT 24 489619401 ps
T889 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3174445542 Jul 13 06:44:34 PM PDT 24 Jul 13 06:44:36 PM PDT 24 304325302 ps
T890 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.598771178 Jul 13 06:44:43 PM PDT 24 Jul 13 06:44:47 PM PDT 24 517748719 ps
T891 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.961636601 Jul 13 06:44:41 PM PDT 24 Jul 13 06:44:45 PM PDT 24 480475446 ps
T892 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3493855095 Jul 13 06:44:27 PM PDT 24 Jul 13 06:44:32 PM PDT 24 489424141 ps
T893 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2521127350 Jul 13 06:44:43 PM PDT 24 Jul 13 06:45:07 PM PDT 24 8681563916 ps
T894 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1529144498 Jul 13 06:44:40 PM PDT 24 Jul 13 06:44:52 PM PDT 24 4968412342 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4141154459 Jul 13 06:44:38 PM PDT 24 Jul 13 06:45:04 PM PDT 24 24289278848 ps
T896 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1133270381 Jul 13 06:45:00 PM PDT 24 Jul 13 06:45:04 PM PDT 24 458017270 ps
T897 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.962689833 Jul 13 06:44:49 PM PDT 24 Jul 13 06:44:52 PM PDT 24 321465665 ps
T898 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1392733114 Jul 13 06:44:50 PM PDT 24 Jul 13 06:44:52 PM PDT 24 374100699 ps
T899 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1945314652 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:51 PM PDT 24 403340565 ps
T900 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1494202893 Jul 13 06:44:45 PM PDT 24 Jul 13 06:44:48 PM PDT 24 342549745 ps
T901 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4292842151 Jul 13 06:44:25 PM PDT 24 Jul 13 06:44:30 PM PDT 24 4862434894 ps
T902 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2862951282 Jul 13 06:44:26 PM PDT 24 Jul 13 06:44:29 PM PDT 24 519642643 ps
T903 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1940276029 Jul 13 06:44:39 PM PDT 24 Jul 13 06:44:47 PM PDT 24 8783143829 ps
T904 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4061524068 Jul 13 06:44:53 PM PDT 24 Jul 13 06:44:54 PM PDT 24 391914600 ps
T905 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.273306512 Jul 13 06:44:58 PM PDT 24 Jul 13 06:45:00 PM PDT 24 388942521 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4278315275 Jul 13 06:44:37 PM PDT 24 Jul 13 06:44:42 PM PDT 24 605085368 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2045624260 Jul 13 06:44:31 PM PDT 24 Jul 13 06:45:05 PM PDT 24 25806815121 ps
T908 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1525990870 Jul 13 06:44:47 PM PDT 24 Jul 13 06:44:51 PM PDT 24 539416056 ps
T909 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.547560843 Jul 13 06:44:43 PM PDT 24 Jul 13 06:45:06 PM PDT 24 8735822238 ps
T910 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3414928049 Jul 13 06:44:27 PM PDT 24 Jul 13 06:44:32 PM PDT 24 5583329879 ps
T911 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.418956453 Jul 13 06:44:42 PM PDT 24 Jul 13 06:44:45 PM PDT 24 655380192 ps
T912 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1946332785 Jul 13 06:44:51 PM PDT 24 Jul 13 06:44:53 PM PDT 24 319345566 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2468672951 Jul 13 06:44:31 PM PDT 24 Jul 13 06:44:35 PM PDT 24 566566863 ps
T914 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1837260241 Jul 13 06:44:27 PM PDT 24 Jul 13 06:44:29 PM PDT 24 687543008 ps
T915 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3508170520 Jul 13 06:44:33 PM PDT 24 Jul 13 06:45:29 PM PDT 24 26497703053 ps
T916 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3795869266 Jul 13 06:44:30 PM PDT 24 Jul 13 06:45:08 PM PDT 24 30311224835 ps
T917 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1789256608 Jul 13 06:44:45 PM PDT 24 Jul 13 06:45:04 PM PDT 24 7952368571 ps
T918 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2960643255 Jul 13 06:44:51 PM PDT 24 Jul 13 06:44:53 PM PDT 24 486229877 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2203934738 Jul 13 06:44:33 PM PDT 24 Jul 13 06:44:35 PM PDT 24 502214677 ps

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3934341899
Short name T3
Test name
Test status
Simulation time 231211818372 ps
CPU time 394.52 seconds
Started Jul 13 06:50:30 PM PDT 24
Finished Jul 13 06:57:05 PM PDT 24
Peak memory 210596 kb
Host smart-be1390d3-4ae1-4c91-b4b2-6adede391d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934341899 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3934341899
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4251990190
Short name T40
Test name
Test status
Simulation time 617578694480 ps
CPU time 1299.48 seconds
Started Jul 13 06:51:25 PM PDT 24
Finished Jul 13 07:13:05 PM PDT 24
Peak memory 201912 kb
Host smart-0b724c6f-1747-4228-aa16-6a446a53dd43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251990190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4251990190
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1574675080
Short name T15
Test name
Test status
Simulation time 164836488576 ps
CPU time 370.53 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:53:28 PM PDT 24
Peak memory 210588 kb
Host smart-bc9d06c2-eacb-4a6c-88dd-249f3711eeb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574675080 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1574675080
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1643675991
Short name T41
Test name
Test status
Simulation time 420818815234 ps
CPU time 635.82 seconds
Started Jul 13 06:49:06 PM PDT 24
Finished Jul 13 06:59:42 PM PDT 24
Peak memory 211544 kb
Host smart-bde75ecf-1087-42e2-b1e8-b2feffe0ae88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643675991 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1643675991
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2495607770
Short name T20
Test name
Test status
Simulation time 1216531721384 ps
CPU time 502.74 seconds
Started Jul 13 06:47:04 PM PDT 24
Finished Jul 13 06:55:27 PM PDT 24
Peak memory 210536 kb
Host smart-f70327b9-6843-46d0-8261-20a2380e314c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495607770 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2495607770
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.320499798
Short name T48
Test name
Test status
Simulation time 540489615932 ps
CPU time 569.82 seconds
Started Jul 13 06:51:03 PM PDT 24
Finished Jul 13 07:00:33 PM PDT 24
Peak memory 201824 kb
Host smart-0d1175f5-88c1-4752-9cfa-0bc0097747e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320499798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.320499798
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2282718144
Short name T138
Test name
Test status
Simulation time 516956343773 ps
CPU time 603.81 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:56:56 PM PDT 24
Peak memory 201992 kb
Host smart-c1ea3030-3bf9-41c9-b5eb-c63121468290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282718144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2282718144
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2015410618
Short name T143
Test name
Test status
Simulation time 492150586181 ps
CPU time 231.34 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:52:02 PM PDT 24
Peak memory 201904 kb
Host smart-ec14b090-a49f-4158-ad9a-c007852c562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015410618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2015410618
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.555803619
Short name T56
Test name
Test status
Simulation time 358327624120 ps
CPU time 112.94 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:48:49 PM PDT 24
Peak memory 201916 kb
Host smart-3b791cc5-af18-4ae6-a23d-2b44e682559e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555803619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.555803619
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1097704652
Short name T149
Test name
Test status
Simulation time 608059476846 ps
CPU time 398.07 seconds
Started Jul 13 06:48:11 PM PDT 24
Finished Jul 13 06:54:50 PM PDT 24
Peak memory 201952 kb
Host smart-615f336c-71f8-4b6b-bfcf-2ccec99e93c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097704652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1097704652
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2779633009
Short name T69
Test name
Test status
Simulation time 453265491 ps
CPU time 2.58 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:46 PM PDT 24
Peak memory 217660 kb
Host smart-f69f8cca-1075-4f2c-81b8-c295386b324f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779633009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2779633009
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2021669877
Short name T221
Test name
Test status
Simulation time 682060349142 ps
CPU time 838.57 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 201968 kb
Host smart-76f42b16-1253-4673-bdcd-b5cf9e8507fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021669877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2021669877
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.812415582
Short name T39
Test name
Test status
Simulation time 511218929768 ps
CPU time 542.18 seconds
Started Jul 13 06:47:24 PM PDT 24
Finished Jul 13 06:56:26 PM PDT 24
Peak memory 201972 kb
Host smart-92ce19b5-d124-4bbf-b7d3-f4eeba05e66b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812415582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.812415582
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3776408700
Short name T63
Test name
Test status
Simulation time 7869522050 ps
CPU time 3.25 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:46:53 PM PDT 24
Peak memory 218224 kb
Host smart-97b959d1-515d-4e7b-b85a-f1b6e9cd4cad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776408700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3776408700
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.157487481
Short name T9
Test name
Test status
Simulation time 327571975293 ps
CPU time 205.02 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:50:04 PM PDT 24
Peak memory 201884 kb
Host smart-802b68e9-6f7f-4520-8d92-ff81e223e169
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=157487481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.157487481
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2616978765
Short name T175
Test name
Test status
Simulation time 526109691537 ps
CPU time 209.86 seconds
Started Jul 13 06:49:12 PM PDT 24
Finished Jul 13 06:52:42 PM PDT 24
Peak memory 201912 kb
Host smart-7bef8cd0-39b2-4d75-9d84-9ddcf06a66d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616978765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2616978765
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2970029369
Short name T243
Test name
Test status
Simulation time 487760195979 ps
CPU time 346.43 seconds
Started Jul 13 06:47:11 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 201864 kb
Host smart-9622edf6-721b-4593-a351-7ea2929b4d18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970029369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2970029369
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2573872845
Short name T117
Test name
Test status
Simulation time 331056159 ps
CPU time 1.18 seconds
Started Jul 13 06:44:44 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 201476 kb
Host smart-6513d26f-36ba-4321-ac69-1cba5cbf9478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573872845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2573872845
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1514264962
Short name T82
Test name
Test status
Simulation time 342225279504 ps
CPU time 669.28 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:59:05 PM PDT 24
Peak memory 201912 kb
Host smart-0c72bf0e-e339-49a4-8750-d47be1cb6220
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514264962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1514264962
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1274664540
Short name T217
Test name
Test status
Simulation time 496094064336 ps
CPU time 600.3 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:56:42 PM PDT 24
Peak memory 201892 kb
Host smart-84c03c58-7616-4233-9371-06dc965e9a7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274664540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1274664540
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1612119134
Short name T47
Test name
Test status
Simulation time 342581345779 ps
CPU time 555.7 seconds
Started Jul 13 06:48:11 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 201960 kb
Host smart-4f7bbc61-3156-493d-a5e5-c9084a581f3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612119134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1612119134
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2320930111
Short name T257
Test name
Test status
Simulation time 294112780628 ps
CPU time 469.05 seconds
Started Jul 13 06:51:31 PM PDT 24
Finished Jul 13 06:59:20 PM PDT 24
Peak memory 210632 kb
Host smart-97e080a8-031a-4366-9814-bb62a9efa9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320930111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2320930111
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.107480941
Short name T185
Test name
Test status
Simulation time 375944680326 ps
CPU time 207.86 seconds
Started Jul 13 06:48:31 PM PDT 24
Finished Jul 13 06:52:00 PM PDT 24
Peak memory 202008 kb
Host smart-90bbb182-258e-4543-b696-776998d58aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107480941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.107480941
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.791123484
Short name T171
Test name
Test status
Simulation time 367380965455 ps
CPU time 863.26 seconds
Started Jul 13 06:49:49 PM PDT 24
Finished Jul 13 07:04:13 PM PDT 24
Peak memory 201912 kb
Host smart-c0b73ebe-29fb-4417-9b86-e0a67290f7dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791123484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.791123484
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4264767992
Short name T208
Test name
Test status
Simulation time 376143896528 ps
CPU time 801.49 seconds
Started Jul 13 06:47:59 PM PDT 24
Finished Jul 13 07:01:21 PM PDT 24
Peak memory 201892 kb
Host smart-8c0382a0-6abd-43f2-b005-aedf1e6439cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264767992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4264767992
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2920729417
Short name T289
Test name
Test status
Simulation time 336080778335 ps
CPU time 370.19 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 06:57:19 PM PDT 24
Peak memory 201912 kb
Host smart-973c966a-896c-4471-9552-12e27e96d677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920729417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2920729417
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2866411971
Short name T256
Test name
Test status
Simulation time 324657216885 ps
CPU time 129.59 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:49:20 PM PDT 24
Peak memory 201988 kb
Host smart-841d15ad-8059-43a7-82e0-706036bb4ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866411971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2866411971
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4086050998
Short name T29
Test name
Test status
Simulation time 427689433 ps
CPU time 0.91 seconds
Started Jul 13 06:46:50 PM PDT 24
Finished Jul 13 06:46:51 PM PDT 24
Peak memory 201672 kb
Host smart-de15a78c-6ce4-4407-b690-c3ed08c8a717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086050998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4086050998
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3878351655
Short name T89
Test name
Test status
Simulation time 192397762664 ps
CPU time 184.65 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:50:15 PM PDT 24
Peak memory 210532 kb
Host smart-50bd572d-be0e-4407-8ba9-d9bc63d39bc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878351655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3878351655
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.80522179
Short name T330
Test name
Test status
Simulation time 8872886766 ps
CPU time 8.1 seconds
Started Jul 13 06:44:37 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201776 kb
Host smart-b0ed1da1-fd62-435a-bb79-312808387a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80522179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg
_err.80522179
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.767306472
Short name T133
Test name
Test status
Simulation time 339758833116 ps
CPU time 679.35 seconds
Started Jul 13 06:47:03 PM PDT 24
Finished Jul 13 06:58:23 PM PDT 24
Peak memory 201924 kb
Host smart-721fcede-1eff-4db0-9efd-cf59c952936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767306472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.767306472
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1990720232
Short name T246
Test name
Test status
Simulation time 353431635683 ps
CPU time 835.32 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 07:01:10 PM PDT 24
Peak memory 201992 kb
Host smart-1b5e8e3d-0055-45a8-bc85-02f707ffde2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990720232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1990720232
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3010379684
Short name T269
Test name
Test status
Simulation time 491019816296 ps
CPU time 1066.01 seconds
Started Jul 13 06:47:10 PM PDT 24
Finished Jul 13 07:04:57 PM PDT 24
Peak memory 201976 kb
Host smart-c23c848a-9525-4ccb-9c65-6f382c477fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010379684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3010379684
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.116401018
Short name T290
Test name
Test status
Simulation time 172447493243 ps
CPU time 75.71 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:49:32 PM PDT 24
Peak memory 201916 kb
Host smart-6eba640a-0189-4ee2-b33c-f939c4691578
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116401018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.116401018
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1259712435
Short name T45
Test name
Test status
Simulation time 321731035022 ps
CPU time 347.67 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:56:49 PM PDT 24
Peak memory 210536 kb
Host smart-e05a6aea-4f00-4a5c-b81d-8b5ae2b72e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259712435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1259712435
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2070268439
Short name T153
Test name
Test status
Simulation time 344745543206 ps
CPU time 744.63 seconds
Started Jul 13 06:46:45 PM PDT 24
Finished Jul 13 06:59:10 PM PDT 24
Peak memory 201892 kb
Host smart-e7568127-9e19-4e1d-8024-bc0bb4d39bc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070268439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2070268439
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2609579596
Short name T306
Test name
Test status
Simulation time 630418642372 ps
CPU time 680.34 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:58:31 PM PDT 24
Peak memory 201880 kb
Host smart-25f00794-1c52-4062-adca-b72099d30977
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609579596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2609579596
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1778728064
Short name T172
Test name
Test status
Simulation time 504306661920 ps
CPU time 228.08 seconds
Started Jul 13 06:47:47 PM PDT 24
Finished Jul 13 06:51:36 PM PDT 24
Peak memory 201888 kb
Host smart-313f025b-2d4b-405e-a667-164401f6e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778728064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1778728064
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3933878346
Short name T52
Test name
Test status
Simulation time 5181344745 ps
CPU time 9.48 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:50 PM PDT 24
Peak memory 201848 kb
Host smart-4d5b7056-58d2-4942-9c51-de4fdad973d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933878346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3933878346
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.280244999
Short name T261
Test name
Test status
Simulation time 311962104605 ps
CPU time 750.24 seconds
Started Jul 13 06:47:18 PM PDT 24
Finished Jul 13 06:59:49 PM PDT 24
Peak memory 202184 kb
Host smart-d9c3902d-456e-4b9a-bdc3-0261a8f14017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280244999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
280244999
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.513021944
Short name T267
Test name
Test status
Simulation time 369703623377 ps
CPU time 352.91 seconds
Started Jul 13 06:48:45 PM PDT 24
Finished Jul 13 06:54:39 PM PDT 24
Peak memory 201932 kb
Host smart-5ae4b40b-ef25-4ea9-ac74-f410e7027eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513021944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
513021944
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1171434081
Short name T166
Test name
Test status
Simulation time 510572205637 ps
CPU time 196.88 seconds
Started Jul 13 06:51:12 PM PDT 24
Finished Jul 13 06:54:30 PM PDT 24
Peak memory 201876 kb
Host smart-e5a1a029-d044-493b-82d7-1e8f741d70cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171434081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1171434081
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.760762838
Short name T282
Test name
Test status
Simulation time 322651260807 ps
CPU time 360.41 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:52:59 PM PDT 24
Peak memory 201968 kb
Host smart-bca8ad79-277f-4c18-aa58-5af964c9f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760762838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.760762838
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4208662419
Short name T276
Test name
Test status
Simulation time 162005397246 ps
CPU time 98.93 seconds
Started Jul 13 06:47:23 PM PDT 24
Finished Jul 13 06:49:03 PM PDT 24
Peak memory 201828 kb
Host smart-923bda11-acac-43f1-ba42-40dd949ed9a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208662419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4208662419
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.909203802
Short name T213
Test name
Test status
Simulation time 328843355462 ps
CPU time 696.8 seconds
Started Jul 13 06:50:04 PM PDT 24
Finished Jul 13 07:01:41 PM PDT 24
Peak memory 201928 kb
Host smart-82b057b3-be0e-4459-a09d-39ffe324b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909203802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.909203802
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2314485765
Short name T327
Test name
Test status
Simulation time 393739318342 ps
CPU time 859.53 seconds
Started Jul 13 06:49:03 PM PDT 24
Finished Jul 13 07:03:23 PM PDT 24
Peak memory 210500 kb
Host smart-6b451f8d-8d23-4c08-bf06-d05329d82f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314485765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2314485765
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2082723713
Short name T356
Test name
Test status
Simulation time 197992538599 ps
CPU time 428.35 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:54:24 PM PDT 24
Peak memory 201892 kb
Host smart-fd76b2a1-2466-474a-b12d-e97941fa671b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082723713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2082723713
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3384983590
Short name T291
Test name
Test status
Simulation time 82025598748 ps
CPU time 175.91 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:50:13 PM PDT 24
Peak memory 218044 kb
Host smart-2bc291ce-aae3-4945-9254-946ec597c0f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384983590 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3384983590
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.343747626
Short name T224
Test name
Test status
Simulation time 165952657979 ps
CPU time 42.35 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:52 PM PDT 24
Peak memory 201924 kb
Host smart-897b78f7-ee87-47fd-91b3-e87e8720bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343747626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.343747626
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4098633582
Short name T14
Test name
Test status
Simulation time 99451232461 ps
CPU time 542.97 seconds
Started Jul 13 06:47:30 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 202184 kb
Host smart-284425cf-0e7b-4cc0-9226-faf979c7f5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098633582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4098633582
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.266993073
Short name T264
Test name
Test status
Simulation time 352431644567 ps
CPU time 778.21 seconds
Started Jul 13 06:46:55 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 201924 kb
Host smart-7502613b-9ed1-4e56-9a1c-94e471c2dde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266993073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.266993073
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1377918827
Short name T278
Test name
Test status
Simulation time 528252549883 ps
CPU time 1165.55 seconds
Started Jul 13 06:48:21 PM PDT 24
Finished Jul 13 07:07:48 PM PDT 24
Peak memory 201912 kb
Host smart-e6f7bcf8-c22f-4d7e-80e2-8591ec33670a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377918827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1377918827
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1509501327
Short name T95
Test name
Test status
Simulation time 492908578576 ps
CPU time 227.54 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:54:50 PM PDT 24
Peak memory 201968 kb
Host smart-cf9a2f67-5e71-4ed6-a224-5d22f7aa8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509501327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1509501327
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.524605999
Short name T294
Test name
Test status
Simulation time 165169561858 ps
CPU time 116.39 seconds
Started Jul 13 06:51:21 PM PDT 24
Finished Jul 13 06:53:18 PM PDT 24
Peak memory 201948 kb
Host smart-9769eef1-8e9f-46ed-9c44-4c3d2e379e3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524605999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.524605999
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3442823048
Short name T207
Test name
Test status
Simulation time 177819113591 ps
CPU time 54.76 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:48:14 PM PDT 24
Peak memory 201912 kb
Host smart-385db360-3a2f-466e-91c5-03332b2c0330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442823048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3442823048
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.4061622099
Short name T271
Test name
Test status
Simulation time 331456194787 ps
CPU time 722.69 seconds
Started Jul 13 06:47:27 PM PDT 24
Finished Jul 13 06:59:30 PM PDT 24
Peak memory 202004 kb
Host smart-731560f5-e95f-4ac9-8c33-1c7ec9af0ca4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061622099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.4061622099
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.155009551
Short name T150
Test name
Test status
Simulation time 582601575155 ps
CPU time 111.34 seconds
Started Jul 13 06:49:58 PM PDT 24
Finished Jul 13 06:51:49 PM PDT 24
Peak memory 201916 kb
Host smart-deae6445-048e-4fef-abb9-b2072c0944fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155009551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.155009551
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1863409751
Short name T253
Test name
Test status
Simulation time 639684787834 ps
CPU time 1358.97 seconds
Started Jul 13 06:51:03 PM PDT 24
Finished Jul 13 07:13:43 PM PDT 24
Peak memory 201928 kb
Host smart-f6956b23-54ea-4a6f-8f98-9b79041bfbd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863409751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1863409751
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2639705388
Short name T216
Test name
Test status
Simulation time 556735769885 ps
CPU time 580.21 seconds
Started Jul 13 06:46:52 PM PDT 24
Finished Jul 13 06:56:33 PM PDT 24
Peak memory 201908 kb
Host smart-25f498c9-3764-46d4-9fe0-629ec6006016
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639705388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2639705388
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2410320350
Short name T273
Test name
Test status
Simulation time 530124251882 ps
CPU time 616.45 seconds
Started Jul 13 06:46:54 PM PDT 24
Finished Jul 13 06:57:11 PM PDT 24
Peak memory 201928 kb
Host smart-e6095d0f-3ddb-4169-a3a9-ac2198744653
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410320350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2410320350
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1760952254
Short name T233
Test name
Test status
Simulation time 484141328240 ps
CPU time 514.13 seconds
Started Jul 13 06:47:04 PM PDT 24
Finished Jul 13 06:55:39 PM PDT 24
Peak memory 201892 kb
Host smart-daf6bdfc-2479-4a5d-943d-b3799680f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760952254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1760952254
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1002317328
Short name T76
Test name
Test status
Simulation time 8186293420 ps
CPU time 21.99 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:45:11 PM PDT 24
Peak memory 201824 kb
Host smart-c59b9449-3866-4e61-9c3d-9742f03bd4f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002317328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1002317328
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2231046198
Short name T206
Test name
Test status
Simulation time 549853439562 ps
CPU time 937.01 seconds
Started Jul 13 06:46:41 PM PDT 24
Finished Jul 13 07:02:19 PM PDT 24
Peak memory 210444 kb
Host smart-666eae09-5d09-4a9e-a694-c38dfd2b6a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231046198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2231046198
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3197947170
Short name T719
Test name
Test status
Simulation time 143230239947 ps
CPU time 189.99 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:49:51 PM PDT 24
Peak memory 211644 kb
Host smart-c61c8a8c-2e9a-4bf7-90be-3913e57468f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197947170 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3197947170
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.830983266
Short name T318
Test name
Test status
Simulation time 351114525655 ps
CPU time 194.04 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:50:41 PM PDT 24
Peak memory 201948 kb
Host smart-0d42d5c5-6201-45a1-8b52-1b068cfbd103
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830983266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.830983266
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.280088734
Short name T154
Test name
Test status
Simulation time 161880271031 ps
CPU time 143.56 seconds
Started Jul 13 06:47:35 PM PDT 24
Finished Jul 13 06:49:59 PM PDT 24
Peak memory 201968 kb
Host smart-cc371483-eeea-4fb6-b5bb-4408f02e9020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280088734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.280088734
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3140939397
Short name T220
Test name
Test status
Simulation time 342704635279 ps
CPU time 179.95 seconds
Started Jul 13 06:48:44 PM PDT 24
Finished Jul 13 06:51:45 PM PDT 24
Peak memory 201900 kb
Host smart-2fd80fc0-d3e7-497e-8daa-873a6982b69b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140939397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3140939397
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4029219667
Short name T18
Test name
Test status
Simulation time 116585628742 ps
CPU time 247.13 seconds
Started Jul 13 06:48:55 PM PDT 24
Finished Jul 13 06:53:03 PM PDT 24
Peak memory 210532 kb
Host smart-30544fed-03df-40a8-accb-b34d934956d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029219667 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4029219667
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.747005968
Short name T315
Test name
Test status
Simulation time 381624421409 ps
CPU time 812.15 seconds
Started Jul 13 06:46:37 PM PDT 24
Finished Jul 13 07:00:09 PM PDT 24
Peak memory 201912 kb
Host smart-a9b77247-6e3c-4569-8116-37718aa09fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747005968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.747005968
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.131121199
Short name T144
Test name
Test status
Simulation time 482421548710 ps
CPU time 271.06 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:51:41 PM PDT 24
Peak memory 201912 kb
Host smart-c5b5649b-3108-413d-823f-ff6877bf3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131121199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.131121199
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3944527958
Short name T199
Test name
Test status
Simulation time 58390298595 ps
CPU time 298.08 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:52:13 PM PDT 24
Peak memory 210616 kb
Host smart-27520262-78c7-4997-bc5a-3aa7e1665b92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944527958 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3944527958
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1364458734
Short name T225
Test name
Test status
Simulation time 354168351778 ps
CPU time 719.93 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 07:00:16 PM PDT 24
Peak memory 201848 kb
Host smart-76180035-213b-451b-8125-4432c1a98dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364458734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1364458734
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3346378621
Short name T254
Test name
Test status
Simulation time 367836002623 ps
CPU time 225.79 seconds
Started Jul 13 06:48:14 PM PDT 24
Finished Jul 13 06:52:01 PM PDT 24
Peak memory 201964 kb
Host smart-83a6709f-ead4-46b1-884f-6484e65eb477
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346378621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3346378621
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3073072053
Short name T237
Test name
Test status
Simulation time 330828715872 ps
CPU time 371.57 seconds
Started Jul 13 06:48:59 PM PDT 24
Finished Jul 13 06:55:11 PM PDT 24
Peak memory 201944 kb
Host smart-8d368437-2d10-4084-893d-9b6b22048963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073072053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3073072053
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4024975184
Short name T232
Test name
Test status
Simulation time 564437485137 ps
CPU time 185.4 seconds
Started Jul 13 06:49:21 PM PDT 24
Finished Jul 13 06:52:27 PM PDT 24
Peak memory 201904 kb
Host smart-8b1397d0-f169-48a5-9927-50fb3caf4f7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024975184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4024975184
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2022640670
Short name T338
Test name
Test status
Simulation time 123130987305 ps
CPU time 629.08 seconds
Started Jul 13 06:49:41 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 202248 kb
Host smart-eb000a32-3cb6-4067-b1a5-fc3b9241f855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022640670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2022640670
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.311322441
Short name T203
Test name
Test status
Simulation time 111852675348 ps
CPU time 572.24 seconds
Started Jul 13 06:50:07 PM PDT 24
Finished Jul 13 06:59:40 PM PDT 24
Peak memory 210764 kb
Host smart-2ea5df4d-b688-4a1f-8e91-480d36761fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311322441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
311322441
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2323478691
Short name T280
Test name
Test status
Simulation time 530980587014 ps
CPU time 621.12 seconds
Started Jul 13 06:51:37 PM PDT 24
Finished Jul 13 07:01:58 PM PDT 24
Peak memory 201868 kb
Host smart-b4d10397-26e6-494e-80db-b4ecd5ebfb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323478691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2323478691
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1109065260
Short name T283
Test name
Test status
Simulation time 336399156653 ps
CPU time 186.44 seconds
Started Jul 13 06:46:59 PM PDT 24
Finished Jul 13 06:50:06 PM PDT 24
Peak memory 201908 kb
Host smart-2c7773a2-0ee0-4bb1-8476-d346a6f57bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109065260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1109065260
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.565888089
Short name T132
Test name
Test status
Simulation time 673522951 ps
CPU time 1.78 seconds
Started Jul 13 06:44:34 PM PDT 24
Finished Jul 13 06:44:36 PM PDT 24
Peak memory 201732 kb
Host smart-4d4f1617-c51c-49b4-aace-04028603594b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565888089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.565888089
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3508170520
Short name T915
Test name
Test status
Simulation time 26497703053 ps
CPU time 55.21 seconds
Started Jul 13 06:44:33 PM PDT 24
Finished Jul 13 06:45:29 PM PDT 24
Peak memory 201820 kb
Host smart-d733865b-f1f5-42b9-9797-612ceba3ea5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508170520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3508170520
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3769312617
Short name T815
Test name
Test status
Simulation time 1310929272 ps
CPU time 2.24 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:46 PM PDT 24
Peak memory 201688 kb
Host smart-1948e404-cfd7-480e-8d89-6d15e8bffe56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769312617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3769312617
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2862951282
Short name T902
Test name
Test status
Simulation time 519642643 ps
CPU time 2.07 seconds
Started Jul 13 06:44:26 PM PDT 24
Finished Jul 13 06:44:29 PM PDT 24
Peak memory 201544 kb
Host smart-3d0d929d-5e54-4c18-a2c3-79c631b0b751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862951282 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2862951282
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3390162126
Short name T121
Test name
Test status
Simulation time 536616302 ps
CPU time 1 seconds
Started Jul 13 06:44:26 PM PDT 24
Finished Jul 13 06:44:28 PM PDT 24
Peak memory 201496 kb
Host smart-f037127a-bdb3-4129-91ea-55e63474d372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390162126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3390162126
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3174445542
Short name T889
Test name
Test status
Simulation time 304325302 ps
CPU time 1.12 seconds
Started Jul 13 06:44:34 PM PDT 24
Finished Jul 13 06:44:36 PM PDT 24
Peak memory 201400 kb
Host smart-84785772-e81b-43d4-946c-ff4b427e353f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174445542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3174445542
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2924452786
Short name T872
Test name
Test status
Simulation time 4454239310 ps
CPU time 15.03 seconds
Started Jul 13 06:44:32 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 201824 kb
Host smart-297c7952-8d28-491b-be4e-6ae921500ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924452786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2924452786
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3846437386
Short name T869
Test name
Test status
Simulation time 574723897 ps
CPU time 2.34 seconds
Started Jul 13 06:44:30 PM PDT 24
Finished Jul 13 06:44:33 PM PDT 24
Peak memory 201800 kb
Host smart-c0d7c3e5-3e5c-45fd-bd2e-36bb982f52f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846437386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3846437386
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4292842151
Short name T901
Test name
Test status
Simulation time 4862434894 ps
CPU time 4.44 seconds
Started Jul 13 06:44:25 PM PDT 24
Finished Jul 13 06:44:30 PM PDT 24
Peak memory 201784 kb
Host smart-be62e51e-4cad-4eee-aa47-94360a9c4b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292842151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.4292842151
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.136031498
Short name T842
Test name
Test status
Simulation time 750064759 ps
CPU time 3.15 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201724 kb
Host smart-86b4fc85-e820-40f6-a101-1eb981c8d937
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136031498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.136031498
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2045624260
Short name T907
Test name
Test status
Simulation time 25806815121 ps
CPU time 33.25 seconds
Started Jul 13 06:44:31 PM PDT 24
Finished Jul 13 06:45:05 PM PDT 24
Peak memory 201860 kb
Host smart-5e05e207-f957-4b23-a067-c3bc99ad6fff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045624260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2045624260
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2274101045
Short name T857
Test name
Test status
Simulation time 1052131472 ps
CPU time 1.27 seconds
Started Jul 13 06:44:26 PM PDT 24
Finished Jul 13 06:44:28 PM PDT 24
Peak memory 201476 kb
Host smart-74d8cd77-3685-4546-a2e1-44d721e8afed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274101045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2274101045
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2703087369
Short name T99
Test name
Test status
Simulation time 470616770 ps
CPU time 1.83 seconds
Started Jul 13 06:44:26 PM PDT 24
Finished Jul 13 06:44:29 PM PDT 24
Peak memory 201556 kb
Host smart-6328ebc0-12ae-40d6-b23b-0fab61e6d3f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703087369 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2703087369
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.295851630
Short name T118
Test name
Test status
Simulation time 347668949 ps
CPU time 1.23 seconds
Started Jul 13 06:44:33 PM PDT 24
Finished Jul 13 06:44:35 PM PDT 24
Peak memory 201476 kb
Host smart-7ec516d5-0708-40a0-9a1f-33db7fed11a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295851630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.295851630
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2203934738
Short name T919
Test name
Test status
Simulation time 502214677 ps
CPU time 0.91 seconds
Started Jul 13 06:44:33 PM PDT 24
Finished Jul 13 06:44:35 PM PDT 24
Peak memory 201436 kb
Host smart-2750d1e4-f3c0-4c34-b513-36d7087c4e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203934738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2203934738
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3414928049
Short name T910
Test name
Test status
Simulation time 5583329879 ps
CPU time 4.29 seconds
Started Jul 13 06:44:27 PM PDT 24
Finished Jul 13 06:44:32 PM PDT 24
Peak memory 201808 kb
Host smart-6ab45761-40e1-4551-9bf5-06729afa32b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414928049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3414928049
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2468672951
Short name T913
Test name
Test status
Simulation time 566566863 ps
CPU time 2.81 seconds
Started Jul 13 06:44:31 PM PDT 24
Finished Jul 13 06:44:35 PM PDT 24
Peak memory 201824 kb
Host smart-b33597b8-37ab-4db5-ba78-b04d6f89be28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468672951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2468672951
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.178803908
Short name T832
Test name
Test status
Simulation time 406208334 ps
CPU time 1.1 seconds
Started Jul 13 06:44:40 PM PDT 24
Finished Jul 13 06:44:42 PM PDT 24
Peak memory 201544 kb
Host smart-710ca60e-ee01-46ac-82bb-69ba24ad8ee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178803908 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.178803908
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.786206713
Short name T125
Test name
Test status
Simulation time 492879194 ps
CPU time 2.11 seconds
Started Jul 13 06:44:40 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201496 kb
Host smart-02294bb2-e37f-4e71-83a1-6c28d8476086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786206713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.786206713
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.766245524
Short name T859
Test name
Test status
Simulation time 386640415 ps
CPU time 0.84 seconds
Started Jul 13 06:44:37 PM PDT 24
Finished Jul 13 06:44:39 PM PDT 24
Peak memory 201396 kb
Host smart-5c64178a-a0fd-41c6-a421-33784b796e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766245524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.766245524
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3532897976
Short name T829
Test name
Test status
Simulation time 460456152 ps
CPU time 2.64 seconds
Started Jul 13 06:44:44 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 218152 kb
Host smart-dbf473fd-dc23-42b3-8a4d-85a86326caaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532897976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3532897976
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.385639111
Short name T74
Test name
Test status
Simulation time 8765130556 ps
CPU time 7.35 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 201840 kb
Host smart-c99ef2ef-cdc8-4484-866b-1d0d8909efb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385639111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.385639111
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.712390846
Short name T861
Test name
Test status
Simulation time 444745474 ps
CPU time 1.92 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 201596 kb
Host smart-aa682d41-aa69-462d-b80f-37d785a76d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712390846 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.712390846
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3245265590
Short name T127
Test name
Test status
Simulation time 512285173 ps
CPU time 2 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 201492 kb
Host smart-fec41b16-631d-4358-818e-2e65ed719a9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245265590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3245265590
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.598771178
Short name T890
Test name
Test status
Simulation time 517748719 ps
CPU time 1.93 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 201340 kb
Host smart-2ecd78c0-469d-46da-b7ba-96c7746d07a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598771178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.598771178
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1529144498
Short name T894
Test name
Test status
Simulation time 4968412342 ps
CPU time 11.43 seconds
Started Jul 13 06:44:40 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201816 kb
Host smart-490d751a-7a1c-4af6-8e64-b9d70b22f2ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529144498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1529144498
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3515847612
Short name T67
Test name
Test status
Simulation time 1324437495 ps
CPU time 1.88 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201784 kb
Host smart-b961250f-f852-4b8a-8a04-c73ae665e2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515847612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3515847612
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2402033063
Short name T331
Test name
Test status
Simulation time 8680640490 ps
CPU time 23 seconds
Started Jul 13 06:44:36 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 201844 kb
Host smart-75f69962-283b-474e-a892-dedf4066e5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402033063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2402033063
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2385628597
Short name T887
Test name
Test status
Simulation time 529841862 ps
CPU time 1.18 seconds
Started Jul 13 06:44:40 PM PDT 24
Finished Jul 13 06:44:42 PM PDT 24
Peak memory 201572 kb
Host smart-859fdc17-192b-41d7-831d-70bf59ecaacf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385628597 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2385628597
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4081315763
Short name T131
Test name
Test status
Simulation time 437289257 ps
CPU time 1.3 seconds
Started Jul 13 06:44:36 PM PDT 24
Finished Jul 13 06:44:38 PM PDT 24
Peak memory 201472 kb
Host smart-ebc2d1f7-b6ea-485e-9ea4-60fc072cc637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081315763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4081315763
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.967558322
Short name T858
Test name
Test status
Simulation time 424370307 ps
CPU time 0.91 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:41 PM PDT 24
Peak memory 201448 kb
Host smart-46789a26-650f-4c42-a300-497808cec500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967558322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.967558322
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4024171404
Short name T849
Test name
Test status
Simulation time 4289326711 ps
CPU time 9.38 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:44:57 PM PDT 24
Peak memory 201824 kb
Host smart-be6ec797-5388-4c24-bf27-f9be0be3c427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024171404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.4024171404
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3135515263
Short name T68
Test name
Test status
Simulation time 375877644 ps
CPU time 3.33 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201728 kb
Host smart-86475712-3cab-4891-a158-3bc9e0ed6790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135515263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3135515263
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1940276029
Short name T903
Test name
Test status
Simulation time 8783143829 ps
CPU time 7.06 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 201860 kb
Host smart-d0f102dd-90a0-409b-b6e7-40662cd0a7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940276029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1940276029
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2738660972
Short name T100
Test name
Test status
Simulation time 518847262 ps
CPU time 1.28 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201480 kb
Host smart-9449d978-7045-4d88-8d14-087ebcbcf698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738660972 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2738660972
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1482955903
Short name T130
Test name
Test status
Simulation time 381017243 ps
CPU time 1.58 seconds
Started Jul 13 06:44:44 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 201472 kb
Host smart-f920d08a-9fa0-44f0-a63b-fe43776712e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482955903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1482955903
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3557070345
Short name T835
Test name
Test status
Simulation time 316651823 ps
CPU time 1.08 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201344 kb
Host smart-4a5e51bb-d4c2-4b98-a8f9-b9f40847ae78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557070345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3557070345
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1591905794
Short name T814
Test name
Test status
Simulation time 2661147204 ps
CPU time 2.11 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201600 kb
Host smart-f3593d79-c060-4e46-a946-95d3c707ed7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591905794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1591905794
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.961636601
Short name T891
Test name
Test status
Simulation time 480475446 ps
CPU time 2.61 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 218052 kb
Host smart-8699bcb8-f7a1-4116-a535-7aa6f0182ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961636601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.961636601
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2521127350
Short name T893
Test name
Test status
Simulation time 8681563916 ps
CPU time 21.7 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:45:07 PM PDT 24
Peak memory 201728 kb
Host smart-624b8cfe-7287-41a9-83a2-c7feab1f5d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521127350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2521127350
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.932916951
Short name T833
Test name
Test status
Simulation time 505497847 ps
CPU time 1.24 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201544 kb
Host smart-f13d5a74-7dc9-4a34-bdc7-dcbc047afe8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932916951 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.932916951
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1374812525
Short name T126
Test name
Test status
Simulation time 419328781 ps
CPU time 1.72 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 201472 kb
Host smart-8782e472-b985-4aa6-a8ee-213ebafb45f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374812525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1374812525
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.689603153
Short name T864
Test name
Test status
Simulation time 357926599 ps
CPU time 0.85 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201444 kb
Host smart-05198c04-9ba6-4a95-b734-4d499bde77e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689603153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.689603153
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3625374149
Short name T54
Test name
Test status
Simulation time 4597806086 ps
CPU time 3.8 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201820 kb
Host smart-b6f220b3-7234-4608-bdc3-55c809f0c9f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625374149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3625374149
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2406729933
Short name T884
Test name
Test status
Simulation time 897857619 ps
CPU time 1.92 seconds
Started Jul 13 06:44:44 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 217772 kb
Host smart-406bc269-c0ea-4d32-8cea-56beaeec4b02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406729933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2406729933
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.912690576
Short name T72
Test name
Test status
Simulation time 371651268 ps
CPU time 1.64 seconds
Started Jul 13 06:44:51 PM PDT 24
Finished Jul 13 06:44:54 PM PDT 24
Peak memory 201504 kb
Host smart-c9cfcab2-3dc3-45d3-b8e5-eec27386c7b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912690576 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.912690576
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1189145579
Short name T831
Test name
Test status
Simulation time 430689993 ps
CPU time 1.6 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201384 kb
Host smart-826039b0-ba4f-40fd-bbda-8c4fb3669435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189145579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1189145579
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3770755441
Short name T838
Test name
Test status
Simulation time 2570123400 ps
CPU time 6.35 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:44:54 PM PDT 24
Peak memory 201640 kb
Host smart-d751c4dd-d043-4e0a-a423-c6086866c9ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770755441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3770755441
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.74540859
Short name T841
Test name
Test status
Simulation time 396387533 ps
CPU time 2.64 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:50 PM PDT 24
Peak memory 217916 kb
Host smart-a05f8296-46f9-4e5c-b27e-adf846da594c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74540859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.74540859
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3042620180
Short name T329
Test name
Test status
Simulation time 8866157050 ps
CPU time 4.72 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201896 kb
Host smart-824a6256-cccc-452a-b2ef-7a1ad33e8686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042620180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3042620180
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2118504628
Short name T813
Test name
Test status
Simulation time 568950570 ps
CPU time 1.21 seconds
Started Jul 13 06:44:49 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201592 kb
Host smart-2686f67f-7434-425e-b242-eb41a7548351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118504628 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2118504628
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3598151737
Short name T119
Test name
Test status
Simulation time 438964233 ps
CPU time 1.28 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:50 PM PDT 24
Peak memory 201504 kb
Host smart-4bd89d05-38f1-4020-a9e4-6cc37ed7f634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598151737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3598151737
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3551712975
Short name T809
Test name
Test status
Simulation time 404787181 ps
CPU time 1.11 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:44 PM PDT 24
Peak memory 201380 kb
Host smart-e7e384a5-10a9-4337-8f16-45cab5e86f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551712975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3551712975
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.398319457
Short name T865
Test name
Test status
Simulation time 5535339351 ps
CPU time 4.23 seconds
Started Jul 13 06:44:53 PM PDT 24
Finished Jul 13 06:44:58 PM PDT 24
Peak memory 201756 kb
Host smart-da926f34-36ea-4ffd-9c92-35db5a57b4b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398319457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.398319457
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.56452425
Short name T874
Test name
Test status
Simulation time 495394738 ps
CPU time 2.26 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:44:50 PM PDT 24
Peak memory 210016 kb
Host smart-7008b1e3-c2b0-4a1f-aa9a-51a3782dc276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56452425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.56452425
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3624957210
Short name T58
Test name
Test status
Simulation time 4436756533 ps
CPU time 3.96 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201856 kb
Host smart-4e8ff75b-2dee-43c2-9f6e-e13c52dbe1e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624957210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3624957210
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2986893347
Short name T820
Test name
Test status
Simulation time 586634345 ps
CPU time 2.22 seconds
Started Jul 13 06:44:49 PM PDT 24
Finished Jul 13 06:44:53 PM PDT 24
Peak memory 201504 kb
Host smart-ec9e6683-0ede-45ef-b053-6426a0d1393a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986893347 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2986893347
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2739750771
Short name T868
Test name
Test status
Simulation time 539371535 ps
CPU time 1.41 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:01 PM PDT 24
Peak memory 201476 kb
Host smart-c816ec3f-24b4-42ca-a3c7-331bcd3c2941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739750771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2739750771
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2223620484
Short name T805
Test name
Test status
Simulation time 487300526 ps
CPU time 1.75 seconds
Started Jul 13 06:44:50 PM PDT 24
Finished Jul 13 06:44:53 PM PDT 24
Peak memory 201428 kb
Host smart-e57651e9-41d7-43d0-89ad-a51d7b6834a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223620484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2223620484
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3287091714
Short name T128
Test name
Test status
Simulation time 2580397842 ps
CPU time 2.26 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201612 kb
Host smart-92083b05-6752-4313-9c18-77ebe79f70fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287091714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3287091714
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1133270381
Short name T896
Test name
Test status
Simulation time 458017270 ps
CPU time 2.24 seconds
Started Jul 13 06:45:00 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 201748 kb
Host smart-50f65924-ad09-4b16-aaf0-d400c8687c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133270381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1133270381
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2603824936
Short name T828
Test name
Test status
Simulation time 5392399438 ps
CPU time 2.38 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201844 kb
Host smart-47f6bf40-2d69-4518-a191-0fd67a5d341b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603824936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2603824936
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.63300998
Short name T817
Test name
Test status
Simulation time 475181080 ps
CPU time 0.97 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:44:56 PM PDT 24
Peak memory 201516 kb
Host smart-7b3a92f9-a94a-4122-b71d-da9cfbe65ed8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63300998 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.63300998
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1338629717
Short name T830
Test name
Test status
Simulation time 413693782 ps
CPU time 1.39 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 201476 kb
Host smart-4554322a-7094-4db3-aab4-f1024ca6ce2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338629717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1338629717
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2285292481
Short name T876
Test name
Test status
Simulation time 515637147 ps
CPU time 1.26 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201420 kb
Host smart-5490bbab-2938-49e1-a913-2e7e438a82ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285292481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2285292481
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.670227145
Short name T875
Test name
Test status
Simulation time 2155048097 ps
CPU time 1.17 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:44:56 PM PDT 24
Peak memory 201608 kb
Host smart-313d94d0-a604-47ec-ae13-4133c000d03c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670227145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.670227145
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4272916720
Short name T843
Test name
Test status
Simulation time 343909152 ps
CPU time 1.53 seconds
Started Jul 13 06:44:49 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201720 kb
Host smart-e111c6f3-685d-411d-bdb5-0fd23dab95bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272916720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4272916720
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1825185177
Short name T883
Test name
Test status
Simulation time 4270728801 ps
CPU time 10.45 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:45:06 PM PDT 24
Peak memory 201796 kb
Host smart-2cb20831-2293-4eb5-a154-fc550f89a907
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825185177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1825185177
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2353130024
Short name T878
Test name
Test status
Simulation time 356258961 ps
CPU time 1.62 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:44:50 PM PDT 24
Peak memory 201556 kb
Host smart-08899cc4-e1aa-4613-9f32-dff3566c6bb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353130024 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2353130024
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3508616196
Short name T116
Test name
Test status
Simulation time 592314865 ps
CPU time 1.16 seconds
Started Jul 13 06:44:49 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201492 kb
Host smart-8eb415f8-7b87-40d9-9350-da3cd8677fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508616196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3508616196
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.820206884
Short name T821
Test name
Test status
Simulation time 505798060 ps
CPU time 0.91 seconds
Started Jul 13 06:44:52 PM PDT 24
Finished Jul 13 06:44:54 PM PDT 24
Peak memory 201380 kb
Host smart-3ed37849-6f1a-4ef7-bb20-7fc86d8caecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820206884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.820206884
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1839126911
Short name T852
Test name
Test status
Simulation time 4173339465 ps
CPU time 10.08 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 201796 kb
Host smart-b9d81f31-b9ce-4108-a4c4-0d7de139d043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839126911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1839126911
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1736627810
Short name T70
Test name
Test status
Simulation time 753648622 ps
CPU time 2.77 seconds
Started Jul 13 06:44:59 PM PDT 24
Finished Jul 13 06:45:03 PM PDT 24
Peak memory 218072 kb
Host smart-f03e70bb-2e48-447c-94da-844c8ab78c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736627810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1736627810
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.271191612
Short name T880
Test name
Test status
Simulation time 8192338537 ps
CPU time 21.51 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:45:10 PM PDT 24
Peak memory 201876 kb
Host smart-5b02700a-1d66-4d48-b999-bd4ede617448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271191612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.271191612
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1996288372
Short name T847
Test name
Test status
Simulation time 1349378326 ps
CPU time 1.79 seconds
Started Jul 13 06:44:28 PM PDT 24
Finished Jul 13 06:44:31 PM PDT 24
Peak memory 201672 kb
Host smart-592a2749-4c95-4beb-81f1-d42398b0920c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996288372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1996288372
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3795869266
Short name T916
Test name
Test status
Simulation time 30311224835 ps
CPU time 37.61 seconds
Started Jul 13 06:44:30 PM PDT 24
Finished Jul 13 06:45:08 PM PDT 24
Peak memory 201812 kb
Host smart-54a9e7af-5cef-4ae0-a3f3-58367537c4a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795869266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3795869266
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.349884758
Short name T113
Test name
Test status
Simulation time 1262104729 ps
CPU time 0.94 seconds
Started Jul 13 06:44:33 PM PDT 24
Finished Jul 13 06:44:35 PM PDT 24
Peak memory 201516 kb
Host smart-cd991a9f-ac64-4214-be0d-7fe21351195a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349884758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.349884758
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2025950148
Short name T825
Test name
Test status
Simulation time 524944260 ps
CPU time 1.44 seconds
Started Jul 13 06:44:31 PM PDT 24
Finished Jul 13 06:44:33 PM PDT 24
Peak memory 201544 kb
Host smart-d3dfe2ac-2935-41bc-814a-03ce0eee4dc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025950148 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2025950148
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1270606373
Short name T818
Test name
Test status
Simulation time 407485297 ps
CPU time 0.94 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:44 PM PDT 24
Peak memory 201696 kb
Host smart-f6b2731e-8a6f-419d-8ef8-4d2ccfa319a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270606373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1270606373
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.422530384
Short name T836
Test name
Test status
Simulation time 500156972 ps
CPU time 1.21 seconds
Started Jul 13 06:44:27 PM PDT 24
Finished Jul 13 06:44:30 PM PDT 24
Peak memory 201364 kb
Host smart-eca87102-5cfe-4afe-8077-6ae022f22dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422530384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.422530384
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1295221948
Short name T863
Test name
Test status
Simulation time 4675946968 ps
CPU time 5.63 seconds
Started Jul 13 06:44:34 PM PDT 24
Finished Jul 13 06:44:40 PM PDT 24
Peak memory 201816 kb
Host smart-2d709964-4244-4cc5-8507-f403ea1c34bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295221948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1295221948
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2517461851
Short name T823
Test name
Test status
Simulation time 336275799 ps
CPU time 1.42 seconds
Started Jul 13 06:44:27 PM PDT 24
Finished Jul 13 06:44:29 PM PDT 24
Peak memory 202028 kb
Host smart-d075f09b-2956-4c69-9cf7-6e90b89acb33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517461851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2517461851
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2561654912
Short name T75
Test name
Test status
Simulation time 4147163220 ps
CPU time 10.76 seconds
Started Jul 13 06:44:33 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201788 kb
Host smart-54b77c6a-4cf1-49f7-b3d7-4937ab6bcc3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561654912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2561654912
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3193305951
Short name T803
Test name
Test status
Simulation time 520705385 ps
CPU time 1.73 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201420 kb
Host smart-9d406173-6ce8-47db-820d-08e48a6ff89b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193305951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3193305951
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.358114278
Short name T827
Test name
Test status
Simulation time 415783092 ps
CPU time 0.7 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201420 kb
Host smart-e1ad5b59-ce80-4f83-9a9b-215637da74e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358114278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.358114278
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1692222743
Short name T810
Test name
Test status
Simulation time 507132037 ps
CPU time 1.75 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:01 PM PDT 24
Peak memory 201396 kb
Host smart-6f0d9d93-c162-4a03-9ae0-969c78304171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692222743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1692222743
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1945314652
Short name T899
Test name
Test status
Simulation time 403340565 ps
CPU time 1.22 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201420 kb
Host smart-6fdeb3bc-c300-48a9-9e60-61f5187a2890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945314652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1945314652
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.191290527
Short name T824
Test name
Test status
Simulation time 444790478 ps
CPU time 1.69 seconds
Started Jul 13 06:44:48 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201432 kb
Host smart-8ea7f5ac-141b-4ec9-8128-5a0d81e39cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191290527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.191290527
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.815846832
Short name T888
Test name
Test status
Simulation time 489619401 ps
CPU time 1.72 seconds
Started Jul 13 06:44:48 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201396 kb
Host smart-41158cf3-dc6f-4582-88ad-a6e136b06a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815846832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.815846832
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4061524068
Short name T904
Test name
Test status
Simulation time 391914600 ps
CPU time 1.15 seconds
Started Jul 13 06:44:53 PM PDT 24
Finished Jul 13 06:44:54 PM PDT 24
Peak memory 201444 kb
Host smart-50018bc2-e905-4c31-9e7e-f5aac7ee73a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061524068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4061524068
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2435573033
Short name T837
Test name
Test status
Simulation time 455391713 ps
CPU time 1.03 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:44:57 PM PDT 24
Peak memory 201432 kb
Host smart-6df0ccf6-1b43-4ac1-a98d-eeb69c8fabeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435573033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2435573033
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1550140687
Short name T802
Test name
Test status
Simulation time 350444357 ps
CPU time 1.48 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201264 kb
Host smart-86861279-4a19-437c-9bc4-d7f8dec8e31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550140687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1550140687
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3202249057
Short name T819
Test name
Test status
Simulation time 509707876 ps
CPU time 0.74 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:50 PM PDT 24
Peak memory 201420 kb
Host smart-2ea82130-46b2-4507-bdac-fde7aff085d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202249057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3202249057
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.415525998
Short name T115
Test name
Test status
Simulation time 859511815 ps
CPU time 4.81 seconds
Started Jul 13 06:44:25 PM PDT 24
Finished Jul 13 06:44:30 PM PDT 24
Peak memory 201744 kb
Host smart-00aefcc5-a13d-4df2-b221-f5a9ab1bb9c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415525998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.415525998
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1353088453
Short name T886
Test name
Test status
Simulation time 9430980589 ps
CPU time 18.58 seconds
Started Jul 13 06:44:27 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 201876 kb
Host smart-44b9fda1-6bfb-4cb3-899b-536656269d66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353088453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1353088453
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1837260241
Short name T914
Test name
Test status
Simulation time 687543008 ps
CPU time 0.94 seconds
Started Jul 13 06:44:27 PM PDT 24
Finished Jul 13 06:44:29 PM PDT 24
Peak memory 201424 kb
Host smart-91356ee2-3764-4af4-a1d4-389ccf45231b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837260241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1837260241
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4113300775
Short name T839
Test name
Test status
Simulation time 485841849 ps
CPU time 1.85 seconds
Started Jul 13 06:44:30 PM PDT 24
Finished Jul 13 06:44:32 PM PDT 24
Peak memory 201496 kb
Host smart-1ebb2276-3b5f-40be-9086-0c48c99f31fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113300775 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4113300775
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.133178188
Short name T834
Test name
Test status
Simulation time 508037960 ps
CPU time 1.8 seconds
Started Jul 13 06:44:25 PM PDT 24
Finished Jul 13 06:44:28 PM PDT 24
Peak memory 201488 kb
Host smart-82543fc4-2874-4709-a56d-649fdcd201e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133178188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.133178188
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.153926128
Short name T811
Test name
Test status
Simulation time 373500706 ps
CPU time 1.57 seconds
Started Jul 13 06:44:26 PM PDT 24
Finished Jul 13 06:44:28 PM PDT 24
Peak memory 201428 kb
Host smart-99a85c05-37dd-47ab-aad1-672fa07be703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153926128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.153926128
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.69108383
Short name T53
Test name
Test status
Simulation time 5582768691 ps
CPU time 6.83 seconds
Started Jul 13 06:44:25 PM PDT 24
Finished Jul 13 06:44:33 PM PDT 24
Peak memory 201888 kb
Host smart-0fb205b1-21d2-4314-8128-6e3029aef0c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69108383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctr
l_same_csr_outstanding.69108383
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3493855095
Short name T892
Test name
Test status
Simulation time 489424141 ps
CPU time 3.16 seconds
Started Jul 13 06:44:27 PM PDT 24
Finished Jul 13 06:44:32 PM PDT 24
Peak memory 201708 kb
Host smart-8347cc4e-4a1c-4210-84c7-ba5efbe078a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493855095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3493855095
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4158229846
Short name T877
Test name
Test status
Simulation time 4399808691 ps
CPU time 2.54 seconds
Started Jul 13 06:44:31 PM PDT 24
Finished Jul 13 06:44:34 PM PDT 24
Peak memory 201740 kb
Host smart-96efc191-e6cb-4b94-a94d-5031d3e5d84d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158229846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4158229846
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1068792576
Short name T806
Test name
Test status
Simulation time 530129664 ps
CPU time 1.9 seconds
Started Jul 13 06:44:50 PM PDT 24
Finished Jul 13 06:44:53 PM PDT 24
Peak memory 201436 kb
Host smart-ceeccdb8-2f80-4299-a7c3-3c89d0655a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068792576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1068792576
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1582021803
Short name T822
Test name
Test status
Simulation time 352965315 ps
CPU time 0.72 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201348 kb
Host smart-d6d429b6-03f1-4d03-8e3a-b6600340fdc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582021803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1582021803
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3898119516
Short name T801
Test name
Test status
Simulation time 545723785 ps
CPU time 0.79 seconds
Started Jul 13 06:44:57 PM PDT 24
Finished Jul 13 06:44:59 PM PDT 24
Peak memory 201400 kb
Host smart-5437f8ad-13dd-42eb-b34a-4d37fb0b71a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898119516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3898119516
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2698272232
Short name T840
Test name
Test status
Simulation time 504496609 ps
CPU time 1.78 seconds
Started Jul 13 06:44:51 PM PDT 24
Finished Jul 13 06:44:54 PM PDT 24
Peak memory 201444 kb
Host smart-899dd7e9-2346-4d2e-91e2-706ab0ee574f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698272232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2698272232
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2326651042
Short name T844
Test name
Test status
Simulation time 328837877 ps
CPU time 1.17 seconds
Started Jul 13 06:44:48 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201404 kb
Host smart-306f794f-a184-457f-baaa-7bc8f3e638ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326651042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2326651042
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.962689833
Short name T897
Test name
Test status
Simulation time 321465665 ps
CPU time 1.32 seconds
Started Jul 13 06:44:49 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201456 kb
Host smart-caaea16e-a369-4f4d-9bfc-55474a3ef69b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962689833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.962689833
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4012850541
Short name T855
Test name
Test status
Simulation time 291329221 ps
CPU time 1.32 seconds
Started Jul 13 06:44:52 PM PDT 24
Finished Jul 13 06:44:55 PM PDT 24
Peak memory 201372 kb
Host smart-7646d5a5-bf36-40b4-b343-1fd34c53eb2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012850541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4012850541
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2960643255
Short name T918
Test name
Test status
Simulation time 486229877 ps
CPU time 1.23 seconds
Started Jul 13 06:44:51 PM PDT 24
Finished Jul 13 06:44:53 PM PDT 24
Peak memory 201436 kb
Host smart-ae0b41ec-c018-4c34-9ca7-52761e886d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960643255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2960643255
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1663282500
Short name T879
Test name
Test status
Simulation time 448961009 ps
CPU time 1.18 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201260 kb
Host smart-04e8423f-caef-484a-82d6-45429625c4f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663282500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1663282500
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4041027342
Short name T867
Test name
Test status
Simulation time 298159154 ps
CPU time 0.97 seconds
Started Jul 13 06:44:52 PM PDT 24
Finished Jul 13 06:44:54 PM PDT 24
Peak memory 201440 kb
Host smart-910261ec-a163-4ae2-8fe2-0ffb5d80388a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041027342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4041027342
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.428032688
Short name T123
Test name
Test status
Simulation time 792471577 ps
CPU time 3.21 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:46 PM PDT 24
Peak memory 201740 kb
Host smart-1c9abb22-acfe-4732-9fcd-ee7c4f8b7cf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428032688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.428032688
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4141154459
Short name T895
Test name
Test status
Simulation time 24289278848 ps
CPU time 24.85 seconds
Started Jul 13 06:44:38 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 201848 kb
Host smart-5cbfa812-e990-4f4a-a74c-f874cd469e53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141154459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4141154459
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3057860354
Short name T112
Test name
Test status
Simulation time 1299393093 ps
CPU time 1.49 seconds
Started Jul 13 06:44:37 PM PDT 24
Finished Jul 13 06:44:39 PM PDT 24
Peak memory 201488 kb
Host smart-7f65463a-b36b-479d-bce7-cd1922a7844a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057860354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3057860354
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1218840738
Short name T882
Test name
Test status
Simulation time 413791667 ps
CPU time 1.81 seconds
Started Jul 13 06:44:40 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201508 kb
Host smart-0f49f26d-4a92-4f46-b744-e470134a1c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218840738 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1218840738
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.442829249
Short name T114
Test name
Test status
Simulation time 430548478 ps
CPU time 1.84 seconds
Started Jul 13 06:44:40 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201520 kb
Host smart-dca919f1-050e-4833-9d52-7e9ddd68da67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442829249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.442829249
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.379290444
Short name T860
Test name
Test status
Simulation time 352817305 ps
CPU time 1.06 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201348 kb
Host smart-67d03947-0e0b-4b79-a31c-f71dc8ec4be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379290444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.379290444
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1896040849
Short name T881
Test name
Test status
Simulation time 2492210245 ps
CPU time 2 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:44 PM PDT 24
Peak memory 201624 kb
Host smart-e6f2c5c4-0b50-48e7-83e1-03cae7cda4e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896040849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1896040849
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.286127763
Short name T862
Test name
Test status
Simulation time 408848777 ps
CPU time 2.82 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:42 PM PDT 24
Peak memory 201800 kb
Host smart-7fa6f2bf-43cd-4e78-a069-98c45889f142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286127763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.286127763
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3460559052
Short name T57
Test name
Test status
Simulation time 4478779071 ps
CPU time 4.48 seconds
Started Jul 13 06:44:29 PM PDT 24
Finished Jul 13 06:44:34 PM PDT 24
Peak memory 201796 kb
Host smart-ed34b8c9-e7dc-44f1-b554-15939d04faa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460559052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3460559052
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.273306512
Short name T905
Test name
Test status
Simulation time 388942521 ps
CPU time 0.77 seconds
Started Jul 13 06:44:58 PM PDT 24
Finished Jul 13 06:45:00 PM PDT 24
Peak memory 201400 kb
Host smart-939a5c39-870d-40da-a127-b18de1d92925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273306512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.273306512
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4012648702
Short name T853
Test name
Test status
Simulation time 478240633 ps
CPU time 0.85 seconds
Started Jul 13 06:44:48 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201468 kb
Host smart-07582f8c-683d-4f68-a2e6-437bcd5afa0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012648702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4012648702
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1392733114
Short name T898
Test name
Test status
Simulation time 374100699 ps
CPU time 0.86 seconds
Started Jul 13 06:44:50 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201420 kb
Host smart-fffd7d06-995a-43cb-9ece-154b2c6e7906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392733114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1392733114
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2951689942
Short name T804
Test name
Test status
Simulation time 302601026 ps
CPU time 1.03 seconds
Started Jul 13 06:44:54 PM PDT 24
Finished Jul 13 06:44:56 PM PDT 24
Peak memory 201380 kb
Host smart-5dd52dde-2225-40dd-b966-279f9bd191e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951689942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2951689942
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2155110254
Short name T807
Test name
Test status
Simulation time 389826732 ps
CPU time 0.96 seconds
Started Jul 13 06:44:49 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201372 kb
Host smart-12186657-9968-440f-b21c-696d1ce6ee9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155110254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2155110254
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2955926816
Short name T816
Test name
Test status
Simulation time 351138795 ps
CPU time 0.9 seconds
Started Jul 13 06:45:01 PM PDT 24
Finished Jul 13 06:45:03 PM PDT 24
Peak memory 201400 kb
Host smart-be54ce99-16b9-40ff-b525-373996592016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955926816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2955926816
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.779631067
Short name T850
Test name
Test status
Simulation time 321828301 ps
CPU time 1.4 seconds
Started Jul 13 06:44:53 PM PDT 24
Finished Jul 13 06:44:55 PM PDT 24
Peak memory 201348 kb
Host smart-1bb3d8ac-b391-45a3-8b7d-58c821946418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779631067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.779631067
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1946332785
Short name T912
Test name
Test status
Simulation time 319345566 ps
CPU time 0.84 seconds
Started Jul 13 06:44:51 PM PDT 24
Finished Jul 13 06:44:53 PM PDT 24
Peak memory 201420 kb
Host smart-9888c8d2-325f-4aea-83d5-4e839bd5a351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946332785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1946332785
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1525990870
Short name T908
Test name
Test status
Simulation time 539416056 ps
CPU time 1.01 seconds
Started Jul 13 06:44:47 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201440 kb
Host smart-9b7b9546-e331-4b1c-afc5-3a986aeebe27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525990870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1525990870
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.346279866
Short name T800
Test name
Test status
Simulation time 508438003 ps
CPU time 0.86 seconds
Started Jul 13 06:44:50 PM PDT 24
Finished Jul 13 06:44:52 PM PDT 24
Peak memory 201416 kb
Host smart-16985d74-fd00-4fe8-b11e-c90ef5728365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346279866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.346279866
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3603673593
Short name T73
Test name
Test status
Simulation time 458230116 ps
CPU time 1.89 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:42 PM PDT 24
Peak memory 201572 kb
Host smart-5d1fa594-0129-4821-97c5-035ab083561f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603673593 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3603673593
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1223520048
Short name T122
Test name
Test status
Simulation time 441218583 ps
CPU time 1.24 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:41 PM PDT 24
Peak memory 201440 kb
Host smart-f2305402-4dd5-48e2-b3f2-4fc1a1f3d6ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223520048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1223520048
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4007390805
Short name T808
Test name
Test status
Simulation time 438320799 ps
CPU time 1.67 seconds
Started Jul 13 06:44:37 PM PDT 24
Finished Jul 13 06:44:40 PM PDT 24
Peak memory 201460 kb
Host smart-e53f1991-3e81-4e18-bfef-5df41f15ebf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007390805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4007390805
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.67324904
Short name T870
Test name
Test status
Simulation time 2155614252 ps
CPU time 4.32 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201636 kb
Host smart-bbc13c2e-3ec3-40fb-9cc9-11b934fe27a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67324904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctr
l_same_csr_outstanding.67324904
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4278315275
Short name T906
Test name
Test status
Simulation time 605085368 ps
CPU time 3.72 seconds
Started Jul 13 06:44:37 PM PDT 24
Finished Jul 13 06:44:42 PM PDT 24
Peak memory 201780 kb
Host smart-a2981c87-e5f1-45e2-88cf-2f807d62c15d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278315275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4278315275
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.827617967
Short name T59
Test name
Test status
Simulation time 8703648403 ps
CPU time 5.31 seconds
Started Jul 13 06:44:38 PM PDT 24
Finished Jul 13 06:44:44 PM PDT 24
Peak memory 201796 kb
Host smart-3540050b-3ca2-41ac-84e6-8414fb823815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827617967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.827617967
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.700673810
Short name T826
Test name
Test status
Simulation time 517988252 ps
CPU time 1.38 seconds
Started Jul 13 06:44:44 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201536 kb
Host smart-d8a52571-618b-4619-bfe9-b447fea35719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700673810 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.700673810
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.313624611
Short name T129
Test name
Test status
Simulation time 565570050 ps
CPU time 2.02 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 201516 kb
Host smart-10a85855-368d-4881-8b5c-b06e8e2f678f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313624611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.313624611
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3842512192
Short name T885
Test name
Test status
Simulation time 422435960 ps
CPU time 1.54 seconds
Started Jul 13 06:44:38 PM PDT 24
Finished Jul 13 06:44:41 PM PDT 24
Peak memory 201400 kb
Host smart-aa0bf370-60ad-434a-b468-6d77ecf55445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842512192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3842512192
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2478412133
Short name T851
Test name
Test status
Simulation time 4442935832 ps
CPU time 16.49 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:45:01 PM PDT 24
Peak memory 201816 kb
Host smart-6e11ec13-ab4a-4afe-9442-cd3af8f3ab1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478412133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2478412133
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3711495996
Short name T845
Test name
Test status
Simulation time 1199473115 ps
CPU time 1.97 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 217692 kb
Host smart-69c260d4-4c2d-479f-a97b-cc964aa37d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711495996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3711495996
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2929499754
Short name T873
Test name
Test status
Simulation time 4216666768 ps
CPU time 3.93 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:51 PM PDT 24
Peak memory 201836 kb
Host smart-09655029-6dde-4e70-9fa0-ff1e0fe551bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929499754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2929499754
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3674206819
Short name T90
Test name
Test status
Simulation time 625091464 ps
CPU time 1.71 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:42 PM PDT 24
Peak memory 201584 kb
Host smart-f23aba0b-a1ac-40b8-92ba-00587855f287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674206819 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3674206819
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2606270009
Short name T55
Test name
Test status
Simulation time 398390352 ps
CPU time 1.7 seconds
Started Jul 13 06:44:40 PM PDT 24
Finished Jul 13 06:44:42 PM PDT 24
Peak memory 201424 kb
Host smart-8419e451-e878-46fb-a44d-dc18a1d02377
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606270009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2606270009
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1494202893
Short name T900
Test name
Test status
Simulation time 342549745 ps
CPU time 0.86 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201420 kb
Host smart-04db136a-7661-408f-b638-d7de6677c59b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494202893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1494202893
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3570990956
Short name T854
Test name
Test status
Simulation time 2401132393 ps
CPU time 7.86 seconds
Started Jul 13 06:44:37 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201620 kb
Host smart-5a047a61-92ee-42ea-991d-3077cac0e0f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570990956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3570990956
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1567057970
Short name T846
Test name
Test status
Simulation time 670876684 ps
CPU time 2.69 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:44:47 PM PDT 24
Peak memory 211028 kb
Host smart-9ec9c1b7-ec7a-41c5-bf02-96ae246c34ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567057970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1567057970
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.547560843
Short name T909
Test name
Test status
Simulation time 8735822238 ps
CPU time 21.38 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:45:06 PM PDT 24
Peak memory 201768 kb
Host smart-3ed58e1a-bb4a-4b2c-bc71-59b18c943c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547560843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.547560843
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.418956453
Short name T911
Test name
Test status
Simulation time 655380192 ps
CPU time 1.07 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:44:45 PM PDT 24
Peak memory 201536 kb
Host smart-48c0aa41-a7eb-47e2-9077-200c7dbf446b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418956453 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.418956453
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.180992573
Short name T124
Test name
Test status
Simulation time 567199225 ps
CPU time 1.45 seconds
Started Jul 13 06:44:44 PM PDT 24
Finished Jul 13 06:44:48 PM PDT 24
Peak memory 201504 kb
Host smart-00ff2031-d2d4-47b6-8ad7-5506f6b33118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180992573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.180992573
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1006071628
Short name T848
Test name
Test status
Simulation time 393541810 ps
CPU time 0.87 seconds
Started Jul 13 06:44:46 PM PDT 24
Finished Jul 13 06:44:49 PM PDT 24
Peak memory 201440 kb
Host smart-05cc6af5-571d-47da-908a-a0593d998160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006071628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1006071628
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.60835383
Short name T856
Test name
Test status
Simulation time 2037841705 ps
CPU time 8.05 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:44:53 PM PDT 24
Peak memory 201536 kb
Host smart-3ee14be7-cee6-4f8f-9510-dc9e5bf7b4a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60835383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctr
l_same_csr_outstanding.60835383
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1789256608
Short name T917
Test name
Test status
Simulation time 7952368571 ps
CPU time 16.94 seconds
Started Jul 13 06:44:45 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 201836 kb
Host smart-f1881dd7-4ae3-459d-b655-955ad1c04d88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789256608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1789256608
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2335992773
Short name T62
Test name
Test status
Simulation time 531987245 ps
CPU time 1.2 seconds
Started Jul 13 06:44:41 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201536 kb
Host smart-280d24b2-23c5-4cfd-843b-5b62ff852235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335992773 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2335992773
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3955173647
Short name T120
Test name
Test status
Simulation time 463467272 ps
CPU time 0.87 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:44:46 PM PDT 24
Peak memory 201464 kb
Host smart-d83c6ecb-92d3-4656-94ba-f2fac5f399be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955173647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3955173647
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3610995747
Short name T812
Test name
Test status
Simulation time 445139811 ps
CPU time 0.81 seconds
Started Jul 13 06:44:38 PM PDT 24
Finished Jul 13 06:44:39 PM PDT 24
Peak memory 201384 kb
Host smart-7b52e453-50ac-494f-9714-57b78712d315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610995747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3610995747
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3384073063
Short name T866
Test name
Test status
Simulation time 4780204945 ps
CPU time 15.83 seconds
Started Jul 13 06:44:43 PM PDT 24
Finished Jul 13 06:45:01 PM PDT 24
Peak memory 201792 kb
Host smart-26dd0504-9f19-48d4-a55e-45bcd53c88db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384073063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3384073063
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2392410666
Short name T871
Test name
Test status
Simulation time 452835136 ps
CPU time 3.24 seconds
Started Jul 13 06:44:39 PM PDT 24
Finished Jul 13 06:44:43 PM PDT 24
Peak memory 201800 kb
Host smart-4c6e988f-fcad-4b9d-9988-9e4cc2763867
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392410666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2392410666
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1731513858
Short name T328
Test name
Test status
Simulation time 8338578892 ps
CPU time 20.71 seconds
Started Jul 13 06:44:42 PM PDT 24
Finished Jul 13 06:45:04 PM PDT 24
Peak memory 201860 kb
Host smart-e9452626-ee59-483b-a59d-135f206563d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731513858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1731513858
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2784769450
Short name T397
Test name
Test status
Simulation time 452572306 ps
CPU time 1.15 seconds
Started Jul 13 06:46:41 PM PDT 24
Finished Jul 13 06:46:43 PM PDT 24
Peak memory 201640 kb
Host smart-0e0d5a3b-57d9-4b5f-8e53-b0aa9b48a208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784769450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2784769450
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3240755701
Short name T709
Test name
Test status
Simulation time 162334579205 ps
CPU time 40.21 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:47:21 PM PDT 24
Peak memory 201900 kb
Host smart-3e2a235c-6f67-42d6-b246-3b26db356c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240755701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3240755701
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2151233682
Short name T371
Test name
Test status
Simulation time 493862318342 ps
CPU time 315.54 seconds
Started Jul 13 06:46:44 PM PDT 24
Finished Jul 13 06:52:00 PM PDT 24
Peak memory 201908 kb
Host smart-84da1034-6b14-4441-ab95-9348b9eda07f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151233682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2151233682
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3792263496
Short name T621
Test name
Test status
Simulation time 165947068935 ps
CPU time 35.03 seconds
Started Jul 13 06:46:39 PM PDT 24
Finished Jul 13 06:47:15 PM PDT 24
Peak memory 201952 kb
Host smart-54237d24-16e5-402a-8a79-425554b9ecf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792263496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3792263496
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3534470079
Short name T489
Test name
Test status
Simulation time 326013301702 ps
CPU time 378.99 seconds
Started Jul 13 06:46:44 PM PDT 24
Finished Jul 13 06:53:03 PM PDT 24
Peak memory 201888 kb
Host smart-faf357e6-2354-4fa7-9187-a74c16f92005
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534470079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3534470079
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2162209382
Short name T83
Test name
Test status
Simulation time 528048185359 ps
CPU time 1257.08 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 07:07:35 PM PDT 24
Peak memory 201972 kb
Host smart-64e2a7aa-0ed9-4643-b4e3-c4bb732011dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162209382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2162209382
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2090345230
Short name T717
Test name
Test status
Simulation time 212969838057 ps
CPU time 447.31 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:54:06 PM PDT 24
Peak memory 201868 kb
Host smart-93f64519-7127-4dfe-9dcc-b1b1378f5b3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090345230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2090345230
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1855539880
Short name T566
Test name
Test status
Simulation time 74021888514 ps
CPU time 320.03 seconds
Started Jul 13 06:46:43 PM PDT 24
Finished Jul 13 06:52:04 PM PDT 24
Peak memory 202240 kb
Host smart-3febaf61-0f08-4dd3-81e9-0d4676018f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855539880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1855539880
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2339475970
Short name T724
Test name
Test status
Simulation time 23345876957 ps
CPU time 51.79 seconds
Started Jul 13 06:46:42 PM PDT 24
Finished Jul 13 06:47:34 PM PDT 24
Peak memory 201728 kb
Host smart-fe868b38-a4e8-434d-ab2e-7254c271fb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339475970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2339475970
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2194080722
Short name T456
Test name
Test status
Simulation time 5385881084 ps
CPU time 12.51 seconds
Started Jul 13 06:46:47 PM PDT 24
Finished Jul 13 06:47:00 PM PDT 24
Peak memory 201716 kb
Host smart-b16fe02d-193a-466e-a720-2d5ea8522497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194080722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2194080722
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2438182473
Short name T77
Test name
Test status
Simulation time 8181311817 ps
CPU time 5.38 seconds
Started Jul 13 06:46:37 PM PDT 24
Finished Jul 13 06:46:43 PM PDT 24
Peak memory 218260 kb
Host smart-af9d6adb-dead-4500-a6c9-4195c696256b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438182473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2438182473
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2563700125
Short name T451
Test name
Test status
Simulation time 5927172631 ps
CPU time 15.67 seconds
Started Jul 13 06:46:41 PM PDT 24
Finished Jul 13 06:46:58 PM PDT 24
Peak memory 201720 kb
Host smart-91d55202-4dc1-4445-87a6-3c2a532df29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563700125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2563700125
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3280275822
Short name T476
Test name
Test status
Simulation time 37514855799 ps
CPU time 83.77 seconds
Started Jul 13 06:46:45 PM PDT 24
Finished Jul 13 06:48:09 PM PDT 24
Peak memory 210284 kb
Host smart-4baf57b5-7085-47f7-b9a8-aa82d7f9ac89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280275822 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3280275822
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3841158330
Short name T107
Test name
Test status
Simulation time 208094619113 ps
CPU time 130.64 seconds
Started Jul 13 06:46:39 PM PDT 24
Finished Jul 13 06:48:50 PM PDT 24
Peak memory 201912 kb
Host smart-c5d4f7d0-2b73-433f-a8cd-c706794e008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841158330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3841158330
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1873967895
Short name T660
Test name
Test status
Simulation time 331635718468 ps
CPU time 764.75 seconds
Started Jul 13 06:46:44 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 201928 kb
Host smart-98335fb0-daee-4bf3-971f-b31d89af0372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873967895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1873967895
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.582905498
Short name T342
Test name
Test status
Simulation time 156995881719 ps
CPU time 342.05 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:52:29 PM PDT 24
Peak memory 201908 kb
Host smart-d3880dd5-7ee8-4cc0-b577-349962811e33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=582905498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.582905498
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4111538574
Short name T572
Test name
Test status
Simulation time 327697104613 ps
CPU time 666.98 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:57:48 PM PDT 24
Peak memory 201976 kb
Host smart-4e10510f-b988-4d16-8dce-94aebf9b6a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111538574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4111538574
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1067077862
Short name T582
Test name
Test status
Simulation time 497854056940 ps
CPU time 1069.51 seconds
Started Jul 13 06:46:39 PM PDT 24
Finished Jul 13 07:04:29 PM PDT 24
Peak memory 201876 kb
Host smart-2bffe569-3f54-491f-985a-cc76f8569d33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067077862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1067077862
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1011148453
Short name T146
Test name
Test status
Simulation time 173814000139 ps
CPU time 203.31 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:50:05 PM PDT 24
Peak memory 201448 kb
Host smart-12e11327-5602-42e3-aeb9-785d3e2b78f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011148453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1011148453
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4068131929
Short name T678
Test name
Test status
Simulation time 204925033815 ps
CPU time 464.47 seconds
Started Jul 13 06:46:41 PM PDT 24
Finished Jul 13 06:54:26 PM PDT 24
Peak memory 201876 kb
Host smart-daf74f49-b60a-4f71-bffe-9036b90f06c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068131929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4068131929
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.262025549
Short name T692
Test name
Test status
Simulation time 100389396899 ps
CPU time 339.1 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:52:21 PM PDT 24
Peak memory 201768 kb
Host smart-e3ebef17-5cc9-4cc8-9d7b-b7fb0bb6ba7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262025549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.262025549
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2082671620
Short name T588
Test name
Test status
Simulation time 38755792851 ps
CPU time 22.96 seconds
Started Jul 13 06:46:47 PM PDT 24
Finished Jul 13 06:47:11 PM PDT 24
Peak memory 201704 kb
Host smart-50369700-4f04-4ef4-a7bb-037ddcaa9699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082671620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2082671620
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2112099366
Short name T374
Test name
Test status
Simulation time 4174231166 ps
CPU time 3.23 seconds
Started Jul 13 06:46:39 PM PDT 24
Finished Jul 13 06:46:43 PM PDT 24
Peak memory 201724 kb
Host smart-18fa550c-222e-44f1-99ac-74240a5bfb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112099366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2112099366
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3214894594
Short name T65
Test name
Test status
Simulation time 4344150977 ps
CPU time 11.26 seconds
Started Jul 13 06:46:45 PM PDT 24
Finished Jul 13 06:46:56 PM PDT 24
Peak memory 217144 kb
Host smart-f4094b52-dd62-4711-bef8-7a033f8cd7b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214894594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3214894594
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.501407457
Short name T597
Test name
Test status
Simulation time 5679660047 ps
CPU time 10.86 seconds
Started Jul 13 06:46:43 PM PDT 24
Finished Jul 13 06:46:55 PM PDT 24
Peak memory 201984 kb
Host smart-afe03deb-68ef-400e-a893-23c9f1e6ddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501407457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.501407457
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1491320665
Short name T780
Test name
Test status
Simulation time 165967185053 ps
CPU time 104.72 seconds
Started Jul 13 06:46:37 PM PDT 24
Finished Jul 13 06:48:22 PM PDT 24
Peak memory 201896 kb
Host smart-7f1e2ddc-884b-476f-a4c6-508782a3a20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491320665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1491320665
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2193434655
Short name T473
Test name
Test status
Simulation time 478551168 ps
CPU time 1.53 seconds
Started Jul 13 06:47:15 PM PDT 24
Finished Jul 13 06:47:17 PM PDT 24
Peak memory 201648 kb
Host smart-388608cc-c35a-43a1-bffe-b4a3dec80ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193434655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2193434655
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2779544710
Short name T215
Test name
Test status
Simulation time 347331504592 ps
CPU time 835.52 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 07:01:06 PM PDT 24
Peak memory 201956 kb
Host smart-6cdaae5d-a5ca-44a1-969a-bb259fc82115
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779544710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2779544710
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.608723221
Short name T747
Test name
Test status
Simulation time 370073295862 ps
CPU time 219.3 seconds
Started Jul 13 06:47:12 PM PDT 24
Finished Jul 13 06:50:52 PM PDT 24
Peak memory 201904 kb
Host smart-25ed06ff-04f6-4157-90d3-b7836acaf78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608723221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.608723221
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.989321950
Short name T10
Test name
Test status
Simulation time 484536984780 ps
CPU time 1097.37 seconds
Started Jul 13 06:47:00 PM PDT 24
Finished Jul 13 07:05:17 PM PDT 24
Peak memory 201948 kb
Host smart-51cf3056-4cfb-4f79-b74e-3e0ca4ee65e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989321950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.989321950
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2986632554
Short name T625
Test name
Test status
Simulation time 487265653578 ps
CPU time 205.38 seconds
Started Jul 13 06:47:06 PM PDT 24
Finished Jul 13 06:50:32 PM PDT 24
Peak memory 201884 kb
Host smart-0e77b8a4-93dd-41b1-bd3f-e36fc458a3df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986632554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2986632554
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.433837701
Short name T770
Test name
Test status
Simulation time 158669063980 ps
CPU time 386.07 seconds
Started Jul 13 06:47:06 PM PDT 24
Finished Jul 13 06:53:33 PM PDT 24
Peak memory 201912 kb
Host smart-d4c3c665-ac4a-4822-858a-fb0804837338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433837701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.433837701
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1444329705
Short name T411
Test name
Test status
Simulation time 490044799453 ps
CPU time 1108.9 seconds
Started Jul 13 06:47:00 PM PDT 24
Finished Jul 13 07:05:29 PM PDT 24
Peak memory 201924 kb
Host smart-2e30a697-0dd7-4601-ab18-651a92cd8ecd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444329705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1444329705
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.930771629
Short name T640
Test name
Test status
Simulation time 191473163979 ps
CPU time 409.46 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:53:47 PM PDT 24
Peak memory 201876 kb
Host smart-9cb7237d-4521-465d-8f41-1afbebe758df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930771629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.930771629
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2081772752
Short name T499
Test name
Test status
Simulation time 113004680241 ps
CPU time 551.15 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:56:19 PM PDT 24
Peak memory 202164 kb
Host smart-1115b69f-e7b2-40ae-8ec8-8ea36b7072af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081772752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2081772752
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.70351732
Short name T352
Test name
Test status
Simulation time 37785509257 ps
CPU time 8.65 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 06:47:22 PM PDT 24
Peak memory 201712 kb
Host smart-4ad78b31-bcba-4129-9bcd-a70cd6d6be4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70351732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.70351732
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2343437836
Short name T466
Test name
Test status
Simulation time 4985315667 ps
CPU time 1.68 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:11 PM PDT 24
Peak memory 201700 kb
Host smart-c043a327-f344-4bda-9934-488c99469374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343437836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2343437836
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3966077509
Short name T633
Test name
Test status
Simulation time 5912373841 ps
CPU time 13.17 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:47:19 PM PDT 24
Peak memory 201696 kb
Host smart-ae6bd073-9896-42d0-bfc0-d2edb17fe100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966077509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3966077509
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1463033723
Short name T36
Test name
Test status
Simulation time 271914830598 ps
CPU time 295.17 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:52:04 PM PDT 24
Peak memory 210468 kb
Host smart-141804de-98d2-480e-b8a8-c5dfb562a970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463033723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1463033723
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1559255571
Short name T301
Test name
Test status
Simulation time 137875215927 ps
CPU time 80.42 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:48:30 PM PDT 24
Peak memory 210236 kb
Host smart-50254147-0f4d-4e35-b7ec-a7be01f63401
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559255571 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1559255571
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.539250638
Short name T686
Test name
Test status
Simulation time 364499833 ps
CPU time 1.43 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:10 PM PDT 24
Peak memory 201648 kb
Host smart-2859dca2-e3dd-4849-aa90-90fd1c7c4339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539250638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.539250638
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.425036459
Short name T292
Test name
Test status
Simulation time 514145026583 ps
CPU time 963.04 seconds
Started Jul 13 06:47:10 PM PDT 24
Finished Jul 13 07:03:15 PM PDT 24
Peak memory 201964 kb
Host smart-f822fd31-52f0-42f7-971b-2ffe7da074e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425036459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.425036459
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3924030113
Short name T725
Test name
Test status
Simulation time 160962307344 ps
CPU time 362.45 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:53:12 PM PDT 24
Peak memory 201932 kb
Host smart-cd0f9820-b2f9-4a5f-a252-6ae94f7d4695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924030113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3924030113
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2492326229
Short name T136
Test name
Test status
Simulation time 326548404715 ps
CPU time 194.18 seconds
Started Jul 13 06:47:06 PM PDT 24
Finished Jul 13 06:50:21 PM PDT 24
Peak memory 201924 kb
Host smart-66bbc6f3-d040-4248-8ba8-3527e30385bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492326229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2492326229
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2777851575
Short name T760
Test name
Test status
Simulation time 164269190080 ps
CPU time 94.16 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:48:50 PM PDT 24
Peak memory 201860 kb
Host smart-97ddce7a-6238-4798-a325-1ad9c7b1f9c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777851575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2777851575
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2341012616
Short name T251
Test name
Test status
Simulation time 324779202125 ps
CPU time 402.12 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:53:52 PM PDT 24
Peak memory 201952 kb
Host smart-5f8d40fd-a079-4629-a2fd-308471aa7138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341012616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2341012616
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2824187549
Short name T428
Test name
Test status
Simulation time 330654446865 ps
CPU time 650.1 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:58:07 PM PDT 24
Peak memory 201864 kb
Host smart-0a6cf132-349a-4c80-862f-415eb309135c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824187549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2824187549
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2603212227
Short name T312
Test name
Test status
Simulation time 380382573902 ps
CPU time 889.07 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 07:02:06 PM PDT 24
Peak memory 201900 kb
Host smart-5a8dddf5-7bee-4763-830e-2c1008ab27e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603212227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2603212227
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3613691814
Short name T429
Test name
Test status
Simulation time 602910992848 ps
CPU time 180.43 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 06:50:15 PM PDT 24
Peak memory 201904 kb
Host smart-59be5d27-6f65-4e92-9afc-81c4744d814b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613691814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3613691814
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1846168618
Short name T27
Test name
Test status
Simulation time 129548072269 ps
CPU time 700.72 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:58:50 PM PDT 24
Peak memory 202308 kb
Host smart-27446e0d-753e-44c3-b1da-be0433b53063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846168618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1846168618
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3954597460
Short name T649
Test name
Test status
Simulation time 41401314433 ps
CPU time 18.77 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:47:36 PM PDT 24
Peak memory 201660 kb
Host smart-3e50415d-0a2a-43b7-b0d1-fb3bc75ed6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954597460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3954597460
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1272819462
Short name T386
Test name
Test status
Simulation time 3920720071 ps
CPU time 10.32 seconds
Started Jul 13 06:47:10 PM PDT 24
Finished Jul 13 06:47:22 PM PDT 24
Peak memory 201720 kb
Host smart-f2e1ef7e-b08f-4d27-aa6a-2d4c48eeb58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272819462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1272819462
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2205606225
Short name T398
Test name
Test status
Simulation time 5813292829 ps
CPU time 3.79 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:13 PM PDT 24
Peak memory 201720 kb
Host smart-e979c571-25a9-4668-870d-19495322805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205606225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2205606225
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.617982109
Short name T701
Test name
Test status
Simulation time 321380502974 ps
CPU time 62.73 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:48:11 PM PDT 24
Peak memory 210224 kb
Host smart-43f62111-c520-40fd-a14d-366664fce221
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617982109 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.617982109
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.153571668
Short name T594
Test name
Test status
Simulation time 478312686 ps
CPU time 1.12 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:47:09 PM PDT 24
Peak memory 201660 kb
Host smart-8984c463-6b78-4818-93ea-887eb8337ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153571668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.153571668
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2206161897
Short name T619
Test name
Test status
Simulation time 179683243424 ps
CPU time 17.76 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:27 PM PDT 24
Peak memory 201736 kb
Host smart-e7178455-8bdb-42ca-b94c-685a8c2e992c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206161897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2206161897
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3397878524
Short name T161
Test name
Test status
Simulation time 323318187725 ps
CPU time 206.74 seconds
Started Jul 13 06:47:10 PM PDT 24
Finished Jul 13 06:50:38 PM PDT 24
Peak memory 201960 kb
Host smart-c266153e-fa17-4192-bbf9-edb7e9054e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397878524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3397878524
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3967653311
Short name T677
Test name
Test status
Simulation time 493401516683 ps
CPU time 1010.41 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 07:04:09 PM PDT 24
Peak memory 201892 kb
Host smart-2a2043c1-b338-4633-ae54-76c9af6b7970
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967653311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3967653311
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1437162787
Short name T299
Test name
Test status
Simulation time 489129772228 ps
CPU time 1041.36 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 07:04:36 PM PDT 24
Peak memory 201992 kb
Host smart-c919ee84-31bd-4f62-9a3e-8877d8650270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437162787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1437162787
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2632415253
Short name T347
Test name
Test status
Simulation time 163327042690 ps
CPU time 31.75 seconds
Started Jul 13 06:47:12 PM PDT 24
Finished Jul 13 06:47:45 PM PDT 24
Peak memory 201892 kb
Host smart-6c7978c3-0e81-481a-a64b-c67654696bf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632415253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2632415253
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.825774956
Short name T258
Test name
Test status
Simulation time 368336691558 ps
CPU time 425.71 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:54:15 PM PDT 24
Peak memory 201956 kb
Host smart-a93d35c3-028a-4d39-8e2d-a73fa19bfc35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825774956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.825774956
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2661141648
Short name T351
Test name
Test status
Simulation time 86879069992 ps
CPU time 311.65 seconds
Started Jul 13 06:47:11 PM PDT 24
Finished Jul 13 06:52:24 PM PDT 24
Peak memory 202252 kb
Host smart-3d481c02-b7b3-4af0-b7cf-5d03f68aa0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661141648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2661141648
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4202064803
Short name T493
Test name
Test status
Simulation time 32786854801 ps
CPU time 20.01 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:29 PM PDT 24
Peak memory 201720 kb
Host smart-5e0e1477-82df-4f9c-ba4d-c5e8cb4c5058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202064803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4202064803
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3863826528
Short name T372
Test name
Test status
Simulation time 5043983163 ps
CPU time 13.16 seconds
Started Jul 13 06:47:12 PM PDT 24
Finished Jul 13 06:47:26 PM PDT 24
Peak memory 201724 kb
Host smart-712a7704-0cfd-476b-b06b-9f015fcee3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863826528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3863826528
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.101850032
Short name T421
Test name
Test status
Simulation time 5595029241 ps
CPU time 3.77 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:47:11 PM PDT 24
Peak memory 201696 kb
Host smart-aa39ee7c-45d9-41bc-9f91-b7c6add68863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101850032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.101850032
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.836104079
Short name T568
Test name
Test status
Simulation time 331220716841 ps
CPU time 592.96 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:57:08 PM PDT 24
Peak memory 202224 kb
Host smart-ea6f9f6a-c38c-476d-a664-2158b9dde34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836104079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
836104079
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.468094978
Short name T634
Test name
Test status
Simulation time 412734193 ps
CPU time 0.82 seconds
Started Jul 13 06:47:12 PM PDT 24
Finished Jul 13 06:47:13 PM PDT 24
Peak memory 201684 kb
Host smart-b1f08782-82c9-4589-8693-c2f1e69e1d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468094978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.468094978
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.289577417
Short name T618
Test name
Test status
Simulation time 159578365656 ps
CPU time 185.44 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:50:14 PM PDT 24
Peak memory 201900 kb
Host smart-7333a777-4a85-4ca9-8f18-015302d0b137
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289577417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.289577417
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1365804428
Short name T575
Test name
Test status
Simulation time 331622317430 ps
CPU time 800 seconds
Started Jul 13 06:47:10 PM PDT 24
Finished Jul 13 07:00:31 PM PDT 24
Peak memory 201888 kb
Host smart-e93cfa89-7893-4d1c-b3f4-0fd2a033e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365804428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1365804428
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3354386513
Short name T790
Test name
Test status
Simulation time 487173823103 ps
CPU time 1171.54 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 07:06:45 PM PDT 24
Peak memory 201916 kb
Host smart-72557037-8bc9-4c70-a1ec-c5242bb0a256
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354386513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3354386513
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1700231949
Short name T156
Test name
Test status
Simulation time 330264158758 ps
CPU time 760.73 seconds
Started Jul 13 06:47:12 PM PDT 24
Finished Jul 13 06:59:54 PM PDT 24
Peak memory 201928 kb
Host smart-17b50d30-7dfa-48ec-b798-03e02e9eb1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700231949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1700231949
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2649078192
Short name T639
Test name
Test status
Simulation time 490438996212 ps
CPU time 265.44 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:51:33 PM PDT 24
Peak memory 201876 kb
Host smart-69f52d36-ee00-40ff-9fc2-5bb46655bc65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649078192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2649078192
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2296903189
Short name T645
Test name
Test status
Simulation time 342545388873 ps
CPU time 209.99 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:50:40 PM PDT 24
Peak memory 201972 kb
Host smart-47c5d1a3-82b6-4217-9f0b-59de51231212
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296903189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2296903189
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1370449187
Short name T515
Test name
Test status
Simulation time 419477484768 ps
CPU time 969.57 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 07:03:24 PM PDT 24
Peak memory 201896 kb
Host smart-35003248-97cd-498a-9fac-42ab4795576b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370449187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1370449187
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3061636688
Short name T564
Test name
Test status
Simulation time 127084485510 ps
CPU time 509.62 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 202240 kb
Host smart-c2c0d6d8-9005-439a-9991-8ab25e1e7783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061636688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3061636688
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2544023538
Short name T514
Test name
Test status
Simulation time 23375242158 ps
CPU time 54.89 seconds
Started Jul 13 06:47:11 PM PDT 24
Finished Jul 13 06:48:07 PM PDT 24
Peak memory 201740 kb
Host smart-0ec17e9c-ef49-4fcd-92e6-a00bcb8ec31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544023538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2544023538
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4027642458
Short name T776
Test name
Test status
Simulation time 2987834544 ps
CPU time 1.72 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:11 PM PDT 24
Peak memory 201736 kb
Host smart-ad918f2d-c988-44a5-aed6-57afbf55d015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027642458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4027642458
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2436780150
Short name T349
Test name
Test status
Simulation time 6036855033 ps
CPU time 13.62 seconds
Started Jul 13 06:47:10 PM PDT 24
Finished Jul 13 06:47:25 PM PDT 24
Peak memory 201720 kb
Host smart-422b57e1-742b-46c0-bd6b-62dd1cd9396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436780150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2436780150
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3853108325
Short name T229
Test name
Test status
Simulation time 306229851904 ps
CPU time 404.93 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:53:56 PM PDT 24
Peak memory 202208 kb
Host smart-a39c4a77-aee3-4c80-a10c-a20c9a16dac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853108325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3853108325
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1623260142
Short name T775
Test name
Test status
Simulation time 391028614 ps
CPU time 1.48 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:47:18 PM PDT 24
Peak memory 201596 kb
Host smart-a8fe1cbf-5957-4b70-8a41-82ed88bf5b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623260142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1623260142
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.118544023
Short name T195
Test name
Test status
Simulation time 357902017290 ps
CPU time 210.72 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:50:45 PM PDT 24
Peak memory 201904 kb
Host smart-68ea0bfe-ffed-448c-9c8c-0546d43af1b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118544023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.118544023
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.967474447
Short name T393
Test name
Test status
Simulation time 327722332103 ps
CPU time 50.51 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:48:06 PM PDT 24
Peak memory 201868 kb
Host smart-0433c5e7-815e-4fcf-84cf-24fae79f41a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=967474447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.967474447
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.458743373
Short name T103
Test name
Test status
Simulation time 162033723363 ps
CPU time 372.75 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:53:27 PM PDT 24
Peak memory 201976 kb
Host smart-c3b09611-2f43-4757-bfcd-49c5dbd8a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458743373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.458743373
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.97419319
Short name T505
Test name
Test status
Simulation time 334515334442 ps
CPU time 781.61 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 201836 kb
Host smart-5bc485db-922a-4ff2-87b0-553db125de2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=97419319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed
.97419319
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3295313488
Short name T259
Test name
Test status
Simulation time 162404223241 ps
CPU time 189.24 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:50:19 PM PDT 24
Peak memory 201896 kb
Host smart-ef93c4e4-9cf3-468f-8c6c-a9d40126ea5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295313488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3295313488
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2578501451
Short name T488
Test name
Test status
Simulation time 405925898131 ps
CPU time 249.66 seconds
Started Jul 13 06:47:11 PM PDT 24
Finished Jul 13 06:51:21 PM PDT 24
Peak memory 201896 kb
Host smart-8b0fbe4a-d636-4fa4-ba1b-4a9b0085fcbf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578501451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2578501451
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1709283314
Short name T755
Test name
Test status
Simulation time 124228889068 ps
CPU time 605.05 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 06:57:19 PM PDT 24
Peak memory 202236 kb
Host smart-8b906c4e-92ec-40b5-a336-a4882e3ff1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709283314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1709283314
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4218081885
Short name T463
Test name
Test status
Simulation time 42291059505 ps
CPU time 9.92 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:47:21 PM PDT 24
Peak memory 201712 kb
Host smart-2db38309-fce7-4207-a78c-ac5554cace83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218081885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4218081885
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.693325414
Short name T612
Test name
Test status
Simulation time 3822212597 ps
CPU time 5.28 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:47:14 PM PDT 24
Peak memory 201744 kb
Host smart-b29c2d28-b692-4855-8d3b-380c38084234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693325414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.693325414
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1568512514
Short name T391
Test name
Test status
Simulation time 5790251535 ps
CPU time 4.47 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:47:14 PM PDT 24
Peak memory 201724 kb
Host smart-83181e5e-00fa-4cda-8f15-1ce043337ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568512514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1568512514
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.4256847317
Short name T97
Test name
Test status
Simulation time 357535998674 ps
CPU time 826.41 seconds
Started Jul 13 06:47:15 PM PDT 24
Finished Jul 13 07:01:02 PM PDT 24
Peak memory 201888 kb
Host smart-cf75c620-df25-40a1-b5dc-fd30d4f451dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256847317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.4256847317
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2307074893
Short name T592
Test name
Test status
Simulation time 396117895 ps
CPU time 1.57 seconds
Started Jul 13 06:47:18 PM PDT 24
Finished Jul 13 06:47:20 PM PDT 24
Peak memory 201640 kb
Host smart-98505deb-56e5-4be3-8edc-ad086c20877a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307074893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2307074893
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2176661050
Short name T46
Test name
Test status
Simulation time 320905179630 ps
CPU time 775.4 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 07:00:10 PM PDT 24
Peak memory 201992 kb
Host smart-dc4ab436-17d2-42d6-a7ae-4b42ed157f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176661050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2176661050
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.549648447
Short name T520
Test name
Test status
Simulation time 167779414362 ps
CPU time 380.22 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 06:53:35 PM PDT 24
Peak memory 201884 kb
Host smart-42d76562-a2d2-4c32-94a8-b11dc41f4e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549648447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.549648447
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2628151161
Short name T81
Test name
Test status
Simulation time 162238636763 ps
CPU time 342.21 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 201884 kb
Host smart-40d49eae-76ee-4e93-b1be-ecb500182464
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628151161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2628151161
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3335095763
Short name T669
Test name
Test status
Simulation time 163857183680 ps
CPU time 67.72 seconds
Started Jul 13 06:47:12 PM PDT 24
Finished Jul 13 06:48:20 PM PDT 24
Peak memory 201924 kb
Host smart-6b4ce4fc-422d-44a4-9030-4dc047f7ef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335095763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3335095763
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.234183814
Short name T159
Test name
Test status
Simulation time 328376726442 ps
CPU time 193.66 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:50:24 PM PDT 24
Peak memory 201908 kb
Host smart-eb0ef171-7499-4145-9644-977e04fc4e0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=234183814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.234183814
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2656892907
Short name T295
Test name
Test status
Simulation time 537858034113 ps
CPU time 609.04 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 201924 kb
Host smart-e3551f0b-b00e-407f-beae-e3aa074c4288
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656892907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2656892907
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4052925253
Short name T483
Test name
Test status
Simulation time 632221658882 ps
CPU time 711.27 seconds
Started Jul 13 06:47:08 PM PDT 24
Finished Jul 13 06:59:01 PM PDT 24
Peak memory 201904 kb
Host smart-67dec85b-9350-4f81-8924-7ef55c105ed1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052925253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4052925253
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.999842482
Short name T38
Test name
Test status
Simulation time 102100834101 ps
CPU time 533.47 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:56:12 PM PDT 24
Peak memory 202208 kb
Host smart-a7578402-d630-4b0d-b053-21398c5d16a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999842482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.999842482
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2764501478
Short name T734
Test name
Test status
Simulation time 32629504223 ps
CPU time 17.54 seconds
Started Jul 13 06:47:13 PM PDT 24
Finished Jul 13 06:47:31 PM PDT 24
Peak memory 201748 kb
Host smart-d436fc59-aedb-4032-b291-dc8402b3ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764501478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2764501478
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2926385042
Short name T710
Test name
Test status
Simulation time 4451208725 ps
CPU time 5.96 seconds
Started Jul 13 06:47:11 PM PDT 24
Finished Jul 13 06:47:18 PM PDT 24
Peak memory 201672 kb
Host smart-28bb3109-9310-440d-9936-ee8e6d18eccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926385042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2926385042
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1609658309
Short name T726
Test name
Test status
Simulation time 5691098534 ps
CPU time 7.63 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:47:23 PM PDT 24
Peak memory 201724 kb
Host smart-c2036ca4-efbd-4f60-a739-3c7c54aca206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609658309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1609658309
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3093193776
Short name T546
Test name
Test status
Simulation time 452964520891 ps
CPU time 1480.29 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 07:11:59 PM PDT 24
Peak memory 212284 kb
Host smart-4116b41f-cc75-4afa-b9b4-53c2ce8ca552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093193776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3093193776
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1026694918
Short name T355
Test name
Test status
Simulation time 357785437 ps
CPU time 1.38 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:47:19 PM PDT 24
Peak memory 201664 kb
Host smart-a977d98b-7500-47da-969f-1567539f6f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026694918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1026694918
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1080859012
Short name T244
Test name
Test status
Simulation time 185720228670 ps
CPU time 421.06 seconds
Started Jul 13 06:47:22 PM PDT 24
Finished Jul 13 06:54:24 PM PDT 24
Peak memory 201988 kb
Host smart-0d0c9698-0231-4289-b5ae-1ea0e7a7e593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080859012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1080859012
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.778911070
Short name T108
Test name
Test status
Simulation time 161326029348 ps
CPU time 353.75 seconds
Started Jul 13 06:47:14 PM PDT 24
Finished Jul 13 06:53:09 PM PDT 24
Peak memory 201916 kb
Host smart-22a018de-99d2-49cb-bbf8-1b835a4123e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778911070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.778911070
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1826907506
Short name T177
Test name
Test status
Simulation time 160193071976 ps
CPU time 306.93 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 06:52:29 PM PDT 24
Peak memory 201848 kb
Host smart-302a2fec-0367-4a60-a4d3-15e193ff8dcd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826907506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1826907506
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1050683826
Short name T732
Test name
Test status
Simulation time 491082226786 ps
CPU time 529.2 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 06:56:12 PM PDT 24
Peak memory 201984 kb
Host smart-cd360430-e8d5-4576-9a05-e093c4542fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050683826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1050683826
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2381702781
Short name T511
Test name
Test status
Simulation time 163950603819 ps
CPU time 99.89 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 06:49:00 PM PDT 24
Peak memory 201832 kb
Host smart-4af44bb6-d75b-46e9-bc6c-e23bf98fb6a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381702781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2381702781
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3036923507
Short name T560
Test name
Test status
Simulation time 177288416293 ps
CPU time 49.45 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:48:17 PM PDT 24
Peak memory 201988 kb
Host smart-4dcc0076-d16d-4328-92f5-46c70efd1ca2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036923507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3036923507
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2302624687
Short name T626
Test name
Test status
Simulation time 405547970239 ps
CPU time 771.49 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 07:00:08 PM PDT 24
Peak memory 201896 kb
Host smart-4cc9c06e-4652-42ed-ba02-b22744a00142
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302624687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2302624687
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3293214716
Short name T590
Test name
Test status
Simulation time 92165378295 ps
CPU time 460.31 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:54:59 PM PDT 24
Peak memory 202232 kb
Host smart-735d5993-b69b-4648-935b-b8f62c97e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293214716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3293214716
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.697990179
Short name T7
Test name
Test status
Simulation time 38435235382 ps
CPU time 86.43 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:48:53 PM PDT 24
Peak memory 201736 kb
Host smart-1efcebe4-4a4b-4be0-8457-47ca993e1e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697990179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.697990179
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2738801943
Short name T563
Test name
Test status
Simulation time 3274769742 ps
CPU time 1.16 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:47:18 PM PDT 24
Peak memory 201700 kb
Host smart-ae46c6e1-9e5b-4b00-b0b7-4760dce31e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738801943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2738801943
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.4203422442
Short name T631
Test name
Test status
Simulation time 5986251867 ps
CPU time 15.22 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 06:47:37 PM PDT 24
Peak memory 201720 kb
Host smart-979915f7-7d35-42f9-ac41-d0b0453d31fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203422442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.4203422442
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1027472642
Short name T615
Test name
Test status
Simulation time 265853200492 ps
CPU time 468.3 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:55:08 PM PDT 24
Peak memory 201964 kb
Host smart-8e8d2400-c781-496d-8fd5-282e7f92984c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027472642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1027472642
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1214086685
Short name T475
Test name
Test status
Simulation time 68427674133 ps
CPU time 102.68 seconds
Started Jul 13 06:47:23 PM PDT 24
Finished Jul 13 06:49:06 PM PDT 24
Peak memory 210572 kb
Host smart-238ea5d1-7101-4ae6-a96d-e2c2062b6827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214086685 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1214086685
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1125121658
Short name T437
Test name
Test status
Simulation time 307597051 ps
CPU time 1.31 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:47:20 PM PDT 24
Peak memory 201696 kb
Host smart-9544a7c2-9598-4d75-8546-51479626542c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125121658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1125121658
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2006516374
Short name T326
Test name
Test status
Simulation time 164484588212 ps
CPU time 56.33 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 06:48:18 PM PDT 24
Peak memory 201912 kb
Host smart-35a30837-4f13-427f-b424-28f8c70db0b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006516374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2006516374
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4028592102
Short name T567
Test name
Test status
Simulation time 498026124868 ps
CPU time 136.04 seconds
Started Jul 13 06:47:22 PM PDT 24
Finished Jul 13 06:49:39 PM PDT 24
Peak memory 201900 kb
Host smart-727ef667-a495-460b-affb-8ffb146ea692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028592102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4028592102
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3070292296
Short name T366
Test name
Test status
Simulation time 493276958555 ps
CPU time 576.32 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 06:56:58 PM PDT 24
Peak memory 201856 kb
Host smart-ae72e93d-3667-442e-acc7-961cec5d1c02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070292296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3070292296
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1812540102
Short name T147
Test name
Test status
Simulation time 325676727984 ps
CPU time 149.76 seconds
Started Jul 13 06:47:23 PM PDT 24
Finished Jul 13 06:49:53 PM PDT 24
Peak memory 201944 kb
Host smart-3f39b991-b8da-4a38-ba7e-8d5a6bc4e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812540102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1812540102
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.547931076
Short name T510
Test name
Test status
Simulation time 166171322548 ps
CPU time 355.13 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:53:12 PM PDT 24
Peak memory 201972 kb
Host smart-ccb8a5d1-d6f2-4553-a220-02d0db344b6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=547931076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.547931076
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1398610143
Short name T287
Test name
Test status
Simulation time 196522989355 ps
CPU time 112.13 seconds
Started Jul 13 06:47:23 PM PDT 24
Finished Jul 13 06:49:15 PM PDT 24
Peak memory 201972 kb
Host smart-10677f50-4143-482f-a5a6-20fc7595fba1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398610143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1398610143
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.610777228
Short name T191
Test name
Test status
Simulation time 626404617263 ps
CPU time 1452.41 seconds
Started Jul 13 06:47:22 PM PDT 24
Finished Jul 13 07:11:36 PM PDT 24
Peak memory 201824 kb
Host smart-c70c1aa1-243f-4e45-845f-762b1fff5951
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610777228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.610777228
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.757554685
Short name T337
Test name
Test status
Simulation time 69597792254 ps
CPU time 370.18 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:53:37 PM PDT 24
Peak memory 202216 kb
Host smart-24a5e7f2-7a07-40ae-9d08-0c83270890c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757554685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.757554685
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.500998914
Short name T757
Test name
Test status
Simulation time 35579034607 ps
CPU time 27.05 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:47:46 PM PDT 24
Peak memory 201732 kb
Host smart-59e40236-623b-4ab3-bbe2-04956f4d67b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500998914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.500998914
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3477741655
Short name T381
Test name
Test status
Simulation time 5007650053 ps
CPU time 12.28 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 06:47:35 PM PDT 24
Peak memory 201716 kb
Host smart-015868df-381d-4789-b9e6-3aa24c50d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477741655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3477741655
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2063749166
Short name T43
Test name
Test status
Simulation time 5810455574 ps
CPU time 13.69 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:47:34 PM PDT 24
Peak memory 201664 kb
Host smart-e453970e-19b4-4d7b-aa94-0b380e145e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063749166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2063749166
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2045856576
Short name T653
Test name
Test status
Simulation time 57251019114 ps
CPU time 32.92 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 06:47:55 PM PDT 24
Peak memory 201712 kb
Host smart-c78a1447-b34d-44a6-b703-82a1af320f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045856576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2045856576
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3357266790
Short name T23
Test name
Test status
Simulation time 52067849809 ps
CPU time 70.33 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 06:48:32 PM PDT 24
Peak memory 210688 kb
Host smart-584fa224-a834-4684-abd9-e022470d2579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357266790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3357266790
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.717743944
Short name T754
Test name
Test status
Simulation time 336865443 ps
CPU time 0.99 seconds
Started Jul 13 06:47:18 PM PDT 24
Finished Jul 13 06:47:20 PM PDT 24
Peak memory 201656 kb
Host smart-d4d8c4bd-4ef8-446f-bff9-85b13deaa1b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717743944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.717743944
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.432647994
Short name T211
Test name
Test status
Simulation time 172504196828 ps
CPU time 99.02 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:48:57 PM PDT 24
Peak memory 202016 kb
Host smart-b0ea5433-a049-45d1-8cc4-bdba8d03faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432647994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.432647994
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2775644664
Short name T275
Test name
Test status
Simulation time 488762049683 ps
CPU time 545.19 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 06:56:28 PM PDT 24
Peak memory 201912 kb
Host smart-e0f4e717-95c6-4460-8f73-8c6c8814b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775644664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2775644664
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3706518904
Short name T1
Test name
Test status
Simulation time 485316028891 ps
CPU time 1078.57 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 07:05:20 PM PDT 24
Peak memory 201884 kb
Host smart-f9e74b94-94d7-440f-85d4-af5a47fce5e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706518904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3706518904
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3455588433
Short name T188
Test name
Test status
Simulation time 491373811310 ps
CPU time 66.02 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 06:48:27 PM PDT 24
Peak memory 201964 kb
Host smart-fbcc2c59-5ec4-4037-b822-aef94fddebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455588433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3455588433
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3391915400
Short name T478
Test name
Test status
Simulation time 482317900144 ps
CPU time 74.16 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:48:41 PM PDT 24
Peak memory 201900 kb
Host smart-87c82659-d4e1-4f55-a0d1-a85e52473c8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391915400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3391915400
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2338692935
Short name T148
Test name
Test status
Simulation time 173798811184 ps
CPU time 180.26 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 06:50:22 PM PDT 24
Peak memory 202000 kb
Host smart-7ccbdb23-f670-483f-9620-4ebc965af89f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338692935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2338692935
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2578797775
Short name T685
Test name
Test status
Simulation time 407694073715 ps
CPU time 151.66 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:49:52 PM PDT 24
Peak memory 201912 kb
Host smart-47c60b2e-41ec-4281-ba67-fcee0f962bbb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578797775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2578797775
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1594231125
Short name T598
Test name
Test status
Simulation time 101026030932 ps
CPU time 330.49 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:52:51 PM PDT 24
Peak memory 202224 kb
Host smart-ede65aba-79d3-4dc1-81de-9473b3d46a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594231125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1594231125
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.247928579
Short name T413
Test name
Test status
Simulation time 32631321242 ps
CPU time 18.67 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:47:37 PM PDT 24
Peak memory 201704 kb
Host smart-6b614d33-3a23-4a68-bd38-f8f2ca0a0c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247928579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.247928579
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3631801793
Short name T399
Test name
Test status
Simulation time 3864029451 ps
CPU time 9.94 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:47:29 PM PDT 24
Peak memory 201556 kb
Host smart-c25618e2-7871-49cf-b1a1-0f57b368c738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631801793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3631801793
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2299868824
Short name T694
Test name
Test status
Simulation time 5588311985 ps
CPU time 7.31 seconds
Started Jul 13 06:47:18 PM PDT 24
Finished Jul 13 06:47:27 PM PDT 24
Peak memory 201704 kb
Host smart-295e4c95-5628-4213-bbeb-69e1e5b09ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299868824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2299868824
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3338145795
Short name T35
Test name
Test status
Simulation time 17068751047 ps
CPU time 21.06 seconds
Started Jul 13 06:47:17 PM PDT 24
Finished Jul 13 06:47:39 PM PDT 24
Peak memory 202004 kb
Host smart-01d299c3-5ca9-4964-b58f-d1f79e121526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338145795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3338145795
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1945860342
Short name T324
Test name
Test status
Simulation time 262623115026 ps
CPU time 191.29 seconds
Started Jul 13 06:47:23 PM PDT 24
Finished Jul 13 06:50:35 PM PDT 24
Peak memory 210612 kb
Host smart-61fd5943-41bc-4948-97f9-034c9a350b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945860342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1945860342
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1649327287
Short name T71
Test name
Test status
Simulation time 391426118 ps
CPU time 1.02 seconds
Started Jul 13 06:47:25 PM PDT 24
Finished Jul 13 06:47:26 PM PDT 24
Peak memory 201656 kb
Host smart-154abe89-42b4-4dfd-816b-daaf242d7b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649327287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1649327287
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1798915498
Short name T226
Test name
Test status
Simulation time 175168195134 ps
CPU time 83.93 seconds
Started Jul 13 06:47:15 PM PDT 24
Finished Jul 13 06:48:40 PM PDT 24
Peak memory 201888 kb
Host smart-9c734adc-786d-4abb-8d45-dbb4e3bd2b03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798915498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1798915498
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.127116231
Short name T240
Test name
Test status
Simulation time 163236557892 ps
CPU time 46.8 seconds
Started Jul 13 06:47:16 PM PDT 24
Finished Jul 13 06:48:04 PM PDT 24
Peak memory 201912 kb
Host smart-436ce2ec-17c4-4215-b6a3-ef2680a850e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127116231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.127116231
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3396667359
Short name T303
Test name
Test status
Simulation time 169004428069 ps
CPU time 382.5 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:53:43 PM PDT 24
Peak memory 201868 kb
Host smart-09a3a6a0-c6ff-4115-91d6-ababef62f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396667359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3396667359
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2790679990
Short name T424
Test name
Test status
Simulation time 496835741438 ps
CPU time 606.77 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:57:27 PM PDT 24
Peak memory 201912 kb
Host smart-5ac59dcc-21b6-4c82-93a5-5abaae78c20e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790679990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2790679990
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3690812991
Short name T212
Test name
Test status
Simulation time 168277529028 ps
CPU time 95.55 seconds
Started Jul 13 06:47:33 PM PDT 24
Finished Jul 13 06:49:09 PM PDT 24
Peak memory 202124 kb
Host smart-54c2a41a-cb0f-44ff-bbaf-36baffcf8771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690812991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3690812991
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3609398225
Short name T791
Test name
Test status
Simulation time 492630142754 ps
CPU time 153.41 seconds
Started Jul 13 06:47:18 PM PDT 24
Finished Jul 13 06:49:52 PM PDT 24
Peak memory 201960 kb
Host smart-e7ef2e98-8941-4a8d-87e1-7842eebc6839
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609398225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3609398225
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1803857423
Short name T699
Test name
Test status
Simulation time 606129675735 ps
CPU time 777.57 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 201880 kb
Host smart-8491943c-a01f-4c22-ae21-f6395a513e3e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803857423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1803857423
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1095385275
Short name T178
Test name
Test status
Simulation time 65803172494 ps
CPU time 206.27 seconds
Started Jul 13 06:47:29 PM PDT 24
Finished Jul 13 06:50:56 PM PDT 24
Peak memory 202448 kb
Host smart-29c2ed9c-2fa1-46b2-bf94-9c6d39453edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095385275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1095385275
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3026821455
Short name T756
Test name
Test status
Simulation time 24102658994 ps
CPU time 11.89 seconds
Started Jul 13 06:47:22 PM PDT 24
Finished Jul 13 06:47:35 PM PDT 24
Peak memory 201648 kb
Host smart-82937ce2-b3d7-4731-ab12-7e3b960a7a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026821455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3026821455
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3995256313
Short name T786
Test name
Test status
Simulation time 3588404808 ps
CPU time 9.07 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 06:47:31 PM PDT 24
Peak memory 201728 kb
Host smart-defc1442-4e0e-4678-b6f8-8718d1108769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995256313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3995256313
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3008674716
Short name T94
Test name
Test status
Simulation time 6030313846 ps
CPU time 1.85 seconds
Started Jul 13 06:47:20 PM PDT 24
Finished Jul 13 06:47:23 PM PDT 24
Peak memory 201736 kb
Host smart-2c2cfbcd-1397-482b-bcd8-59cf40c9cf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008674716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3008674716
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.46550564
Short name T703
Test name
Test status
Simulation time 256972430605 ps
CPU time 250.82 seconds
Started Jul 13 06:47:24 PM PDT 24
Finished Jul 13 06:51:36 PM PDT 24
Peak memory 210540 kb
Host smart-0540afc0-bac8-4960-b737-a9768821c775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46550564 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.46550564
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.337454261
Short name T530
Test name
Test status
Simulation time 386915751 ps
CPU time 0.86 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:46:50 PM PDT 24
Peak memory 201676 kb
Host smart-087352da-2f05-40ec-ac89-8d6b9747f0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337454261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.337454261
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.483718765
Short name T222
Test name
Test status
Simulation time 177413497649 ps
CPU time 364.11 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:52:43 PM PDT 24
Peak memory 201964 kb
Host smart-aa7338a8-a7c9-4fc1-9254-d5e0c2ce32d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483718765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.483718765
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2598492511
Short name T197
Test name
Test status
Simulation time 164424407740 ps
CPU time 103.42 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:48:32 PM PDT 24
Peak memory 201988 kb
Host smart-b38da1f5-5020-4e6d-b147-b757dc94376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598492511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2598492511
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2890823356
Short name T235
Test name
Test status
Simulation time 327641585593 ps
CPU time 208.33 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:50:10 PM PDT 24
Peak memory 201960 kb
Host smart-5e87b385-dd1e-44a4-8bc7-5230f5bc8702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890823356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2890823356
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.868007275
Short name T218
Test name
Test status
Simulation time 495525153959 ps
CPU time 464.64 seconds
Started Jul 13 06:46:45 PM PDT 24
Finished Jul 13 06:54:30 PM PDT 24
Peak memory 201908 kb
Host smart-e4550f74-483c-458f-a7cb-e09fef605e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868007275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.868007275
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1993674947
Short name T395
Test name
Test status
Simulation time 328464314553 ps
CPU time 259.17 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:51:00 PM PDT 24
Peak memory 201892 kb
Host smart-df801e0b-07c4-4680-9469-dfe29dc856c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993674947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1993674947
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3258225640
Short name T763
Test name
Test status
Simulation time 666588491756 ps
CPU time 374.9 seconds
Started Jul 13 06:46:44 PM PDT 24
Finished Jul 13 06:53:00 PM PDT 24
Peak memory 201980 kb
Host smart-1fb20f4e-546b-4942-bb60-9aea465671ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258225640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3258225640
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2095177797
Short name T410
Test name
Test status
Simulation time 197527341331 ps
CPU time 119.36 seconds
Started Jul 13 06:46:40 PM PDT 24
Finished Jul 13 06:48:41 PM PDT 24
Peak memory 201872 kb
Host smart-2c61d982-0740-40f3-acfb-2a4fa0d3af38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095177797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2095177797
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2608444673
Short name T714
Test name
Test status
Simulation time 99911235458 ps
CPU time 327.57 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:52:14 PM PDT 24
Peak memory 202216 kb
Host smart-ebed81bd-68da-4b0a-aa4f-4cb0ce31c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608444673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2608444673
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.228639748
Short name T543
Test name
Test status
Simulation time 35775342653 ps
CPU time 22.36 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:47:11 PM PDT 24
Peak memory 201748 kb
Host smart-d856e516-16b2-43c8-9b39-fd5a16ce818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228639748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.228639748
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1229817323
Short name T179
Test name
Test status
Simulation time 5151720573 ps
CPU time 3.61 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:46:55 PM PDT 24
Peak memory 200856 kb
Host smart-55781dd2-8255-4378-b050-3e7be4fa328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229817323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1229817323
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1509077611
Short name T78
Test name
Test status
Simulation time 8363735638 ps
CPU time 19.26 seconds
Started Jul 13 06:46:52 PM PDT 24
Finished Jul 13 06:47:12 PM PDT 24
Peak memory 218284 kb
Host smart-00e9572f-8ef0-48ec-a72f-4f3e0033aaed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509077611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1509077611
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4024167885
Short name T573
Test name
Test status
Simulation time 5928773873 ps
CPU time 4.23 seconds
Started Jul 13 06:46:38 PM PDT 24
Finished Jul 13 06:46:43 PM PDT 24
Peak memory 201696 kb
Host smart-d0786217-9851-466c-958c-0e48cd12abdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024167885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4024167885
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2976177167
Short name T387
Test name
Test status
Simulation time 92060612871 ps
CPU time 454.46 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:54:21 PM PDT 24
Peak memory 202224 kb
Host smart-66f68d53-0e50-4c72-97e9-f31cb3a70d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976177167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2976177167
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.247568212
Short name T675
Test name
Test status
Simulation time 49118888444 ps
CPU time 100.14 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:48:29 PM PDT 24
Peak memory 210536 kb
Host smart-b012490a-5332-4c03-b994-d78918d77de4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247568212 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.247568212
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.4225608395
Short name T716
Test name
Test status
Simulation time 425352139 ps
CPU time 1.62 seconds
Started Jul 13 06:47:33 PM PDT 24
Finished Jul 13 06:47:35 PM PDT 24
Peak memory 201668 kb
Host smart-b8a18131-6336-4b78-ac82-f267cc73fbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225608395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.4225608395
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3471504734
Short name T236
Test name
Test status
Simulation time 344516928089 ps
CPU time 701.27 seconds
Started Jul 13 06:47:24 PM PDT 24
Finished Jul 13 06:59:06 PM PDT 24
Peak memory 201960 kb
Host smart-4e741633-b82d-443a-9cbd-d6fa7b8b68b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471504734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3471504734
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4140954749
Short name T665
Test name
Test status
Simulation time 196202362102 ps
CPU time 210.83 seconds
Started Jul 13 06:47:28 PM PDT 24
Finished Jul 13 06:50:59 PM PDT 24
Peak memory 202064 kb
Host smart-2aaee7ff-dfa3-4b21-9445-1dd44d57a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140954749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4140954749
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3127197412
Short name T284
Test name
Test status
Simulation time 160311071731 ps
CPU time 373.45 seconds
Started Jul 13 06:47:19 PM PDT 24
Finished Jul 13 06:53:34 PM PDT 24
Peak memory 201888 kb
Host smart-8f3ef225-485c-4dea-bd36-d0d089a9bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127197412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3127197412
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3135202900
Short name T26
Test name
Test status
Simulation time 490856631619 ps
CPU time 1035.38 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 07:04:37 PM PDT 24
Peak memory 201908 kb
Host smart-fdfa69e6-60db-46f4-9c54-23423070cfe0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135202900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3135202900
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1296595541
Short name T727
Test name
Test status
Simulation time 324055963286 ps
CPU time 769.96 seconds
Started Jul 13 06:47:21 PM PDT 24
Finished Jul 13 07:00:12 PM PDT 24
Peak memory 201972 kb
Host smart-880c43ed-6e40-415a-8d16-877f2a85f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296595541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1296595541
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4091729499
Short name T620
Test name
Test status
Simulation time 169360874759 ps
CPU time 199.07 seconds
Started Jul 13 06:47:28 PM PDT 24
Finished Jul 13 06:50:48 PM PDT 24
Peak memory 202060 kb
Host smart-5de09a0f-4551-4dd1-ad66-ef85a6291a63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091729499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4091729499
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4016769998
Short name T142
Test name
Test status
Simulation time 354637210752 ps
CPU time 783.75 seconds
Started Jul 13 06:47:29 PM PDT 24
Finished Jul 13 07:00:33 PM PDT 24
Peak memory 202076 kb
Host smart-ed5cd9ae-1e38-45c9-8756-9c72217661b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016769998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4016769998
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3629045906
Short name T516
Test name
Test status
Simulation time 197078625308 ps
CPU time 227.23 seconds
Started Jul 13 06:47:29 PM PDT 24
Finished Jul 13 06:51:16 PM PDT 24
Peak memory 202068 kb
Host smart-0811e5fc-4d46-4329-9ab3-42a707f21f80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629045906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3629045906
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.748391415
Short name T6
Test name
Test status
Simulation time 121982958266 ps
CPU time 671.9 seconds
Started Jul 13 06:47:30 PM PDT 24
Finished Jul 13 06:58:42 PM PDT 24
Peak memory 202212 kb
Host smart-0644f567-d05b-4028-96b9-10d3d7993c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748391415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.748391415
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2947586810
Short name T683
Test name
Test status
Simulation time 34704463839 ps
CPU time 33.71 seconds
Started Jul 13 06:47:22 PM PDT 24
Finished Jul 13 06:47:56 PM PDT 24
Peak memory 201716 kb
Host smart-d05739a1-f1ae-4a8a-a436-dc32edd14360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947586810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2947586810
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2218675874
Short name T659
Test name
Test status
Simulation time 5009587521 ps
CPU time 3.32 seconds
Started Jul 13 06:47:24 PM PDT 24
Finished Jul 13 06:47:27 PM PDT 24
Peak memory 201712 kb
Host smart-4f1ef037-2457-4e80-9acc-7b7aec27366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218675874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2218675874
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1817136705
Short name T500
Test name
Test status
Simulation time 5769329660 ps
CPU time 7.78 seconds
Started Jul 13 06:47:28 PM PDT 24
Finished Jul 13 06:47:36 PM PDT 24
Peak memory 201876 kb
Host smart-c2ae60a8-d640-46e0-aa9f-b450a374e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817136705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1817136705
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2071374541
Short name T219
Test name
Test status
Simulation time 630680685783 ps
CPU time 1689.14 seconds
Started Jul 13 06:47:27 PM PDT 24
Finished Jul 13 07:15:37 PM PDT 24
Peak memory 202272 kb
Host smart-419b539b-1606-4285-ba4e-6dab153e63aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071374541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2071374541
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2643932415
Short name T249
Test name
Test status
Simulation time 73812211920 ps
CPU time 83.55 seconds
Started Jul 13 06:47:27 PM PDT 24
Finished Jul 13 06:48:52 PM PDT 24
Peak memory 210284 kb
Host smart-78d88ecb-9477-47e7-bbb1-40b23d1da93c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643932415 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2643932415
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2054839785
Short name T192
Test name
Test status
Simulation time 604495228 ps
CPU time 0.73 seconds
Started Jul 13 06:47:31 PM PDT 24
Finished Jul 13 06:47:32 PM PDT 24
Peak memory 201648 kb
Host smart-d224d6f8-fc8e-440d-bf27-13e8fa2bbe56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054839785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2054839785
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1801431296
Short name T713
Test name
Test status
Simulation time 324133261307 ps
CPU time 704.11 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:59:10 PM PDT 24
Peak memory 201972 kb
Host smart-f18358f1-e0a7-4a56-a454-07acdeb1bf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801431296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1801431296
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4082373580
Short name T134
Test name
Test status
Simulation time 495552239377 ps
CPU time 1062.1 seconds
Started Jul 13 06:47:33 PM PDT 24
Finished Jul 13 07:05:15 PM PDT 24
Peak memory 201984 kb
Host smart-226dd3d4-3132-4e17-a5e7-f6ab7989f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082373580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4082373580
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3596388517
Short name T158
Test name
Test status
Simulation time 493665813718 ps
CPU time 1216.94 seconds
Started Jul 13 06:47:33 PM PDT 24
Finished Jul 13 07:07:50 PM PDT 24
Peak memory 201868 kb
Host smart-df43522a-403a-4f25-b0c0-98e3bbd2c871
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596388517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3596388517
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1047919160
Short name T698
Test name
Test status
Simulation time 492138932734 ps
CPU time 280.2 seconds
Started Jul 13 06:47:33 PM PDT 24
Finished Jul 13 06:52:14 PM PDT 24
Peak memory 201864 kb
Host smart-d3816560-c10b-450d-97d9-d8d44bdffa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047919160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1047919160
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1587283907
Short name T636
Test name
Test status
Simulation time 158064625293 ps
CPU time 374.75 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:53:41 PM PDT 24
Peak memory 201880 kb
Host smart-9b349727-c2d7-4ac9-b464-248c0c015829
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587283907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1587283907
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.4248119338
Short name T661
Test name
Test status
Simulation time 338249241373 ps
CPU time 769.85 seconds
Started Jul 13 06:47:27 PM PDT 24
Finished Jul 13 07:00:18 PM PDT 24
Peak memory 201984 kb
Host smart-2275e626-8c5b-4793-8b8d-30a1ff9826fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248119338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.4248119338
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1115500068
Short name T576
Test name
Test status
Simulation time 576897732501 ps
CPU time 525.77 seconds
Started Jul 13 06:47:25 PM PDT 24
Finished Jul 13 06:56:11 PM PDT 24
Peak memory 201904 kb
Host smart-bbbb3f02-f738-41d7-ad72-19e18feeda31
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115500068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1115500068
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.457680892
Short name T751
Test name
Test status
Simulation time 33638538064 ps
CPU time 68.89 seconds
Started Jul 13 06:47:29 PM PDT 24
Finished Jul 13 06:48:38 PM PDT 24
Peak memory 201700 kb
Host smart-083d069b-a50b-456e-b9b8-fa88d1f3edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457680892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.457680892
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2534718159
Short name T736
Test name
Test status
Simulation time 3727928089 ps
CPU time 2.84 seconds
Started Jul 13 06:47:33 PM PDT 24
Finished Jul 13 06:47:36 PM PDT 24
Peak memory 201740 kb
Host smart-28c5ac08-6e5d-4f23-afe2-5ee5b3d91288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534718159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2534718159
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1839733509
Short name T638
Test name
Test status
Simulation time 5560379184 ps
CPU time 7.34 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:47:35 PM PDT 24
Peak memory 201728 kb
Host smart-a9d45596-d743-424f-9f93-bfdc265eba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839733509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1839733509
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2393846633
Short name T752
Test name
Test status
Simulation time 176958687607 ps
CPU time 110.94 seconds
Started Jul 13 06:47:27 PM PDT 24
Finished Jul 13 06:49:19 PM PDT 24
Peak memory 201968 kb
Host smart-ef563c00-e70a-4276-9070-e7639ebd092c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393846633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2393846633
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1113143964
Short name T767
Test name
Test status
Simulation time 287979000237 ps
CPU time 167.21 seconds
Started Jul 13 06:47:32 PM PDT 24
Finished Jul 13 06:50:20 PM PDT 24
Peak memory 210252 kb
Host smart-9e90b5b1-11e5-4208-8e1a-caa9b60a01c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113143964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1113143964
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4291001183
Short name T404
Test name
Test status
Simulation time 334941267 ps
CPU time 1.33 seconds
Started Jul 13 06:47:37 PM PDT 24
Finished Jul 13 06:47:38 PM PDT 24
Peak memory 201500 kb
Host smart-51283950-8a4d-4820-9b2c-8426cd1f3ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291001183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4291001183
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1191890099
Short name T281
Test name
Test status
Simulation time 526727717165 ps
CPU time 74.85 seconds
Started Jul 13 06:47:27 PM PDT 24
Finished Jul 13 06:48:43 PM PDT 24
Peak memory 201960 kb
Host smart-791716ad-e5c2-4dcd-a478-5577e4dd8907
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191890099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1191890099
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3019297951
Short name T194
Test name
Test status
Simulation time 158001001897 ps
CPU time 187.25 seconds
Started Jul 13 06:47:34 PM PDT 24
Finished Jul 13 06:50:41 PM PDT 24
Peak memory 202168 kb
Host smart-a9e0ad2d-c5d2-4ca2-91ed-05ef875b5513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019297951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3019297951
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.528650260
Short name T394
Test name
Test status
Simulation time 332546209955 ps
CPU time 157.13 seconds
Started Jul 13 06:47:31 PM PDT 24
Finished Jul 13 06:50:09 PM PDT 24
Peak memory 201868 kb
Host smart-5551c55e-91f0-43f9-959f-22590efea533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=528650260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.528650260
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1982488389
Short name T163
Test name
Test status
Simulation time 488963879012 ps
CPU time 327.27 seconds
Started Jul 13 06:47:35 PM PDT 24
Finished Jul 13 06:53:03 PM PDT 24
Peak memory 202068 kb
Host smart-60336d2a-a00d-4de6-91c9-3f654ea1506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982488389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1982488389
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.867915558
Short name T167
Test name
Test status
Simulation time 491619020052 ps
CPU time 319.4 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:52:46 PM PDT 24
Peak memory 201892 kb
Host smart-3f4eff4f-84f8-4b2b-9112-75f57080e99e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=867915558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.867915558
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.709423157
Short name T231
Test name
Test status
Simulation time 172691064815 ps
CPU time 376.22 seconds
Started Jul 13 06:47:26 PM PDT 24
Finished Jul 13 06:53:43 PM PDT 24
Peak memory 201912 kb
Host smart-0ce9d2f2-585d-4fc1-80f7-0bdf3417cb46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709423157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.709423157
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2368135134
Short name T524
Test name
Test status
Simulation time 612510936291 ps
CPU time 1236.68 seconds
Started Jul 13 06:47:33 PM PDT 24
Finished Jul 13 07:08:10 PM PDT 24
Peak memory 201892 kb
Host smart-683fcb8d-5d42-4850-b81d-603fa5c2e34f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368135134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2368135134
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2759201359
Short name T711
Test name
Test status
Simulation time 114984413204 ps
CPU time 427.58 seconds
Started Jul 13 06:47:37 PM PDT 24
Finished Jul 13 06:54:45 PM PDT 24
Peak memory 202320 kb
Host smart-2426fc40-3ae7-4ef8-9771-ec1432c9084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759201359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2759201359
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1404618477
Short name T623
Test name
Test status
Simulation time 28653232062 ps
CPU time 42.25 seconds
Started Jul 13 06:47:40 PM PDT 24
Finished Jul 13 06:48:22 PM PDT 24
Peak memory 201720 kb
Host smart-fce064ca-416a-441d-a42a-d8074f0249bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404618477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1404618477
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1307726347
Short name T799
Test name
Test status
Simulation time 3408991039 ps
CPU time 4.7 seconds
Started Jul 13 06:47:37 PM PDT 24
Finished Jul 13 06:47:42 PM PDT 24
Peak memory 201744 kb
Host smart-427d4705-5434-4a09-9997-31d8ada36cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307726347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1307726347
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.840190263
Short name T434
Test name
Test status
Simulation time 5704996587 ps
CPU time 6.94 seconds
Started Jul 13 06:47:27 PM PDT 24
Finished Jul 13 06:47:35 PM PDT 24
Peak memory 201644 kb
Host smart-922f8556-c83d-46ac-aa95-48eff48d99e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840190263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.840190263
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2402146274
Short name T87
Test name
Test status
Simulation time 210479160594 ps
CPU time 101.05 seconds
Started Jul 13 06:47:35 PM PDT 24
Finished Jul 13 06:49:16 PM PDT 24
Peak memory 201960 kb
Host smart-82c4211c-978d-42b3-9f27-fdd60a495c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402146274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2402146274
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2364143592
Short name T110
Test name
Test status
Simulation time 117602065494 ps
CPU time 250.34 seconds
Started Jul 13 06:47:35 PM PDT 24
Finished Jul 13 06:51:45 PM PDT 24
Peak memory 210236 kb
Host smart-f67a3e69-6d16-4cf7-aa1f-9db288c6e635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364143592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2364143592
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2235658891
Short name T580
Test name
Test status
Simulation time 326558910 ps
CPU time 1.26 seconds
Started Jul 13 06:47:37 PM PDT 24
Finished Jul 13 06:47:39 PM PDT 24
Peak memory 201648 kb
Host smart-ba2af202-0a0c-48c9-8753-d2ac83776027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235658891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2235658891
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2403893445
Short name T248
Test name
Test status
Simulation time 164376974186 ps
CPU time 19.84 seconds
Started Jul 13 06:47:35 PM PDT 24
Finished Jul 13 06:47:55 PM PDT 24
Peak memory 201936 kb
Host smart-5c4075e2-ada6-4cba-96cb-6ebf9c739a55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403893445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2403893445
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1480675692
Short name T285
Test name
Test status
Simulation time 332189537300 ps
CPU time 111.21 seconds
Started Jul 13 06:47:35 PM PDT 24
Finished Jul 13 06:49:27 PM PDT 24
Peak memory 201864 kb
Host smart-51775d34-598d-4c68-9a6e-7fbf17188406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480675692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1480675692
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1897385911
Short name T650
Test name
Test status
Simulation time 334809308911 ps
CPU time 440.11 seconds
Started Jul 13 06:47:36 PM PDT 24
Finished Jul 13 06:54:57 PM PDT 24
Peak memory 201904 kb
Host smart-0f43d123-4dac-4a59-bd95-53e95524f58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897385911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1897385911
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2204273327
Short name T787
Test name
Test status
Simulation time 325440916422 ps
CPU time 143.97 seconds
Started Jul 13 06:47:44 PM PDT 24
Finished Jul 13 06:50:08 PM PDT 24
Peak memory 201904 kb
Host smart-13948314-b424-499b-bf45-6d21197d115b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204273327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2204273327
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3749346331
Short name T477
Test name
Test status
Simulation time 328573012881 ps
CPU time 799.53 seconds
Started Jul 13 06:47:36 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 201964 kb
Host smart-6ea1aefe-9412-441f-ad9b-b1b628cdf4fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749346331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3749346331
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3973100391
Short name T187
Test name
Test status
Simulation time 375841198551 ps
CPU time 46.04 seconds
Started Jul 13 06:47:39 PM PDT 24
Finished Jul 13 06:48:25 PM PDT 24
Peak memory 201912 kb
Host smart-7867f764-8d7a-46cb-a23d-f533d14a52fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973100391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3973100391
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.784906649
Short name T415
Test name
Test status
Simulation time 611793280685 ps
CPU time 367.85 seconds
Started Jul 13 06:47:40 PM PDT 24
Finished Jul 13 06:53:48 PM PDT 24
Peak memory 201912 kb
Host smart-f5f0c7c5-9bb1-4fdd-8e70-33c4544d1d3f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784906649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.784906649
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.205417197
Short name T664
Test name
Test status
Simulation time 80692714364 ps
CPU time 276.93 seconds
Started Jul 13 06:47:36 PM PDT 24
Finished Jul 13 06:52:13 PM PDT 24
Peak memory 202244 kb
Host smart-62efb90b-5f3b-48f9-a251-79799ed7d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205417197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.205417197
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.928194791
Short name T579
Test name
Test status
Simulation time 33793139734 ps
CPU time 38.59 seconds
Started Jul 13 06:47:37 PM PDT 24
Finished Jul 13 06:48:16 PM PDT 24
Peak memory 201728 kb
Host smart-33c8a46c-5eed-4555-943a-35adc6705528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928194791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.928194791
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3469157582
Short name T549
Test name
Test status
Simulation time 5245734523 ps
CPU time 3.35 seconds
Started Jul 13 06:47:37 PM PDT 24
Finished Jul 13 06:47:41 PM PDT 24
Peak memory 201652 kb
Host smart-9715cc26-a73d-4bf7-a286-9ac11cd56507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469157582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3469157582
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.743246296
Short name T652
Test name
Test status
Simulation time 5834407550 ps
CPU time 13.16 seconds
Started Jul 13 06:47:37 PM PDT 24
Finished Jul 13 06:47:51 PM PDT 24
Peak memory 201724 kb
Host smart-c1488c82-eb95-4507-999e-80e580631d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743246296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.743246296
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1064420856
Short name T407
Test name
Test status
Simulation time 12363854620 ps
CPU time 4.03 seconds
Started Jul 13 06:47:39 PM PDT 24
Finished Jul 13 06:47:43 PM PDT 24
Peak memory 202144 kb
Host smart-7a841c30-5c86-477d-a60a-f5a5751087ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064420856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1064420856
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1582115200
Short name T21
Test name
Test status
Simulation time 243307351215 ps
CPU time 42.28 seconds
Started Jul 13 06:47:39 PM PDT 24
Finished Jul 13 06:48:21 PM PDT 24
Peak memory 202340 kb
Host smart-c4436608-9b50-458d-8798-8c62faaeb910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582115200 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1582115200
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2084961003
Short name T470
Test name
Test status
Simulation time 400390524 ps
CPU time 0.83 seconds
Started Jul 13 06:47:47 PM PDT 24
Finished Jul 13 06:47:49 PM PDT 24
Peak memory 201644 kb
Host smart-600880bf-2620-4fe7-b4ae-52061e2e46c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084961003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2084961003
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.4091973288
Short name T577
Test name
Test status
Simulation time 157748921179 ps
CPU time 174.42 seconds
Started Jul 13 06:47:47 PM PDT 24
Finished Jul 13 06:50:42 PM PDT 24
Peak memory 201944 kb
Host smart-f617eeca-f6d7-4245-afd5-a7be83206d2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091973288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.4091973288
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.222893132
Short name T12
Test name
Test status
Simulation time 494561782658 ps
CPU time 1169.02 seconds
Started Jul 13 06:47:45 PM PDT 24
Finished Jul 13 07:07:15 PM PDT 24
Peak memory 201948 kb
Host smart-6d6a0472-8215-4ff6-8a95-28503c2d44de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222893132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.222893132
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.917354104
Short name T662
Test name
Test status
Simulation time 321663382301 ps
CPU time 321.33 seconds
Started Jul 13 06:47:45 PM PDT 24
Finished Jul 13 06:53:06 PM PDT 24
Peak memory 201872 kb
Host smart-f6860168-6a97-4dd0-bd1f-30aa656f744f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=917354104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.917354104
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3521942569
Short name T403
Test name
Test status
Simulation time 166798296029 ps
CPU time 96.28 seconds
Started Jul 13 06:47:47 PM PDT 24
Finished Jul 13 06:49:24 PM PDT 24
Peak memory 201960 kb
Host smart-e5a75351-028e-49a0-ad87-1f8bbb4e307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521942569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3521942569
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.917691864
Short name T611
Test name
Test status
Simulation time 323284454384 ps
CPU time 188.13 seconds
Started Jul 13 06:47:46 PM PDT 24
Finished Jul 13 06:50:55 PM PDT 24
Peak memory 201892 kb
Host smart-273c7197-6f21-4faf-94bc-e0a4bb583bac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=917691864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.917691864
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2903742242
Short name T706
Test name
Test status
Simulation time 167349360299 ps
CPU time 100.55 seconds
Started Jul 13 06:47:47 PM PDT 24
Finished Jul 13 06:49:28 PM PDT 24
Peak memory 201920 kb
Host smart-8173bd0b-b217-4d69-8328-74e73623a1c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903742242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2903742242
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4281440156
Short name T545
Test name
Test status
Simulation time 410512917789 ps
CPU time 167.77 seconds
Started Jul 13 06:47:46 PM PDT 24
Finished Jul 13 06:50:34 PM PDT 24
Peak memory 201876 kb
Host smart-ab02f4aa-a08e-4f17-95cb-0cdc9e66c171
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281440156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4281440156
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3857043827
Short name T51
Test name
Test status
Simulation time 85691952140 ps
CPU time 278.46 seconds
Started Jul 13 06:47:45 PM PDT 24
Finished Jul 13 06:52:24 PM PDT 24
Peak memory 202240 kb
Host smart-dabf75d0-48c0-470a-bb87-b3dadc2ac585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857043827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3857043827
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1609600862
Short name T368
Test name
Test status
Simulation time 38906721725 ps
CPU time 92.73 seconds
Started Jul 13 06:47:45 PM PDT 24
Finished Jul 13 06:49:19 PM PDT 24
Peak memory 201700 kb
Host smart-1df5d52d-ad94-44b0-99fe-f68fc27aaaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609600862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1609600862
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.156629837
Short name T536
Test name
Test status
Simulation time 5110433637 ps
CPU time 12.93 seconds
Started Jul 13 06:47:45 PM PDT 24
Finished Jul 13 06:47:59 PM PDT 24
Peak memory 201704 kb
Host smart-a9e1d7b3-f69c-4929-971b-9002a19b8e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156629837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.156629837
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.84230224
Short name T737
Test name
Test status
Simulation time 5609306825 ps
CPU time 4.13 seconds
Started Jul 13 06:47:36 PM PDT 24
Finished Jul 13 06:47:41 PM PDT 24
Peak memory 201712 kb
Host smart-d5fb03a2-da79-4137-a80c-6c41955f5f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84230224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.84230224
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2481922653
Short name T745
Test name
Test status
Simulation time 645594473410 ps
CPU time 1464.04 seconds
Started Jul 13 06:47:45 PM PDT 24
Finished Jul 13 07:12:10 PM PDT 24
Peak memory 201980 kb
Host smart-c2272153-e55f-4980-9c8f-b3d55fe1be80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481922653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2481922653
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1091245259
Short name T265
Test name
Test status
Simulation time 192925786870 ps
CPU time 350.73 seconds
Started Jul 13 06:47:45 PM PDT 24
Finished Jul 13 06:53:36 PM PDT 24
Peak memory 210648 kb
Host smart-207a44ad-678c-4ba5-8881-554c7d6551a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091245259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1091245259
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3387307795
Short name T643
Test name
Test status
Simulation time 508001473 ps
CPU time 1.19 seconds
Started Jul 13 06:47:54 PM PDT 24
Finished Jul 13 06:47:56 PM PDT 24
Peak memory 201608 kb
Host smart-206547a9-0eed-40f6-bdf6-39b619269d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387307795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3387307795
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3071171705
Short name T314
Test name
Test status
Simulation time 513762353517 ps
CPU time 279.4 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:52:35 PM PDT 24
Peak memory 201972 kb
Host smart-f12cf8c9-a712-4f56-98e8-3c0cec955e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071171705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3071171705
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1285452351
Short name T238
Test name
Test status
Simulation time 326530768101 ps
CPU time 187.91 seconds
Started Jul 13 06:47:56 PM PDT 24
Finished Jul 13 06:51:04 PM PDT 24
Peak memory 201904 kb
Host smart-a31396f1-e952-4764-9912-79bb7575c5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285452351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1285452351
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3539645325
Short name T720
Test name
Test status
Simulation time 324125519433 ps
CPU time 197.62 seconds
Started Jul 13 06:47:57 PM PDT 24
Finished Jul 13 06:51:15 PM PDT 24
Peak memory 201892 kb
Host smart-2e40b760-18f8-4c30-9841-5a5b1124fc42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539645325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3539645325
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1965211856
Short name T630
Test name
Test status
Simulation time 164829122038 ps
CPU time 63.42 seconds
Started Jul 13 06:47:44 PM PDT 24
Finished Jul 13 06:48:48 PM PDT 24
Peak memory 201976 kb
Host smart-d918820b-6808-49ee-bb8e-9a3fedd43b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965211856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1965211856
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3143117779
Short name T501
Test name
Test status
Simulation time 164816356222 ps
CPU time 82.09 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:49:18 PM PDT 24
Peak memory 201916 kb
Host smart-3c408e97-280a-4ed9-85a0-23b835694311
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143117779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3143117779
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2482890981
Short name T31
Test name
Test status
Simulation time 352290640350 ps
CPU time 805.32 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 07:01:21 PM PDT 24
Peak memory 201900 kb
Host smart-0730e477-5189-48cf-a179-f03851c440de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482890981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2482890981
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.249524860
Short name T408
Test name
Test status
Simulation time 589475462158 ps
CPU time 328.84 seconds
Started Jul 13 06:47:58 PM PDT 24
Finished Jul 13 06:53:27 PM PDT 24
Peak memory 201956 kb
Host smart-0bc118ac-b425-43d8-b002-bed1a33136f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249524860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.249524860
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4137891539
Short name T464
Test name
Test status
Simulation time 129173111484 ps
CPU time 614.75 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:58:11 PM PDT 24
Peak memory 202264 kb
Host smart-8fe2d60c-921b-4836-acd9-637939529214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137891539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4137891539
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1512834552
Short name T439
Test name
Test status
Simulation time 34167644549 ps
CPU time 39.73 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:48:35 PM PDT 24
Peak memory 201724 kb
Host smart-ed416d85-5f2a-4732-97ec-f3e22283517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512834552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1512834552
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.924443348
Short name T647
Test name
Test status
Simulation time 3762066131 ps
CPU time 5.15 seconds
Started Jul 13 06:47:58 PM PDT 24
Finished Jul 13 06:48:03 PM PDT 24
Peak memory 201724 kb
Host smart-02e0d28b-7662-468d-8d48-62cbfd224769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924443348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.924443348
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.4071490526
Short name T622
Test name
Test status
Simulation time 5823264696 ps
CPU time 14.29 seconds
Started Jul 13 06:47:44 PM PDT 24
Finished Jul 13 06:47:59 PM PDT 24
Peak memory 201724 kb
Host smart-2d40400c-f644-4a46-aaeb-319511f051f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071490526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.4071490526
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.794195528
Short name T28
Test name
Test status
Simulation time 329635296944 ps
CPU time 237.72 seconds
Started Jul 13 06:47:56 PM PDT 24
Finished Jul 13 06:51:54 PM PDT 24
Peak memory 201896 kb
Host smart-391e8fcd-6424-4a09-9996-603ba2e81ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794195528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
794195528
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.656673973
Short name T252
Test name
Test status
Simulation time 116580071147 ps
CPU time 252.97 seconds
Started Jul 13 06:47:56 PM PDT 24
Finished Jul 13 06:52:10 PM PDT 24
Peak memory 210540 kb
Host smart-409d99be-2d33-42af-82ed-b512b76170fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656673973 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.656673973
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3220976507
Short name T453
Test name
Test status
Simulation time 311365343 ps
CPU time 0.91 seconds
Started Jul 13 06:47:54 PM PDT 24
Finished Jul 13 06:47:55 PM PDT 24
Peak memory 201664 kb
Host smart-29803947-959e-4bd5-803d-db39e736258f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220976507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3220976507
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.792034349
Short name T502
Test name
Test status
Simulation time 335945896709 ps
CPU time 150.46 seconds
Started Jul 13 06:47:56 PM PDT 24
Finished Jul 13 06:50:27 PM PDT 24
Peak memory 201924 kb
Host smart-2ebada47-abe4-44ba-9367-19571ab46f07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792034349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.792034349
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3793481239
Short name T513
Test name
Test status
Simulation time 173759334306 ps
CPU time 389.62 seconds
Started Jul 13 06:47:56 PM PDT 24
Finished Jul 13 06:54:26 PM PDT 24
Peak memory 201940 kb
Host smart-ac19004d-d628-4a1c-ba6b-2bd7f1a6b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793481239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3793481239
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1143928999
Short name T102
Test name
Test status
Simulation time 162382067495 ps
CPU time 172.06 seconds
Started Jul 13 06:47:54 PM PDT 24
Finished Jul 13 06:50:46 PM PDT 24
Peak memory 201956 kb
Host smart-4e5f842d-6d82-4f2c-b919-30aec53a2f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143928999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1143928999
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2892268257
Short name T487
Test name
Test status
Simulation time 498513952411 ps
CPU time 1073.11 seconds
Started Jul 13 06:47:54 PM PDT 24
Finished Jul 13 07:05:48 PM PDT 24
Peak memory 201872 kb
Host smart-90946e7e-0412-4521-b346-c8db90d7d60f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892268257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2892268257
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2097889878
Short name T784
Test name
Test status
Simulation time 329217178730 ps
CPU time 692.97 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:59:29 PM PDT 24
Peak memory 201952 kb
Host smart-442bedcd-dc0f-4089-b030-94c69ab590ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097889878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2097889878
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3042786937
Short name T554
Test name
Test status
Simulation time 160744981012 ps
CPU time 374.38 seconds
Started Jul 13 06:47:54 PM PDT 24
Finished Jul 13 06:54:09 PM PDT 24
Peak memory 201896 kb
Host smart-d6a6cef0-6bb8-4837-be2b-a7aba7fbb102
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042786937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3042786937
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3017068384
Short name T365
Test name
Test status
Simulation time 194606451973 ps
CPU time 243.17 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:51:59 PM PDT 24
Peak memory 201856 kb
Host smart-dcc39f35-1168-4f09-8784-a11c8e04941b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017068384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3017068384
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.4123804727
Short name T498
Test name
Test status
Simulation time 104121567987 ps
CPU time 428.31 seconds
Started Jul 13 06:47:56 PM PDT 24
Finished Jul 13 06:55:05 PM PDT 24
Peak memory 202256 kb
Host smart-de1ddaad-842b-46d9-bb09-93750db5decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123804727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4123804727
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.936530949
Short name T601
Test name
Test status
Simulation time 27720506481 ps
CPU time 15.19 seconds
Started Jul 13 06:47:58 PM PDT 24
Finished Jul 13 06:48:14 PM PDT 24
Peak memory 201660 kb
Host smart-d9063ebf-9731-48e9-bb68-0c39d1376f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936530949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.936530949
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1198119367
Short name T646
Test name
Test status
Simulation time 2948443973 ps
CPU time 3.7 seconds
Started Jul 13 06:47:57 PM PDT 24
Finished Jul 13 06:48:01 PM PDT 24
Peak memory 201720 kb
Host smart-221f8680-a5ad-4e23-8321-0271393ea6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198119367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1198119367
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2454776595
Short name T519
Test name
Test status
Simulation time 6191608324 ps
CPU time 3.84 seconds
Started Jul 13 06:47:54 PM PDT 24
Finished Jul 13 06:47:59 PM PDT 24
Peak memory 201720 kb
Host smart-ee219b2f-054f-4edc-a2fe-7a62764f3635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454776595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2454776595
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2776631236
Short name T313
Test name
Test status
Simulation time 463574498231 ps
CPU time 425.09 seconds
Started Jul 13 06:47:54 PM PDT 24
Finished Jul 13 06:55:00 PM PDT 24
Peak memory 201956 kb
Host smart-581ad526-e89a-4fe6-9e9d-a06e39e85077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776631236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2776631236
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4148557669
Short name T198
Test name
Test status
Simulation time 43856083289 ps
CPU time 70.67 seconds
Started Jul 13 06:47:56 PM PDT 24
Finished Jul 13 06:49:07 PM PDT 24
Peak memory 202028 kb
Host smart-a55394ef-4257-4bfd-8094-3a729680fa64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148557669 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4148557669
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2228928216
Short name T181
Test name
Test status
Simulation time 357664335 ps
CPU time 0.82 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:48:10 PM PDT 24
Peak memory 201672 kb
Host smart-33b906f8-7fa7-4e9f-92a9-699296e6eec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228928216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2228928216
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3017565523
Short name T297
Test name
Test status
Simulation time 167459470064 ps
CPU time 307.02 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:53:17 PM PDT 24
Peak memory 201988 kb
Host smart-349a5cf0-c88c-405d-b4f5-06ffed2dcb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017565523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3017565523
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.961354733
Short name T145
Test name
Test status
Simulation time 492727433611 ps
CPU time 201.08 seconds
Started Jul 13 06:48:11 PM PDT 24
Finished Jul 13 06:51:32 PM PDT 24
Peak memory 201888 kb
Host smart-17738938-cc68-4f4b-93e3-ace6035caf49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=961354733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.961354733
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1816532835
Short name T268
Test name
Test status
Simulation time 328412305413 ps
CPU time 710.38 seconds
Started Jul 13 06:47:55 PM PDT 24
Finished Jul 13 06:59:46 PM PDT 24
Peak memory 201904 kb
Host smart-8a0b6dcc-3280-4e68-bad5-d2b0d6471ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816532835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1816532835
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1319747789
Short name T369
Test name
Test status
Simulation time 326762527433 ps
CPU time 190.16 seconds
Started Jul 13 06:47:53 PM PDT 24
Finished Jul 13 06:51:04 PM PDT 24
Peak memory 201928 kb
Host smart-df52649a-f2db-40c2-ade5-a2bcef46ecf1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319747789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1319747789
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4081591264
Short name T190
Test name
Test status
Simulation time 403130485381 ps
CPU time 237.54 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:52:07 PM PDT 24
Peak memory 201896 kb
Host smart-62a5893f-bfe5-4f89-81d5-db8b89a70874
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081591264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4081591264
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.81264410
Short name T333
Test name
Test status
Simulation time 108788134244 ps
CPU time 438.68 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:55:29 PM PDT 24
Peak memory 202276 kb
Host smart-bdc08e97-8136-40dd-b9da-f99ca034dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81264410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.81264410
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2236742275
Short name T380
Test name
Test status
Simulation time 44485151439 ps
CPU time 10.54 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:48:20 PM PDT 24
Peak memory 201712 kb
Host smart-9805be59-9895-4492-a612-452c6259e1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236742275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2236742275
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.328690915
Short name T535
Test name
Test status
Simulation time 4472545407 ps
CPU time 11.06 seconds
Started Jul 13 06:48:10 PM PDT 24
Finished Jul 13 06:48:22 PM PDT 24
Peak memory 201740 kb
Host smart-9df60494-a5e3-4ba4-bbe9-54c69bbdb8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328690915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.328690915
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3414643666
Short name T624
Test name
Test status
Simulation time 6045606225 ps
CPU time 8.13 seconds
Started Jul 13 06:47:58 PM PDT 24
Finished Jul 13 06:48:06 PM PDT 24
Peak memory 201660 kb
Host smart-499a0d49-e3da-43b2-bf96-266776348cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414643666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3414643666
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2161165335
Short name T667
Test name
Test status
Simulation time 227528919229 ps
CPU time 1210.99 seconds
Started Jul 13 06:48:11 PM PDT 24
Finished Jul 13 07:08:23 PM PDT 24
Peak memory 218072 kb
Host smart-32a401f1-84e0-4d56-80a0-bc24a78da4b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161165335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2161165335
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1171735988
Short name T22
Test name
Test status
Simulation time 290034502374 ps
CPU time 191.98 seconds
Started Jul 13 06:48:08 PM PDT 24
Finished Jul 13 06:51:21 PM PDT 24
Peak memory 211616 kb
Host smart-cd1a2c6e-0165-4bf9-bda1-084b70c93d82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171735988 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1171735988
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1579222351
Short name T562
Test name
Test status
Simulation time 471524146 ps
CPU time 0.87 seconds
Started Jul 13 06:48:13 PM PDT 24
Finished Jul 13 06:48:14 PM PDT 24
Peak memory 201648 kb
Host smart-62c9ec0e-650a-4d86-919b-f8b79f7a2288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579222351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1579222351
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.362624457
Short name T781
Test name
Test status
Simulation time 200093967516 ps
CPU time 405.88 seconds
Started Jul 13 06:48:08 PM PDT 24
Finished Jul 13 06:54:54 PM PDT 24
Peak memory 201924 kb
Host smart-4bf43018-5558-4733-bcfd-1e38f67658fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362624457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.362624457
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.540128720
Short name T497
Test name
Test status
Simulation time 526942245350 ps
CPU time 637.41 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:58:47 PM PDT 24
Peak memory 201912 kb
Host smart-c2481235-bf6b-4c45-95d0-141ff74a87b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540128720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.540128720
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.296238834
Short name T768
Test name
Test status
Simulation time 492862122539 ps
CPU time 298.1 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:53:08 PM PDT 24
Peak memory 201904 kb
Host smart-05545b76-f9d1-4efa-becc-4db6c81a18c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296238834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.296238834
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1742344844
Short name T384
Test name
Test status
Simulation time 497879244867 ps
CPU time 433.27 seconds
Started Jul 13 06:48:10 PM PDT 24
Finished Jul 13 06:55:24 PM PDT 24
Peak memory 201868 kb
Host smart-85e8042c-0cd0-43ba-97a4-d5e11ee11193
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742344844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1742344844
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2312720263
Short name T135
Test name
Test status
Simulation time 166603103348 ps
CPU time 359.22 seconds
Started Jul 13 06:48:10 PM PDT 24
Finished Jul 13 06:54:10 PM PDT 24
Peak memory 201972 kb
Host smart-ec85db9e-2727-4d19-8f4f-10d487cf9650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312720263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2312720263
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3167727033
Short name T616
Test name
Test status
Simulation time 326202370208 ps
CPU time 720.67 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 201896 kb
Host smart-2176ea5d-6c14-4b50-ae29-8ccf582f544d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167727033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3167727033
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4082032232
Short name T561
Test name
Test status
Simulation time 202044502538 ps
CPU time 213.05 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:51:42 PM PDT 24
Peak memory 201960 kb
Host smart-a7d128cd-bab5-434d-8c63-f5cc82b1aa5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082032232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4082032232
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1254642051
Short name T604
Test name
Test status
Simulation time 201883073008 ps
CPU time 469.64 seconds
Started Jul 13 06:48:10 PM PDT 24
Finished Jul 13 06:56:01 PM PDT 24
Peak memory 201948 kb
Host smart-a5cd4406-9a87-432e-a6d1-a759d8791dc2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254642051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1254642051
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2200894768
Short name T362
Test name
Test status
Simulation time 106248463261 ps
CPU time 476.39 seconds
Started Jul 13 06:48:14 PM PDT 24
Finished Jul 13 06:56:11 PM PDT 24
Peak memory 202196 kb
Host smart-3866fee3-ba82-4425-8258-cff6a24aa5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200894768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2200894768
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3437430825
Short name T358
Test name
Test status
Simulation time 40802008198 ps
CPU time 43.52 seconds
Started Jul 13 06:48:19 PM PDT 24
Finished Jul 13 06:49:02 PM PDT 24
Peak memory 201708 kb
Host smart-585ad618-2bc1-4dd7-8e54-1924e0720da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437430825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3437430825
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3196890608
Short name T586
Test name
Test status
Simulation time 3888852156 ps
CPU time 3.23 seconds
Started Jul 13 06:48:09 PM PDT 24
Finished Jul 13 06:48:13 PM PDT 24
Peak memory 201704 kb
Host smart-00e91d4e-328a-4f8e-a6aa-e8524c8f93d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196890608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3196890608
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1957342640
Short name T409
Test name
Test status
Simulation time 5958369018 ps
CPU time 3.86 seconds
Started Jul 13 06:48:11 PM PDT 24
Finished Jul 13 06:48:16 PM PDT 24
Peak memory 201696 kb
Host smart-e16deac9-9d99-4fbb-9aea-0afb6e0ed4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957342640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1957342640
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.401936051
Short name T405
Test name
Test status
Simulation time 40245223327 ps
CPU time 6.37 seconds
Started Jul 13 06:48:18 PM PDT 24
Finished Jul 13 06:48:25 PM PDT 24
Peak memory 201728 kb
Host smart-9f54f523-1d6b-48e9-b513-0957c7a84e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401936051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
401936051
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1696191243
Short name T19
Test name
Test status
Simulation time 22282600788 ps
CPU time 49.64 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:49:06 PM PDT 24
Peak memory 210232 kb
Host smart-2aa2a665-a3f7-4224-998e-ea329e9ada18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696191243 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1696191243
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1800077457
Short name T539
Test name
Test status
Simulation time 473358255 ps
CPU time 0.86 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:48:16 PM PDT 24
Peak memory 201652 kb
Host smart-8c8c976a-d4b4-474d-8370-078391f5b7af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800077457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1800077457
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4121195491
Short name T436
Test name
Test status
Simulation time 494107458928 ps
CPU time 552.02 seconds
Started Jul 13 06:48:14 PM PDT 24
Finished Jul 13 06:57:27 PM PDT 24
Peak memory 201924 kb
Host smart-7e5097c3-12a8-4f5b-8e95-8dfe9b6f1b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121195491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4121195491
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.4195863490
Short name T676
Test name
Test status
Simulation time 173173722750 ps
CPU time 66.07 seconds
Started Jul 13 06:48:14 PM PDT 24
Finished Jul 13 06:49:21 PM PDT 24
Peak memory 202052 kb
Host smart-67b33e4f-cc96-455b-bce4-479f588cf876
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195863490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.4195863490
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3676854680
Short name T209
Test name
Test status
Simulation time 492671130085 ps
CPU time 1138.72 seconds
Started Jul 13 06:48:18 PM PDT 24
Finished Jul 13 07:07:17 PM PDT 24
Peak memory 201960 kb
Host smart-bef0b542-e029-4a33-b51f-80a52bef10f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676854680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3676854680
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1463261107
Short name T641
Test name
Test status
Simulation time 317693613841 ps
CPU time 683.83 seconds
Started Jul 13 06:48:12 PM PDT 24
Finished Jul 13 06:59:36 PM PDT 24
Peak memory 201912 kb
Host smart-1b9fd741-ca2e-4eeb-89c8-996fbd5e7b49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463261107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1463261107
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3726374915
Short name T8
Test name
Test status
Simulation time 204891440065 ps
CPU time 247.93 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:52:24 PM PDT 24
Peak memory 201940 kb
Host smart-0ab38900-dd34-4bdc-a28a-0ce53b07d1de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726374915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3726374915
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1751509676
Short name T335
Test name
Test status
Simulation time 79477907931 ps
CPU time 289.54 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:53:06 PM PDT 24
Peak memory 202232 kb
Host smart-f10a1951-39ba-4f4b-aac4-99230264a539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751509676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1751509676
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1992675101
Short name T797
Test name
Test status
Simulation time 36858413665 ps
CPU time 75.92 seconds
Started Jul 13 06:48:18 PM PDT 24
Finished Jul 13 06:49:35 PM PDT 24
Peak memory 201708 kb
Host smart-64169545-5ac7-4d95-9996-44755b4d860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992675101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1992675101
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3096385580
Short name T547
Test name
Test status
Simulation time 2809803108 ps
CPU time 3.89 seconds
Started Jul 13 06:48:14 PM PDT 24
Finished Jul 13 06:48:19 PM PDT 24
Peak memory 201664 kb
Host smart-f1298d12-6104-46d9-936d-665064aa014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096385580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3096385580
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1545880738
Short name T557
Test name
Test status
Simulation time 5745920957 ps
CPU time 2.22 seconds
Started Jul 13 06:48:14 PM PDT 24
Finished Jul 13 06:48:16 PM PDT 24
Peak memory 201728 kb
Host smart-34988d81-290c-48eb-a3cc-fa211a7c7b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545880738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1545880738
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.791747453
Short name T687
Test name
Test status
Simulation time 431501162298 ps
CPU time 1023.99 seconds
Started Jul 13 06:48:13 PM PDT 24
Finished Jul 13 07:05:18 PM PDT 24
Peak memory 210456 kb
Host smart-4058e9ff-9806-47b0-81d7-9d95ca2ea800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791747453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
791747453
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1846663998
Short name T60
Test name
Test status
Simulation time 99811096719 ps
CPU time 164.66 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:51:01 PM PDT 24
Peak memory 218136 kb
Host smart-2c6b044e-a3d8-492a-a9dc-b6569f912883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846663998 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1846663998
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4198876043
Short name T492
Test name
Test status
Simulation time 434402360 ps
CPU time 0.77 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:46:52 PM PDT 24
Peak memory 201648 kb
Host smart-5a6369b7-8530-4e96-bc2f-725b8c16d8dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198876043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4198876043
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.634036852
Short name T151
Test name
Test status
Simulation time 332107544457 ps
CPU time 79.62 seconds
Started Jul 13 06:46:49 PM PDT 24
Finished Jul 13 06:48:10 PM PDT 24
Peak memory 201960 kb
Host smart-b1bfa9a3-6051-49a8-bfe0-ee40dbb78e8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634036852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.634036852
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.4270191303
Short name T422
Test name
Test status
Simulation time 163408397183 ps
CPU time 155.77 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:49:25 PM PDT 24
Peak memory 201892 kb
Host smart-71cb2db0-5675-414b-8a32-8bd1eff62957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270191303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.4270191303
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3735382168
Short name T480
Test name
Test status
Simulation time 497228568352 ps
CPU time 180.01 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:49:57 PM PDT 24
Peak memory 201924 kb
Host smart-b958631d-ac24-483e-9472-8fd42a6d7527
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735382168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3735382168
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3706580638
Short name T672
Test name
Test status
Simulation time 324865168853 ps
CPU time 175.36 seconds
Started Jul 13 06:46:52 PM PDT 24
Finished Jul 13 06:49:48 PM PDT 24
Peak memory 201908 kb
Host smart-347bf6ab-24e0-4808-98cf-f0ed6ba79995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706580638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3706580638
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3572060111
Short name T416
Test name
Test status
Simulation time 334806516038 ps
CPU time 692.93 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:58:22 PM PDT 24
Peak memory 201912 kb
Host smart-20acd712-6a75-461f-a3b7-ee594b870e1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572060111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3572060111
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2742809096
Short name T759
Test name
Test status
Simulation time 553656313679 ps
CPU time 983.34 seconds
Started Jul 13 06:46:52 PM PDT 24
Finished Jul 13 07:03:16 PM PDT 24
Peak memory 201904 kb
Host smart-263d7f95-57ba-4933-9b35-ea8ea7482c8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742809096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2742809096
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2730401963
Short name T472
Test name
Test status
Simulation time 609294064804 ps
CPU time 758.55 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:59:28 PM PDT 24
Peak memory 201880 kb
Host smart-2ac6202a-1538-459f-a1f0-ac23bc7aeb83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730401963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2730401963
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1171993295
Short name T353
Test name
Test status
Simulation time 69235090229 ps
CPU time 282.67 seconds
Started Jul 13 06:46:47 PM PDT 24
Finished Jul 13 06:51:30 PM PDT 24
Peak memory 202176 kb
Host smart-d8f103f5-0e87-4133-980a-a9c83d64b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171993295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1171993295
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3467820527
Short name T679
Test name
Test status
Simulation time 28855762824 ps
CPU time 67.88 seconds
Started Jul 13 06:46:47 PM PDT 24
Finished Jul 13 06:47:56 PM PDT 24
Peak memory 201708 kb
Host smart-2e5849ad-dc53-40db-b55b-539c207a0603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467820527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3467820527
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1153829996
Short name T388
Test name
Test status
Simulation time 3532979738 ps
CPU time 2.54 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:46:50 PM PDT 24
Peak memory 201724 kb
Host smart-c4b25520-5eab-4e01-a9d6-d8be8b4f5626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153829996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1153829996
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.762782549
Short name T64
Test name
Test status
Simulation time 7846365183 ps
CPU time 4.84 seconds
Started Jul 13 06:46:54 PM PDT 24
Finished Jul 13 06:46:59 PM PDT 24
Peak memory 218304 kb
Host smart-1e39ab76-313a-408a-97a4-9fa43d930006
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762782549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.762782549
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.185890146
Short name T796
Test name
Test status
Simulation time 5722333651 ps
CPU time 7.49 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:46:57 PM PDT 24
Peak memory 201752 kb
Host smart-0083df10-aef8-44b1-abc8-d060c340fd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185890146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.185890146
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2115849954
Short name T32
Test name
Test status
Simulation time 6926126429 ps
CPU time 4.88 seconds
Started Jul 13 06:46:47 PM PDT 24
Finished Jul 13 06:46:53 PM PDT 24
Peak memory 201724 kb
Host smart-8dbc356e-4822-4f09-820f-85e3bb0cbe80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115849954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2115849954
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.627621649
Short name T247
Test name
Test status
Simulation time 286887137929 ps
CPU time 301.09 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:51:59 PM PDT 24
Peak memory 218120 kb
Host smart-e33d5c36-a2a2-4334-af30-fb8eda30c0a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627621649 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.627621649
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3640279899
Short name T370
Test name
Test status
Simulation time 357772432 ps
CPU time 0.84 seconds
Started Jul 13 06:48:22 PM PDT 24
Finished Jul 13 06:48:24 PM PDT 24
Peak memory 201700 kb
Host smart-ccf6177f-78b4-4c89-870f-80ea529fc319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640279899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3640279899
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2162889287
Short name T300
Test name
Test status
Simulation time 507253817439 ps
CPU time 142.89 seconds
Started Jul 13 06:48:22 PM PDT 24
Finished Jul 13 06:50:46 PM PDT 24
Peak memory 201928 kb
Host smart-c61f1363-8ffd-44e4-800b-7df83075248f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162889287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2162889287
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.626125652
Short name T795
Test name
Test status
Simulation time 505305112452 ps
CPU time 1142.63 seconds
Started Jul 13 06:48:23 PM PDT 24
Finished Jul 13 07:07:26 PM PDT 24
Peak memory 201912 kb
Host smart-040817ba-475b-4dd3-9c58-b1055072fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626125652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.626125652
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2244406797
Short name T550
Test name
Test status
Simulation time 170272792922 ps
CPU time 394.27 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:54:49 PM PDT 24
Peak memory 201904 kb
Host smart-b3363a07-1780-46d5-b3de-beb5f51b761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244406797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2244406797
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3112346831
Short name T574
Test name
Test status
Simulation time 167336874229 ps
CPU time 185.31 seconds
Started Jul 13 06:48:22 PM PDT 24
Finished Jul 13 06:51:28 PM PDT 24
Peak memory 201792 kb
Host smart-69932923-95f6-4f91-aab9-25e48e7d9bc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112346831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3112346831
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2483939762
Short name T137
Test name
Test status
Simulation time 488512510483 ps
CPU time 268.43 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:52:44 PM PDT 24
Peak memory 201964 kb
Host smart-84fb99fe-3485-4826-9172-8501bd54a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483939762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2483939762
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.462953576
Short name T382
Test name
Test status
Simulation time 329018371276 ps
CPU time 180.98 seconds
Started Jul 13 06:48:15 PM PDT 24
Finished Jul 13 06:51:17 PM PDT 24
Peak memory 201912 kb
Host smart-1d32be41-bdca-482f-93da-97e1d2b2c403
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=462953576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.462953576
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2076723087
Short name T430
Test name
Test status
Simulation time 205663967374 ps
CPU time 116.39 seconds
Started Jul 13 06:48:21 PM PDT 24
Finished Jul 13 06:50:18 PM PDT 24
Peak memory 201888 kb
Host smart-10a351e9-d7de-410f-8784-06ea8b51d16d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076723087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2076723087
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3706490997
Short name T193
Test name
Test status
Simulation time 71873747154 ps
CPU time 249.33 seconds
Started Jul 13 06:48:21 PM PDT 24
Finished Jul 13 06:52:31 PM PDT 24
Peak memory 202172 kb
Host smart-b6b5d96a-f6b7-49f7-b11b-7a5cc344e2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706490997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3706490997
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2620803513
Short name T733
Test name
Test status
Simulation time 34084778317 ps
CPU time 53.23 seconds
Started Jul 13 06:48:21 PM PDT 24
Finished Jul 13 06:49:15 PM PDT 24
Peak memory 201712 kb
Host smart-6907850f-2edd-4fc2-bfb6-6b4292905532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620803513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2620803513
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3886039213
Short name T503
Test name
Test status
Simulation time 2925947098 ps
CPU time 1.77 seconds
Started Jul 13 06:48:21 PM PDT 24
Finished Jul 13 06:48:23 PM PDT 24
Peak memory 201684 kb
Host smart-9470fbed-24be-44db-bb69-afb70a4eb150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886039213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3886039213
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3220856996
Short name T512
Test name
Test status
Simulation time 5951746248 ps
CPU time 4.79 seconds
Started Jul 13 06:48:14 PM PDT 24
Finished Jul 13 06:48:20 PM PDT 24
Peak memory 201696 kb
Host smart-c1c61009-2408-4be7-b9be-5b8a72828bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220856996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3220856996
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2116586023
Short name T702
Test name
Test status
Simulation time 39360239566 ps
CPU time 49.63 seconds
Started Jul 13 06:48:21 PM PDT 24
Finished Jul 13 06:49:11 PM PDT 24
Peak memory 201976 kb
Host smart-74f836b1-91b8-4f26-802d-fb08640cb82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116586023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2116586023
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1927371829
Short name T773
Test name
Test status
Simulation time 58571136798 ps
CPU time 103.36 seconds
Started Jul 13 06:48:23 PM PDT 24
Finished Jul 13 06:50:07 PM PDT 24
Peak memory 218672 kb
Host smart-d9b10a09-2347-49f2-9828-6a303575aaf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927371829 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1927371829
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.851468863
Short name T417
Test name
Test status
Simulation time 425275663 ps
CPU time 0.88 seconds
Started Jul 13 06:48:47 PM PDT 24
Finished Jul 13 06:48:48 PM PDT 24
Peak memory 201672 kb
Host smart-fe9cb724-84de-4bf6-846f-f5e3418729db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851468863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.851468863
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3793730980
Short name T764
Test name
Test status
Simulation time 499117374198 ps
CPU time 146 seconds
Started Jul 13 06:48:32 PM PDT 24
Finished Jul 13 06:50:58 PM PDT 24
Peak memory 201916 kb
Host smart-2b2b004e-1fff-4f9f-86cf-4d034d697e8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793730980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3793730980
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.397341860
Short name T682
Test name
Test status
Simulation time 488886423253 ps
CPU time 524.2 seconds
Started Jul 13 06:48:35 PM PDT 24
Finished Jul 13 06:57:19 PM PDT 24
Peak memory 201904 kb
Host smart-aa809c71-0696-4dae-96c3-31c1af6a7eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397341860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.397341860
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.22243656
Short name T412
Test name
Test status
Simulation time 165373422409 ps
CPU time 194.98 seconds
Started Jul 13 06:48:30 PM PDT 24
Finished Jul 13 06:51:46 PM PDT 24
Peak memory 201896 kb
Host smart-c7cc9747-8215-46aa-81e9-fd4fc4d8a168
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=22243656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt
_fixed.22243656
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2727957636
Short name T753
Test name
Test status
Simulation time 162821464640 ps
CPU time 185.59 seconds
Started Jul 13 06:48:32 PM PDT 24
Finished Jul 13 06:51:38 PM PDT 24
Peak memory 201900 kb
Host smart-835d97ed-eb64-4fff-86fa-a9ce890ed666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727957636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2727957636
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2533093647
Short name T541
Test name
Test status
Simulation time 494670037828 ps
CPU time 537.3 seconds
Started Jul 13 06:48:30 PM PDT 24
Finished Jul 13 06:57:28 PM PDT 24
Peak memory 201880 kb
Host smart-1a433967-5487-4796-809f-7617b60ab035
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533093647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2533093647
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2581536872
Short name T96
Test name
Test status
Simulation time 653801467569 ps
CPU time 1450.2 seconds
Started Jul 13 06:48:31 PM PDT 24
Finished Jul 13 07:12:42 PM PDT 24
Peak memory 201900 kb
Host smart-4394995d-c165-497e-89a6-90559d3c6019
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581536872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2581536872
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3036184555
Short name T518
Test name
Test status
Simulation time 190676073922 ps
CPU time 109.94 seconds
Started Jul 13 06:48:30 PM PDT 24
Finished Jul 13 06:50:21 PM PDT 24
Peak memory 201944 kb
Host smart-d6c0a8a9-482a-46a2-a710-1ae0475da6c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036184555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3036184555
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1457671867
Short name T447
Test name
Test status
Simulation time 94976913431 ps
CPU time 393.83 seconds
Started Jul 13 06:48:33 PM PDT 24
Finished Jul 13 06:55:07 PM PDT 24
Peak memory 202204 kb
Host smart-580169c5-9ba4-4029-aa5f-a4728e22baca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457671867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1457671867
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2598123173
Short name T446
Test name
Test status
Simulation time 42187761262 ps
CPU time 88.99 seconds
Started Jul 13 06:48:30 PM PDT 24
Finished Jul 13 06:50:00 PM PDT 24
Peak memory 201716 kb
Host smart-149cdf6c-1e2b-423b-bc7f-155d5542e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598123173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2598123173
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2760997269
Short name T359
Test name
Test status
Simulation time 5195394017 ps
CPU time 1.69 seconds
Started Jul 13 06:48:30 PM PDT 24
Finished Jul 13 06:48:32 PM PDT 24
Peak memory 201708 kb
Host smart-08554134-be58-4364-885b-b15def0ac804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760997269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2760997269
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.630361404
Short name T419
Test name
Test status
Simulation time 5639019995 ps
CPU time 13.1 seconds
Started Jul 13 06:48:30 PM PDT 24
Finished Jul 13 06:48:43 PM PDT 24
Peak memory 201720 kb
Host smart-81e2a0b0-34a8-4934-bed2-343174c06da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630361404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.630361404
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1467637364
Short name T762
Test name
Test status
Simulation time 21966076545 ps
CPU time 38.05 seconds
Started Jul 13 06:48:46 PM PDT 24
Finished Jul 13 06:49:25 PM PDT 24
Peak memory 210232 kb
Host smart-6e0cc96c-fad4-4b4f-bc39-dbc8457a4969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467637364 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1467637364
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2364742800
Short name T533
Test name
Test status
Simulation time 365549987 ps
CPU time 0.79 seconds
Started Jul 13 06:48:54 PM PDT 24
Finished Jul 13 06:48:55 PM PDT 24
Peak memory 201636 kb
Host smart-4fcec835-caf2-4402-b24e-e2a2dbbb5030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364742800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2364742800
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1018621873
Short name T461
Test name
Test status
Simulation time 177828463759 ps
CPU time 110.63 seconds
Started Jul 13 06:48:46 PM PDT 24
Finished Jul 13 06:50:37 PM PDT 24
Peak memory 201872 kb
Host smart-3068035b-95ff-4ade-9623-6f0d0cfad43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018621873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1018621873
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1979706330
Short name T288
Test name
Test status
Simulation time 160676841555 ps
CPU time 93.97 seconds
Started Jul 13 06:48:46 PM PDT 24
Finished Jul 13 06:50:20 PM PDT 24
Peak memory 201932 kb
Host smart-311f33cd-89be-42e7-bada-fa5ba2971168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979706330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1979706330
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2965621321
Short name T452
Test name
Test status
Simulation time 489113106610 ps
CPU time 301.51 seconds
Started Jul 13 06:48:46 PM PDT 24
Finished Jul 13 06:53:48 PM PDT 24
Peak memory 201872 kb
Host smart-b8904f77-885e-4a34-89cd-acf28d4bacc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965621321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2965621321
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.426324482
Short name T654
Test name
Test status
Simulation time 484322961920 ps
CPU time 1129.52 seconds
Started Jul 13 06:48:44 PM PDT 24
Finished Jul 13 07:07:33 PM PDT 24
Peak memory 201964 kb
Host smart-705c1caf-b5cd-4570-aa87-1956ddfa84eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426324482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.426324482
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3455027600
Short name T738
Test name
Test status
Simulation time 490727992995 ps
CPU time 282.42 seconds
Started Jul 13 06:48:44 PM PDT 24
Finished Jul 13 06:53:27 PM PDT 24
Peak memory 201900 kb
Host smart-60344143-a478-4527-b91c-8a6ad85b1cfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455027600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3455027600
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2951777001
Short name T162
Test name
Test status
Simulation time 178817315987 ps
CPU time 370.29 seconds
Started Jul 13 06:48:45 PM PDT 24
Finished Jul 13 06:54:55 PM PDT 24
Peak memory 201948 kb
Host smart-fec08955-7571-416e-bf1b-3bf800feddc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951777001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2951777001
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.980114101
Short name T385
Test name
Test status
Simulation time 205337744240 ps
CPU time 216.71 seconds
Started Jul 13 06:48:43 PM PDT 24
Finished Jul 13 06:52:21 PM PDT 24
Peak memory 201916 kb
Host smart-79f69b0a-0bf4-410a-8cb6-c70a5318bae7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980114101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.980114101
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1347370865
Short name T50
Test name
Test status
Simulation time 139075812745 ps
CPU time 525.41 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 202300 kb
Host smart-16f505cc-ca79-4625-aa32-2ce55cd29ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347370865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1347370865
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.228672872
Short name T688
Test name
Test status
Simulation time 42670220736 ps
CPU time 92.46 seconds
Started Jul 13 06:48:54 PM PDT 24
Finished Jul 13 06:50:27 PM PDT 24
Peak memory 201720 kb
Host smart-e9b0948b-92bb-4e45-b39f-523ad5f83050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228672872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.228672872
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.750792129
Short name T741
Test name
Test status
Simulation time 3496348522 ps
CPU time 8.19 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 06:49:05 PM PDT 24
Peak memory 201672 kb
Host smart-692352cc-87c5-4cfb-8313-001c992ab11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750792129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.750792129
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2366166681
Short name T406
Test name
Test status
Simulation time 5927272479 ps
CPU time 2.74 seconds
Started Jul 13 06:48:45 PM PDT 24
Finished Jul 13 06:48:48 PM PDT 24
Peak memory 201724 kb
Host smart-ee8f5825-8d7a-41fe-be12-1cdffc6357ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366166681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2366166681
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.50881221
Short name T697
Test name
Test status
Simulation time 162113967981 ps
CPU time 63.96 seconds
Started Jul 13 06:48:55 PM PDT 24
Finished Jul 13 06:49:59 PM PDT 24
Peak memory 201896 kb
Host smart-08801e73-f887-4b95-a21e-f4b16a5b200f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50881221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.50881221
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4184500452
Short name T523
Test name
Test status
Simulation time 478222741 ps
CPU time 1.66 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 06:48:58 PM PDT 24
Peak memory 201592 kb
Host smart-7cfb76f2-6bb6-46e3-a2fb-1ae6d07c0204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184500452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4184500452
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1393459517
Short name T731
Test name
Test status
Simulation time 544435877030 ps
CPU time 314.71 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 06:54:11 PM PDT 24
Peak memory 201892 kb
Host smart-ab7272cb-2def-4a7a-95a7-c78d5edeaef9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393459517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1393459517
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3960177096
Short name T556
Test name
Test status
Simulation time 500355504882 ps
CPU time 1114.49 seconds
Started Jul 13 06:48:55 PM PDT 24
Finished Jul 13 07:07:30 PM PDT 24
Peak memory 202164 kb
Host smart-ead16ab7-fa30-4e70-9356-af32b1cefd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960177096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3960177096
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3337192300
Short name T170
Test name
Test status
Simulation time 328100059793 ps
CPU time 51.39 seconds
Started Jul 13 06:48:54 PM PDT 24
Finished Jul 13 06:49:46 PM PDT 24
Peak memory 201976 kb
Host smart-3ef4368f-7333-4ffa-a104-393a416d847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337192300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3337192300
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3462653728
Short name T364
Test name
Test status
Simulation time 492888233365 ps
CPU time 300.47 seconds
Started Jul 13 06:48:54 PM PDT 24
Finished Jul 13 06:53:55 PM PDT 24
Peak memory 201896 kb
Host smart-a606ce0a-8ea6-4aa2-98a0-6d3c5e87cda1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462653728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3462653728
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.52026779
Short name T509
Test name
Test status
Simulation time 338446673476 ps
CPU time 760.07 seconds
Started Jul 13 06:48:54 PM PDT 24
Finished Jul 13 07:01:34 PM PDT 24
Peak memory 201972 kb
Host smart-02a47cc1-70f9-4453-a464-1e5be84ecb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52026779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.52026779
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4229125616
Short name T98
Test name
Test status
Simulation time 493426314716 ps
CPU time 404.67 seconds
Started Jul 13 06:48:55 PM PDT 24
Finished Jul 13 06:55:40 PM PDT 24
Peak memory 201860 kb
Host smart-13d53977-e365-4ca8-9af8-4d7e1efeb439
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229125616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4229125616
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2800763757
Short name T715
Test name
Test status
Simulation time 178122887711 ps
CPU time 251.97 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 06:53:08 PM PDT 24
Peak memory 201904 kb
Host smart-6bf36727-def8-4376-a5b8-f1212363c09d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800763757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2800763757
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2154600185
Short name T587
Test name
Test status
Simulation time 605210944335 ps
CPU time 1273.57 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 07:10:10 PM PDT 24
Peak memory 201888 kb
Host smart-9f51c70c-88b3-40cf-87bb-3e44dc0a2029
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154600185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2154600185
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.101559823
Short name T202
Test name
Test status
Simulation time 66192845129 ps
CPU time 245.25 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 06:53:02 PM PDT 24
Peak memory 202212 kb
Host smart-c09a6268-b3bc-499c-9a18-2a4cea701315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101559823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.101559823
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3026469461
Short name T348
Test name
Test status
Simulation time 33184436136 ps
CPU time 76.12 seconds
Started Jul 13 06:48:57 PM PDT 24
Finished Jul 13 06:50:13 PM PDT 24
Peak memory 201552 kb
Host smart-46898a25-5b1e-494a-bb77-c3773e4aec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026469461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3026469461
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2003740343
Short name T392
Test name
Test status
Simulation time 3843168664 ps
CPU time 9.33 seconds
Started Jul 13 06:48:53 PM PDT 24
Finished Jul 13 06:49:03 PM PDT 24
Peak memory 201708 kb
Host smart-60bab58e-171c-42cc-ab55-c65fff1016c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003740343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2003740343
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4021449019
Short name T471
Test name
Test status
Simulation time 5608700187 ps
CPU time 6.9 seconds
Started Jul 13 06:48:55 PM PDT 24
Finished Jul 13 06:49:03 PM PDT 24
Peak memory 201696 kb
Host smart-24b760b3-a22c-4c8c-8131-3552b2fbe9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021449019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4021449019
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.228044093
Short name T700
Test name
Test status
Simulation time 473845883080 ps
CPU time 308.48 seconds
Started Jul 13 06:48:56 PM PDT 24
Finished Jul 13 06:54:05 PM PDT 24
Peak memory 218620 kb
Host smart-fc6552a4-f3e8-4d0f-a5b9-6599e24ede85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228044093 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.228044093
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3685806869
Short name T607
Test name
Test status
Simulation time 376852728 ps
CPU time 1.49 seconds
Started Jul 13 06:49:02 PM PDT 24
Finished Jul 13 06:49:04 PM PDT 24
Peak memory 201648 kb
Host smart-c07fda47-61b3-456b-868b-1e0c0a47c77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685806869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3685806869
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.4108601205
Short name T323
Test name
Test status
Simulation time 543733667995 ps
CPU time 51.48 seconds
Started Jul 13 06:49:03 PM PDT 24
Finished Jul 13 06:49:55 PM PDT 24
Peak memory 201908 kb
Host smart-3c2a2078-43e8-489c-89a7-d6cf58e097e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108601205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.4108601205
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2875944359
Short name T260
Test name
Test status
Simulation time 163177775125 ps
CPU time 84.14 seconds
Started Jul 13 06:49:05 PM PDT 24
Finished Jul 13 06:50:29 PM PDT 24
Peak memory 201912 kb
Host smart-6e988d16-badb-4377-ab00-442171648672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875944359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2875944359
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3735421679
Short name T165
Test name
Test status
Simulation time 159886290280 ps
CPU time 376.49 seconds
Started Jul 13 06:49:00 PM PDT 24
Finished Jul 13 06:55:16 PM PDT 24
Peak memory 201048 kb
Host smart-aa9ebfd5-3842-4fa6-a4e3-d7706c8f703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735421679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3735421679
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.858278810
Short name T670
Test name
Test status
Simulation time 493560949343 ps
CPU time 260.73 seconds
Started Jul 13 06:48:55 PM PDT 24
Finished Jul 13 06:53:16 PM PDT 24
Peak memory 201944 kb
Host smart-99ab0cec-f86e-4652-a3ff-2b45d5ed0a9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=858278810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.858278810
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2709814468
Short name T695
Test name
Test status
Simulation time 489187079406 ps
CPU time 1117.9 seconds
Started Jul 13 06:48:54 PM PDT 24
Finished Jul 13 07:07:32 PM PDT 24
Peak memory 201972 kb
Host smart-f70f7d42-27d0-449a-929f-6c0436626c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709814468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2709814468
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.652865871
Short name T180
Test name
Test status
Simulation time 329595547836 ps
CPU time 191.05 seconds
Started Jul 13 06:48:54 PM PDT 24
Finished Jul 13 06:52:06 PM PDT 24
Peak memory 201924 kb
Host smart-471f7e99-5d1c-496a-8f9e-82457324614b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=652865871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.652865871
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3027704461
Short name T648
Test name
Test status
Simulation time 371452989196 ps
CPU time 405.13 seconds
Started Jul 13 06:48:55 PM PDT 24
Finished Jul 13 06:55:41 PM PDT 24
Peak memory 201968 kb
Host smart-b5b9410c-c2fa-4c29-9088-b343cb162ab9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027704461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3027704461
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3443229361
Short name T375
Test name
Test status
Simulation time 393813593096 ps
CPU time 968.38 seconds
Started Jul 13 06:49:05 PM PDT 24
Finished Jul 13 07:05:14 PM PDT 24
Peak memory 201876 kb
Host smart-fe088a91-8424-44ec-95c9-81abf0e8273e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443229361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3443229361
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3835575884
Short name T525
Test name
Test status
Simulation time 87421425635 ps
CPU time 274.42 seconds
Started Jul 13 06:49:03 PM PDT 24
Finished Jul 13 06:53:38 PM PDT 24
Peak memory 202260 kb
Host smart-199b8c6f-6d7b-4861-a52e-dcf932e3c91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835575884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3835575884
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2536158191
Short name T423
Test name
Test status
Simulation time 38679813161 ps
CPU time 86.4 seconds
Started Jul 13 06:49:04 PM PDT 24
Finished Jul 13 06:50:31 PM PDT 24
Peak memory 201744 kb
Host smart-b1f72ea9-df66-4362-83b9-5a75f74c32be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536158191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2536158191
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.215902046
Short name T534
Test name
Test status
Simulation time 3966196847 ps
CPU time 2.43 seconds
Started Jul 13 06:49:06 PM PDT 24
Finished Jul 13 06:49:09 PM PDT 24
Peak memory 201724 kb
Host smart-ff83b24b-eea4-423d-a18c-2d47194235f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215902046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.215902046
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2107437781
Short name T789
Test name
Test status
Simulation time 5697911865 ps
CPU time 12.7 seconds
Started Jul 13 06:49:00 PM PDT 24
Finished Jul 13 06:49:13 PM PDT 24
Peak memory 201008 kb
Host smart-5af8be94-a6a6-4067-9b96-e49504eab0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107437781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2107437781
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1246655514
Short name T635
Test name
Test status
Simulation time 327396952 ps
CPU time 0.77 seconds
Started Jul 13 06:49:13 PM PDT 24
Finished Jul 13 06:49:14 PM PDT 24
Peak memory 201656 kb
Host smart-10d6b84a-20d7-4abd-9c1a-fdda1513f9c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246655514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1246655514
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.805639637
Short name T286
Test name
Test status
Simulation time 188276371299 ps
CPU time 225.38 seconds
Started Jul 13 06:49:15 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 201760 kb
Host smart-715da642-0d55-4902-ae17-c647cfa57c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805639637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.805639637
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4115680277
Short name T152
Test name
Test status
Simulation time 325887815290 ps
CPU time 218.94 seconds
Started Jul 13 06:49:04 PM PDT 24
Finished Jul 13 06:52:44 PM PDT 24
Peak memory 201868 kb
Host smart-4d3b0ede-be7a-4283-818e-edefb3c8c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115680277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4115680277
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2102494028
Short name T495
Test name
Test status
Simulation time 331602478925 ps
CPU time 722.02 seconds
Started Jul 13 06:49:05 PM PDT 24
Finished Jul 13 07:01:07 PM PDT 24
Peak memory 201904 kb
Host smart-62ce39c1-7c3d-4bf3-a5e1-a65132c10ce4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102494028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2102494028
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.602951790
Short name T681
Test name
Test status
Simulation time 167326518577 ps
CPU time 388.74 seconds
Started Jul 13 06:49:06 PM PDT 24
Finished Jul 13 06:55:35 PM PDT 24
Peak memory 201756 kb
Host smart-39fb954a-37b9-4a2d-8515-04ce43acdc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602951790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.602951790
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3864932186
Short name T486
Test name
Test status
Simulation time 492525577770 ps
CPU time 1086.92 seconds
Started Jul 13 06:49:06 PM PDT 24
Finished Jul 13 07:07:13 PM PDT 24
Peak memory 202140 kb
Host smart-ac929c9a-dbd2-4358-a2c0-7c2c3d7965dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864932186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3864932186
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.32478003
Short name T606
Test name
Test status
Simulation time 179968049024 ps
CPU time 105.71 seconds
Started Jul 13 06:49:04 PM PDT 24
Finished Jul 13 06:50:50 PM PDT 24
Peak memory 201896 kb
Host smart-184b4b09-b740-4564-b3d6-d0213d37cfba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32478003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_w
akeup.32478003
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.305398064
Short name T743
Test name
Test status
Simulation time 410863364336 ps
CPU time 698.96 seconds
Started Jul 13 06:49:04 PM PDT 24
Finished Jul 13 07:00:44 PM PDT 24
Peak memory 201892 kb
Host smart-1ff4252c-2232-4064-9254-2d0510568dd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305398064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.305398064
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3194444810
Short name T449
Test name
Test status
Simulation time 122978850888 ps
CPU time 401.44 seconds
Started Jul 13 06:49:13 PM PDT 24
Finished Jul 13 06:55:55 PM PDT 24
Peak memory 202284 kb
Host smart-acecfb4d-4f09-4b40-9c9c-fe0f43831555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194444810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3194444810
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.604971905
Short name T431
Test name
Test status
Simulation time 32230584462 ps
CPU time 10.18 seconds
Started Jul 13 06:49:14 PM PDT 24
Finished Jul 13 06:49:24 PM PDT 24
Peak memory 201724 kb
Host smart-1cd45a34-1b39-4c78-83e2-1a3d88354e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604971905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.604971905
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3948473945
Short name T25
Test name
Test status
Simulation time 4386936005 ps
CPU time 7 seconds
Started Jul 13 06:49:15 PM PDT 24
Finished Jul 13 06:49:22 PM PDT 24
Peak memory 201720 kb
Host smart-a1f0f182-591c-4906-abb1-15fc666e7318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948473945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3948473945
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2001340489
Short name T345
Test name
Test status
Simulation time 5924952856 ps
CPU time 7.39 seconds
Started Jul 13 06:49:04 PM PDT 24
Finished Jul 13 06:49:12 PM PDT 24
Peak memory 201744 kb
Host smart-a970399b-bd17-4e63-adb0-23fe2f318f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001340489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2001340489
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1150201336
Short name T105
Test name
Test status
Simulation time 321516726532 ps
CPU time 702.87 seconds
Started Jul 13 06:49:13 PM PDT 24
Finished Jul 13 07:00:56 PM PDT 24
Peak memory 201956 kb
Host smart-40251759-76ec-4276-b51f-12e123d3863b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150201336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1150201336
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1684064678
Short name T605
Test name
Test status
Simulation time 92962063359 ps
CPU time 166.65 seconds
Started Jul 13 06:49:13 PM PDT 24
Finished Jul 13 06:52:00 PM PDT 24
Peak memory 218364 kb
Host smart-5e929f3d-b4ba-4f12-8615-80b3d8d0def1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684064678 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1684064678
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3254666786
Short name T712
Test name
Test status
Simulation time 406710485 ps
CPU time 0.79 seconds
Started Jul 13 06:49:23 PM PDT 24
Finished Jul 13 06:49:24 PM PDT 24
Peak memory 201568 kb
Host smart-5ae8dd4e-7f37-427d-b2a3-48abe71ef6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254666786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3254666786
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1555104414
Short name T250
Test name
Test status
Simulation time 371169894195 ps
CPU time 916.71 seconds
Started Jul 13 06:49:23 PM PDT 24
Finished Jul 13 07:04:40 PM PDT 24
Peak memory 201856 kb
Host smart-a006128b-7c3a-4b19-97e7-231c801815a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555104414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1555104414
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2534126635
Short name T788
Test name
Test status
Simulation time 164249354204 ps
CPU time 259.01 seconds
Started Jul 13 06:49:21 PM PDT 24
Finished Jul 13 06:53:41 PM PDT 24
Peak memory 201976 kb
Host smart-d6e7ece3-31f3-4f79-98ca-6635372751d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534126635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2534126635
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3079533066
Short name T378
Test name
Test status
Simulation time 331991522951 ps
CPU time 170.83 seconds
Started Jul 13 06:49:22 PM PDT 24
Finished Jul 13 06:52:14 PM PDT 24
Peak memory 201896 kb
Host smart-e9a78ead-348d-4e11-a084-ecb47c7304fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079533066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3079533066
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3867745783
Short name T617
Test name
Test status
Simulation time 166882486779 ps
CPU time 95.53 seconds
Started Jul 13 06:49:16 PM PDT 24
Finished Jul 13 06:50:52 PM PDT 24
Peak memory 201756 kb
Host smart-7039f652-b0b4-48b5-91ad-314433050455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867745783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3867745783
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4155594689
Short name T414
Test name
Test status
Simulation time 322785240151 ps
CPU time 374.63 seconds
Started Jul 13 06:49:13 PM PDT 24
Finished Jul 13 06:55:28 PM PDT 24
Peak memory 201880 kb
Host smart-33ac4796-e86b-4f8e-aac7-6f610701c222
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155594689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4155594689
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2884040782
Short name T739
Test name
Test status
Simulation time 555285037105 ps
CPU time 671.59 seconds
Started Jul 13 06:49:24 PM PDT 24
Finished Jul 13 07:00:37 PM PDT 24
Peak memory 201912 kb
Host smart-dd225fe2-c3a5-461d-b9ae-9a61d16f5a61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884040782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2884040782
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.185258291
Short name T242
Test name
Test status
Simulation time 194812975456 ps
CPU time 197.82 seconds
Started Jul 13 06:49:21 PM PDT 24
Finished Jul 13 06:52:39 PM PDT 24
Peak memory 201892 kb
Host smart-6d878ae9-0975-4f46-90f9-73d104444720
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185258291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.185258291
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3981130812
Short name T655
Test name
Test status
Simulation time 93925068572 ps
CPU time 262.54 seconds
Started Jul 13 06:49:24 PM PDT 24
Finished Jul 13 06:53:46 PM PDT 24
Peak memory 202244 kb
Host smart-539c9e43-2b5e-4a5e-9151-7c7cc43ef2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981130812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3981130812
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3349540717
Short name T344
Test name
Test status
Simulation time 40583217198 ps
CPU time 15.63 seconds
Started Jul 13 06:49:24 PM PDT 24
Finished Jul 13 06:49:41 PM PDT 24
Peak memory 201712 kb
Host smart-67017b06-762c-41e1-aeb2-7528acddc7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349540717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3349540717
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2840625756
Short name T522
Test name
Test status
Simulation time 5202740528 ps
CPU time 1.99 seconds
Started Jul 13 06:49:22 PM PDT 24
Finished Jul 13 06:49:25 PM PDT 24
Peak memory 201728 kb
Host smart-504dcee6-9c76-4307-baf3-b0102a38a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840625756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2840625756
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3943166836
Short name T450
Test name
Test status
Simulation time 6156110078 ps
CPU time 13.74 seconds
Started Jul 13 06:49:15 PM PDT 24
Finished Jul 13 06:49:29 PM PDT 24
Peak memory 201696 kb
Host smart-319a4f11-16ab-405e-a42d-83240ff9cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943166836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3943166836
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1378023596
Short name T184
Test name
Test status
Simulation time 416991187577 ps
CPU time 538.08 seconds
Started Jul 13 06:49:27 PM PDT 24
Finished Jul 13 06:58:25 PM PDT 24
Peak memory 202180 kb
Host smart-186c5e99-8c76-4478-802f-3774e8daa213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378023596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1378023596
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.130003893
Short name T34
Test name
Test status
Simulation time 40311319322 ps
CPU time 46.8 seconds
Started Jul 13 06:49:22 PM PDT 24
Finished Jul 13 06:50:10 PM PDT 24
Peak memory 202096 kb
Host smart-8c76ab9d-fd9b-4560-96ec-880fd754014c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130003893 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.130003893
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3047720669
Short name T438
Test name
Test status
Simulation time 490973723 ps
CPU time 0.94 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 06:49:34 PM PDT 24
Peak memory 201664 kb
Host smart-4eb97528-dbde-484e-818d-e058c5be8307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047720669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3047720669
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2952895414
Short name T316
Test name
Test status
Simulation time 346237721292 ps
CPU time 210.03 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 06:53:03 PM PDT 24
Peak memory 201808 kb
Host smart-971d6dc1-15c0-4d62-bfac-0c6b47c0b95e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952895414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2952895414
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2757755484
Short name T311
Test name
Test status
Simulation time 190400967290 ps
CPU time 422.53 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 06:56:35 PM PDT 24
Peak memory 201904 kb
Host smart-883ed0af-f293-4d73-acfb-1fa2a2462535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757755484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2757755484
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1822948009
Short name T772
Test name
Test status
Simulation time 485257070049 ps
CPU time 284.97 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 06:54:17 PM PDT 24
Peak memory 201928 kb
Host smart-11e2ed07-1443-4e46-b3c7-7ac26ce3c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822948009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1822948009
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1429880376
Short name T441
Test name
Test status
Simulation time 330441556567 ps
CPU time 210.39 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 06:53:03 PM PDT 24
Peak memory 202068 kb
Host smart-aaeefe99-49cf-4398-aa78-1958bb560a2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429880376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1429880376
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3008775447
Short name T255
Test name
Test status
Simulation time 483694145903 ps
CPU time 1044.29 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 07:06:56 PM PDT 24
Peak memory 201968 kb
Host smart-b5f784d9-3baf-4061-bbcb-e9a11a4adcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008775447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3008775447
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.886298882
Short name T160
Test name
Test status
Simulation time 484701286439 ps
CPU time 452.65 seconds
Started Jul 13 06:49:31 PM PDT 24
Finished Jul 13 06:57:05 PM PDT 24
Peak memory 201912 kb
Host smart-38842f1b-25d3-4522-9ef4-ac3489dda3c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=886298882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.886298882
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3332706303
Short name T139
Test name
Test status
Simulation time 627381648570 ps
CPU time 187.99 seconds
Started Jul 13 06:49:31 PM PDT 24
Finished Jul 13 06:52:40 PM PDT 24
Peak memory 201968 kb
Host smart-3aadfdd3-9969-4f0a-a16b-0ad83288e7e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332706303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3332706303
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1609080372
Short name T241
Test name
Test status
Simulation time 205633607007 ps
CPU time 440.88 seconds
Started Jul 13 06:49:31 PM PDT 24
Finished Jul 13 06:56:53 PM PDT 24
Peak memory 201932 kb
Host smart-67c78ecb-d363-4578-80fc-2b186324285b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609080372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1609080372
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2917617375
Short name T341
Test name
Test status
Simulation time 105492658465 ps
CPU time 531.54 seconds
Started Jul 13 06:49:31 PM PDT 24
Finished Jul 13 06:58:23 PM PDT 24
Peak memory 202228 kb
Host smart-63835c33-bda2-4ad4-9a99-3af6479a89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917617375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2917617375
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.73377764
Short name T596
Test name
Test status
Simulation time 35236912541 ps
CPU time 58.67 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 06:50:31 PM PDT 24
Peak memory 201712 kb
Host smart-d35f7ab8-1129-473d-b9b2-34fbd43b567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73377764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.73377764
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3487154226
Short name T610
Test name
Test status
Simulation time 4894511294 ps
CPU time 12.19 seconds
Started Jul 13 06:49:31 PM PDT 24
Finished Jul 13 06:49:44 PM PDT 24
Peak memory 201700 kb
Host smart-70bdae5b-a970-4e29-b888-e83e642139db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487154226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3487154226
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.947019993
Short name T748
Test name
Test status
Simulation time 5572464816 ps
CPU time 13.19 seconds
Started Jul 13 06:49:23 PM PDT 24
Finished Jul 13 06:49:36 PM PDT 24
Peak memory 201720 kb
Host smart-22f1ec75-3cf9-46b9-9323-745d076e7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947019993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.947019993
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3062081298
Short name T532
Test name
Test status
Simulation time 514507738408 ps
CPU time 566 seconds
Started Jul 13 06:49:30 PM PDT 24
Finished Jul 13 06:58:56 PM PDT 24
Peak memory 201952 kb
Host smart-89ed68b8-7f30-4438-bbb1-9cb57d9bcdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062081298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3062081298
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4134466448
Short name T37
Test name
Test status
Simulation time 64882650004 ps
CPU time 148.44 seconds
Started Jul 13 06:49:30 PM PDT 24
Finished Jul 13 06:51:59 PM PDT 24
Peak memory 218652 kb
Host smart-41cad60f-d6c8-4d4b-824b-6a3038b9dc8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134466448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4134466448
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2767135661
Short name T728
Test name
Test status
Simulation time 349898853 ps
CPU time 0.88 seconds
Started Jul 13 06:49:50 PM PDT 24
Finished Jul 13 06:49:51 PM PDT 24
Peak memory 201648 kb
Host smart-193b8bd2-3fdd-4d8a-94d3-f1824d09bf44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767135661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2767135661
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1750896586
Short name T298
Test name
Test status
Simulation time 495890401882 ps
CPU time 1123.16 seconds
Started Jul 13 06:49:39 PM PDT 24
Finished Jul 13 07:08:22 PM PDT 24
Peak memory 201928 kb
Host smart-6c3bb01f-2b33-412a-9673-608983714f58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750896586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1750896586
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.314533555
Short name T309
Test name
Test status
Simulation time 491809957086 ps
CPU time 571.36 seconds
Started Jul 13 06:49:41 PM PDT 24
Finished Jul 13 06:59:13 PM PDT 24
Peak memory 201900 kb
Host smart-25921eb3-7b29-4bb1-bc8e-c177b19927b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314533555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.314533555
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2460258941
Short name T263
Test name
Test status
Simulation time 485327988226 ps
CPU time 302.46 seconds
Started Jul 13 06:49:39 PM PDT 24
Finished Jul 13 06:54:42 PM PDT 24
Peak memory 201844 kb
Host smart-19085a36-5e38-4f9b-934b-2702bcc9a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460258941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2460258941
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1181563369
Short name T30
Test name
Test status
Simulation time 330707539079 ps
CPU time 777.86 seconds
Started Jul 13 06:49:39 PM PDT 24
Finished Jul 13 07:02:37 PM PDT 24
Peak memory 201892 kb
Host smart-ab7b181e-e2bb-4826-9794-8dca55a71e88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181563369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1181563369
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3586832205
Short name T448
Test name
Test status
Simulation time 161750452802 ps
CPU time 98.12 seconds
Started Jul 13 06:49:41 PM PDT 24
Finished Jul 13 06:51:20 PM PDT 24
Peak memory 202000 kb
Host smart-3e82e674-8e48-40f6-85ea-0d37cd8e7902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586832205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3586832205
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2218903718
Short name T442
Test name
Test status
Simulation time 487819268900 ps
CPU time 417.49 seconds
Started Jul 13 06:49:39 PM PDT 24
Finished Jul 13 06:56:37 PM PDT 24
Peak memory 201936 kb
Host smart-95fa30c6-29f2-4531-88e9-ee2a81a34f99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218903718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2218903718
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4280174442
Short name T589
Test name
Test status
Simulation time 179311622043 ps
CPU time 120.68 seconds
Started Jul 13 06:49:38 PM PDT 24
Finished Jul 13 06:51:39 PM PDT 24
Peak memory 201892 kb
Host smart-d0551cc1-e3ce-4d56-9a52-f4033f25ddd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280174442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4280174442
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3347391816
Short name T183
Test name
Test status
Simulation time 587185525411 ps
CPU time 1343.13 seconds
Started Jul 13 06:49:39 PM PDT 24
Finished Jul 13 07:12:03 PM PDT 24
Peak memory 201884 kb
Host smart-6f39cc3d-dad8-46c0-a859-58875ea65048
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347391816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3347391816
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3271285821
Short name T485
Test name
Test status
Simulation time 30687944607 ps
CPU time 25.17 seconds
Started Jul 13 06:49:39 PM PDT 24
Finished Jul 13 06:50:05 PM PDT 24
Peak memory 201656 kb
Host smart-1360af50-02e4-4d89-8479-7874728c49d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271285821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3271285821
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.193731662
Short name T544
Test name
Test status
Simulation time 3770384501 ps
CPU time 8.3 seconds
Started Jul 13 06:49:41 PM PDT 24
Finished Jul 13 06:49:50 PM PDT 24
Peak memory 201704 kb
Host smart-9cb6504a-94bf-46ef-a944-d337cdbef025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193731662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.193731662
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2614028325
Short name T696
Test name
Test status
Simulation time 5945713074 ps
CPU time 13.24 seconds
Started Jul 13 06:49:32 PM PDT 24
Finished Jul 13 06:49:46 PM PDT 24
Peak memory 201616 kb
Host smart-d7725564-585c-4d63-b608-fa2be9d5cec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614028325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2614028325
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.300659788
Short name T223
Test name
Test status
Simulation time 586605285058 ps
CPU time 1129.4 seconds
Started Jul 13 06:49:41 PM PDT 24
Finished Jul 13 07:08:31 PM PDT 24
Peak memory 201944 kb
Host smart-d2fe7928-29a1-42fd-942d-501ac91b4283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300659788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
300659788
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4213321696
Short name T584
Test name
Test status
Simulation time 245063283002 ps
CPU time 227.89 seconds
Started Jul 13 06:49:40 PM PDT 24
Finished Jul 13 06:53:28 PM PDT 24
Peak memory 202516 kb
Host smart-91db70a1-890c-423c-895e-3cd3e02104b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213321696 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4213321696
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3655702956
Short name T537
Test name
Test status
Simulation time 471963034 ps
CPU time 1.15 seconds
Started Jul 13 06:49:57 PM PDT 24
Finished Jul 13 06:49:59 PM PDT 24
Peak memory 201676 kb
Host smart-f492ed01-31f9-48c6-9cd6-465fa4b4d073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655702956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3655702956
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1444173281
Short name T210
Test name
Test status
Simulation time 553939963161 ps
CPU time 355.49 seconds
Started Jul 13 06:49:48 PM PDT 24
Finished Jul 13 06:55:44 PM PDT 24
Peak memory 202008 kb
Host smart-860185ca-c3bc-4d16-839a-c208df987b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444173281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1444173281
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.981366727
Short name T558
Test name
Test status
Simulation time 490891601302 ps
CPU time 568.28 seconds
Started Jul 13 06:49:49 PM PDT 24
Finished Jul 13 06:59:18 PM PDT 24
Peak memory 201868 kb
Host smart-aa94871d-b732-4ddd-a425-2957c68a35ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981366727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.981366727
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1869348691
Short name T482
Test name
Test status
Simulation time 161681050190 ps
CPU time 180.99 seconds
Started Jul 13 06:49:48 PM PDT 24
Finished Jul 13 06:52:50 PM PDT 24
Peak memory 201876 kb
Host smart-8a4602f6-6aad-461f-a4cf-cd874636c551
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869348691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1869348691
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3198251648
Short name T141
Test name
Test status
Simulation time 495701628737 ps
CPU time 292.53 seconds
Started Jul 13 06:49:50 PM PDT 24
Finished Jul 13 06:54:43 PM PDT 24
Peak memory 201988 kb
Host smart-167ab6c3-5570-4093-9b65-e985cc108a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198251648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3198251648
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1123335521
Short name T168
Test name
Test status
Simulation time 501562945432 ps
CPU time 290.68 seconds
Started Jul 13 06:49:50 PM PDT 24
Finished Jul 13 06:54:41 PM PDT 24
Peak memory 201892 kb
Host smart-8116b355-499c-451f-9511-8cd684dff309
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123335521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1123335521
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1048816504
Short name T49
Test name
Test status
Simulation time 168561322005 ps
CPU time 91.73 seconds
Started Jul 13 06:49:49 PM PDT 24
Finished Jul 13 06:51:21 PM PDT 24
Peak memory 201992 kb
Host smart-e86ea140-ced4-4862-9052-b27b8a8602fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048816504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1048816504
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1587314436
Short name T673
Test name
Test status
Simulation time 403263987178 ps
CPU time 449.87 seconds
Started Jul 13 06:49:51 PM PDT 24
Finished Jul 13 06:57:21 PM PDT 24
Peak memory 201940 kb
Host smart-df408d19-6175-41fa-a2c5-2e098ffcdc6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587314436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1587314436
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3906521366
Short name T2
Test name
Test status
Simulation time 107004815963 ps
CPU time 398.11 seconds
Started Jul 13 06:49:56 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 202140 kb
Host smart-5c6bbdb7-7ed8-4113-92f9-fdd2589e0166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906521366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3906521366
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.484664944
Short name T798
Test name
Test status
Simulation time 42008732139 ps
CPU time 91.1 seconds
Started Jul 13 06:49:57 PM PDT 24
Finished Jul 13 06:51:28 PM PDT 24
Peak memory 201752 kb
Host smart-0f9b2fcf-b07d-4571-8cc4-8a428b5673d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484664944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.484664944
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.777952688
Short name T559
Test name
Test status
Simulation time 5124731219 ps
CPU time 1.43 seconds
Started Jul 13 06:52:38 PM PDT 24
Finished Jul 13 06:52:39 PM PDT 24
Peak memory 201876 kb
Host smart-ddb942e2-bbf9-4011-b7a6-8aa81cf8d5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777952688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.777952688
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3590000559
Short name T11
Test name
Test status
Simulation time 5569543517 ps
CPU time 3.86 seconds
Started Jul 13 06:49:50 PM PDT 24
Finished Jul 13 06:49:54 PM PDT 24
Peak memory 201724 kb
Host smart-60c8f3fc-390d-4161-9f62-46b894f94be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590000559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3590000559
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3021481956
Short name T484
Test name
Test status
Simulation time 197025281627 ps
CPU time 360.22 seconds
Started Jul 13 06:49:57 PM PDT 24
Finished Jul 13 06:55:57 PM PDT 24
Peak memory 201908 kb
Host smart-38da1db0-7cfe-4046-a99c-ee2ffe2764e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021481956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3021481956
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.795541645
Short name T671
Test name
Test status
Simulation time 62593876420 ps
CPU time 144.92 seconds
Started Jul 13 06:49:58 PM PDT 24
Finished Jul 13 06:52:23 PM PDT 24
Peak memory 210240 kb
Host smart-3d8d08e5-f2fd-4834-ae40-6eaced4e13d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795541645 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.795541645
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.408146021
Short name T657
Test name
Test status
Simulation time 323591678 ps
CPU time 0.86 seconds
Started Jul 13 06:46:49 PM PDT 24
Finished Jul 13 06:46:51 PM PDT 24
Peak memory 201656 kb
Host smart-eebc8304-9998-4207-a1b6-fb6b30856ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408146021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.408146021
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1047164572
Short name T293
Test name
Test status
Simulation time 159423086494 ps
CPU time 218.25 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:50:37 PM PDT 24
Peak memory 201948 kb
Host smart-fd60b2ed-9feb-4db6-9ff1-f66d4a0695ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047164572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1047164572
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.4251556820
Short name T637
Test name
Test status
Simulation time 508543330181 ps
CPU time 775.37 seconds
Started Jul 13 06:46:50 PM PDT 24
Finished Jul 13 06:59:46 PM PDT 24
Peak memory 201912 kb
Host smart-43ea76bc-4679-4b51-b11f-f8b773fd7990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251556820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4251556820
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2830863360
Short name T270
Test name
Test status
Simulation time 162845884628 ps
CPU time 158.03 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:49:30 PM PDT 24
Peak memory 201868 kb
Host smart-b51d3024-5fb8-44ad-934f-8280a806fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830863360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2830863360
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2443289620
Short name T750
Test name
Test status
Simulation time 162169203173 ps
CPU time 98.68 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:48:30 PM PDT 24
Peak memory 201900 kb
Host smart-7556d1ae-482a-4c9f-ade4-7f7397848288
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443289620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2443289620
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3592876563
Short name T783
Test name
Test status
Simulation time 486125766853 ps
CPU time 255.11 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:51:02 PM PDT 24
Peak memory 201900 kb
Host smart-26db0991-b033-43d5-96f3-c05c83763407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592876563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3592876563
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.474425454
Short name T740
Test name
Test status
Simulation time 330146799399 ps
CPU time 741.48 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:59:20 PM PDT 24
Peak memory 201784 kb
Host smart-df4e109d-615c-4682-8d32-e703fa1b22f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=474425454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.474425454
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2491149057
Short name T245
Test name
Test status
Simulation time 179618940289 ps
CPU time 112.5 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:48:44 PM PDT 24
Peak memory 201928 kb
Host smart-0b7242b2-1874-407f-a694-2ac3a9a87e58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491149057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2491149057
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3474745765
Short name T494
Test name
Test status
Simulation time 400535434669 ps
CPU time 965.65 seconds
Started Jul 13 06:46:53 PM PDT 24
Finished Jul 13 07:02:59 PM PDT 24
Peak memory 201868 kb
Host smart-d2900a7e-57f7-43fb-ad71-2b4c3fc3bc64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474745765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3474745765
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3422952644
Short name T205
Test name
Test status
Simulation time 130794076833 ps
CPU time 601.78 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:56:54 PM PDT 24
Peak memory 202316 kb
Host smart-16955f4d-21e4-4228-ab24-ef5f42f9f3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422952644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3422952644
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2148525041
Short name T360
Test name
Test status
Simulation time 47470770229 ps
CPU time 113.16 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:48:40 PM PDT 24
Peak memory 201708 kb
Host smart-d35e4a81-65f8-4547-a474-8d63496ab520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148525041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2148525041
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2970011907
Short name T602
Test name
Test status
Simulation time 3883506571 ps
CPU time 9.01 seconds
Started Jul 13 06:47:03 PM PDT 24
Finished Jul 13 06:47:12 PM PDT 24
Peak memory 201724 kb
Host smart-eda72b4c-bdfe-433a-808c-f2bec5577c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970011907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2970011907
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.287249987
Short name T390
Test name
Test status
Simulation time 5903533298 ps
CPU time 4.67 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:46:54 PM PDT 24
Peak memory 201724 kb
Host smart-6ef29237-43d2-4df3-9ebe-dc7c61a8c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287249987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.287249987
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3597555170
Short name T305
Test name
Test status
Simulation time 370188761221 ps
CPU time 243.85 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:51:00 PM PDT 24
Peak memory 201980 kb
Host smart-371ddca5-563c-4c6c-ac6e-5a1769fb94fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597555170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3597555170
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.328001235
Short name T656
Test name
Test status
Simulation time 61006419161 ps
CPU time 134.71 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:49:04 PM PDT 24
Peak memory 210572 kb
Host smart-26c70956-00a8-4fc8-bfb0-85acda9abc2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328001235 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.328001235
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3000851959
Short name T583
Test name
Test status
Simulation time 456805557 ps
CPU time 1.64 seconds
Started Jul 13 06:50:05 PM PDT 24
Finished Jul 13 06:50:07 PM PDT 24
Peak memory 201632 kb
Host smart-56754c93-128a-432a-8595-c365fe036159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000851959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3000851959
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2306817286
Short name T320
Test name
Test status
Simulation time 226511403970 ps
CPU time 496.87 seconds
Started Jul 13 06:50:03 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 201888 kb
Host smart-6549d269-9c99-4557-a4f8-ced0c7240096
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306817286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2306817286
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3081294008
Short name T272
Test name
Test status
Simulation time 173247488177 ps
CPU time 392.54 seconds
Started Jul 13 06:50:04 PM PDT 24
Finished Jul 13 06:56:38 PM PDT 24
Peak memory 201996 kb
Host smart-29df88a6-00ac-4f4f-9cd1-5c6316563f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081294008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3081294008
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3288034168
Short name T277
Test name
Test status
Simulation time 486345343466 ps
CPU time 639.16 seconds
Started Jul 13 06:49:56 PM PDT 24
Finished Jul 13 07:00:35 PM PDT 24
Peak memory 201888 kb
Host smart-32b323e7-498b-43e1-ada5-e0c1848cdf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288034168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3288034168
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2572667272
Short name T401
Test name
Test status
Simulation time 162274523797 ps
CPU time 110.42 seconds
Started Jul 13 06:49:55 PM PDT 24
Finished Jul 13 06:51:46 PM PDT 24
Peak memory 201884 kb
Host smart-9766c7c8-6616-49bd-b517-475e8ccfc18a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572667272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2572667272
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2508540348
Short name T214
Test name
Test status
Simulation time 499417821884 ps
CPU time 1037.84 seconds
Started Jul 13 06:49:57 PM PDT 24
Finished Jul 13 07:07:16 PM PDT 24
Peak memory 201888 kb
Host smart-bed5512b-08c3-43c3-8a8d-b8d79b223480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508540348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2508540348
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3191565260
Short name T614
Test name
Test status
Simulation time 330458662963 ps
CPU time 182.5 seconds
Started Jul 13 06:49:58 PM PDT 24
Finished Jul 13 06:53:01 PM PDT 24
Peak memory 201904 kb
Host smart-cc9df64a-cd93-4105-b851-b26bf0f65cf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191565260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3191565260
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2598225592
Short name T173
Test name
Test status
Simulation time 611184673618 ps
CPU time 320.19 seconds
Started Jul 13 06:49:55 PM PDT 24
Finished Jul 13 06:55:16 PM PDT 24
Peak memory 201904 kb
Host smart-000c7238-8a27-4fdb-a971-885e6de073e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598225592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2598225592
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.438412046
Short name T474
Test name
Test status
Simulation time 104233139735 ps
CPU time 527.87 seconds
Started Jul 13 06:50:05 PM PDT 24
Finished Jul 13 06:58:53 PM PDT 24
Peak memory 202272 kb
Host smart-0b4441c5-29cf-40d9-b35e-5e33bb09ea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438412046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.438412046
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1863877213
Short name T496
Test name
Test status
Simulation time 32516311828 ps
CPU time 9.69 seconds
Started Jul 13 06:50:03 PM PDT 24
Finished Jul 13 06:50:13 PM PDT 24
Peak memory 201720 kb
Host smart-426075a8-ed14-4321-9a26-8279ce37ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863877213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1863877213
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1241488799
Short name T354
Test name
Test status
Simulation time 5105662687 ps
CPU time 10.94 seconds
Started Jul 13 06:50:05 PM PDT 24
Finished Jul 13 06:50:16 PM PDT 24
Peak memory 201704 kb
Host smart-c0e00bb8-fdde-4cd9-aa5e-9f6c7cb5fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241488799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1241488799
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2721946691
Short name T454
Test name
Test status
Simulation time 5730920943 ps
CPU time 4.13 seconds
Started Jul 13 06:49:58 PM PDT 24
Finished Jul 13 06:50:03 PM PDT 24
Peak memory 201876 kb
Host smart-598e9757-f691-4dca-97ee-dd6d0a6b8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721946691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2721946691
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1509444141
Short name T17
Test name
Test status
Simulation time 97757796646 ps
CPU time 40.38 seconds
Started Jul 13 06:50:04 PM PDT 24
Finished Jul 13 06:50:45 PM PDT 24
Peak memory 202092 kb
Host smart-d50a4d72-adce-48d6-a0de-66e124867b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509444141 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1509444141
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3322105440
Short name T389
Test name
Test status
Simulation time 528598135 ps
CPU time 1.85 seconds
Started Jul 13 06:50:23 PM PDT 24
Finished Jul 13 06:50:25 PM PDT 24
Peak memory 201648 kb
Host smart-e3321452-dc26-46f6-82dd-cf724131e1a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322105440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3322105440
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1195960728
Short name T234
Test name
Test status
Simulation time 399952884064 ps
CPU time 133.67 seconds
Started Jul 13 06:50:14 PM PDT 24
Finished Jul 13 06:52:28 PM PDT 24
Peak memory 201888 kb
Host smart-480bdffe-fff2-4bd7-b743-57c457975aa3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195960728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1195960728
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2892217997
Short name T230
Test name
Test status
Simulation time 329199374026 ps
CPU time 756.82 seconds
Started Jul 13 06:50:15 PM PDT 24
Finished Jul 13 07:02:52 PM PDT 24
Peak memory 201820 kb
Host smart-efdfbeed-838e-4a35-8b9d-a243b120ed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892217997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2892217997
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.686132249
Short name T548
Test name
Test status
Simulation time 501168990982 ps
CPU time 295 seconds
Started Jul 13 06:50:04 PM PDT 24
Finished Jul 13 06:55:00 PM PDT 24
Peak memory 201896 kb
Host smart-15b689f3-9576-4230-bd55-b1e3244c6feb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=686132249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.686132249
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.966356059
Short name T266
Test name
Test status
Simulation time 320987665227 ps
CPU time 454.34 seconds
Started Jul 13 06:50:07 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 201908 kb
Host smart-74df8404-5dd6-47e7-a06f-d3e275c02a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966356059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.966356059
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2124057878
Short name T420
Test name
Test status
Simulation time 171501588738 ps
CPU time 357.31 seconds
Started Jul 13 06:50:03 PM PDT 24
Finished Jul 13 06:56:00 PM PDT 24
Peak memory 201844 kb
Host smart-541d6d5e-4397-480e-892a-2db9ac5fd603
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124057878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2124057878
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1134322306
Short name T603
Test name
Test status
Simulation time 196275478834 ps
CPU time 107.09 seconds
Started Jul 13 06:50:04 PM PDT 24
Finished Jul 13 06:51:51 PM PDT 24
Peak memory 201912 kb
Host smart-363a48b0-7e37-479d-9256-a12ef3f18218
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134322306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1134322306
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3260467778
Short name T79
Test name
Test status
Simulation time 203022982056 ps
CPU time 259.92 seconds
Started Jul 13 06:50:16 PM PDT 24
Finished Jul 13 06:54:36 PM PDT 24
Peak memory 201796 kb
Host smart-448a26dc-17b8-4b77-81c1-bfe06ea977c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260467778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3260467778
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.805116356
Short name T508
Test name
Test status
Simulation time 86877710649 ps
CPU time 301.27 seconds
Started Jul 13 06:50:14 PM PDT 24
Finished Jul 13 06:55:16 PM PDT 24
Peak memory 202292 kb
Host smart-82294d58-d9ea-4928-ab53-30f55ef64020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805116356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.805116356
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1081009398
Short name T777
Test name
Test status
Simulation time 46809663673 ps
CPU time 99.18 seconds
Started Jul 13 06:50:14 PM PDT 24
Finished Jul 13 06:51:54 PM PDT 24
Peak memory 201652 kb
Host smart-5b6e9b3d-f1d3-455e-b205-5f94042a653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081009398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1081009398
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2160770607
Short name T506
Test name
Test status
Simulation time 5046770164 ps
CPU time 12.33 seconds
Started Jul 13 06:50:15 PM PDT 24
Finished Jul 13 06:50:28 PM PDT 24
Peak memory 201624 kb
Host smart-66f683e5-2ffa-4009-8bb5-dd99109c7aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160770607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2160770607
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.466921932
Short name T361
Test name
Test status
Simulation time 5722173714 ps
CPU time 14.14 seconds
Started Jul 13 06:50:05 PM PDT 24
Finished Jul 13 06:50:19 PM PDT 24
Peak memory 201680 kb
Host smart-e03edc0f-5c9d-4a15-a426-f69cabec472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466921932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.466921932
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3448796107
Short name T707
Test name
Test status
Simulation time 378486095403 ps
CPU time 679.46 seconds
Started Jul 13 06:50:13 PM PDT 24
Finished Jul 13 07:01:33 PM PDT 24
Peak memory 201984 kb
Host smart-35cac724-ed54-4016-bac7-56dd9d16729a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448796107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3448796107
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3379338404
Short name T24
Test name
Test status
Simulation time 342919337643 ps
CPU time 209.08 seconds
Started Jul 13 06:50:13 PM PDT 24
Finished Jul 13 06:53:43 PM PDT 24
Peak memory 210596 kb
Host smart-028dc956-784b-4c8c-a0d2-9ad0146c2e19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379338404 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3379338404
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3897501860
Short name T465
Test name
Test status
Simulation time 382199712 ps
CPU time 0.87 seconds
Started Jul 13 06:50:32 PM PDT 24
Finished Jul 13 06:50:33 PM PDT 24
Peak memory 201644 kb
Host smart-7fc56eb3-225d-4164-895c-53ca33bd993c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897501860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3897501860
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3160480233
Short name T169
Test name
Test status
Simulation time 181074203311 ps
CPU time 43.49 seconds
Started Jul 13 06:50:23 PM PDT 24
Finished Jul 13 06:51:06 PM PDT 24
Peak memory 201968 kb
Host smart-81713b43-fdec-49c3-beb3-70806ca7c985
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160480233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3160480233
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1758945717
Short name T540
Test name
Test status
Simulation time 167067603969 ps
CPU time 100.44 seconds
Started Jul 13 06:50:30 PM PDT 24
Finished Jul 13 06:52:11 PM PDT 24
Peak memory 201948 kb
Host smart-01532dcd-40fb-4363-a15e-9114bd693169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758945717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1758945717
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.741739525
Short name T164
Test name
Test status
Simulation time 493047582508 ps
CPU time 1142.3 seconds
Started Jul 13 06:50:23 PM PDT 24
Finished Jul 13 07:09:26 PM PDT 24
Peak memory 201892 kb
Host smart-2c174500-9c49-4ffc-972f-8d4bbc067c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741739525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.741739525
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2003757507
Short name T460
Test name
Test status
Simulation time 324970734304 ps
CPU time 756.28 seconds
Started Jul 13 06:50:23 PM PDT 24
Finished Jul 13 07:02:59 PM PDT 24
Peak memory 201940 kb
Host smart-83404a20-1161-4d1c-bfd0-2d193ea585f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003757507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2003757507
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2109466721
Short name T723
Test name
Test status
Simulation time 328645260627 ps
CPU time 773.11 seconds
Started Jul 13 06:50:23 PM PDT 24
Finished Jul 13 07:03:17 PM PDT 24
Peak memory 201952 kb
Host smart-8838b658-5d0b-426c-8cfc-ed800b2a5470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109466721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2109466721
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3237612059
Short name T182
Test name
Test status
Simulation time 328541033855 ps
CPU time 380.6 seconds
Started Jul 13 06:50:23 PM PDT 24
Finished Jul 13 06:56:43 PM PDT 24
Peak memory 201900 kb
Host smart-04956b2a-e4c5-4185-ad4a-9f8751d27054
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237612059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3237612059
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1541256191
Short name T322
Test name
Test status
Simulation time 591341125085 ps
CPU time 362.04 seconds
Started Jul 13 06:50:23 PM PDT 24
Finished Jul 13 06:56:26 PM PDT 24
Peak memory 201900 kb
Host smart-c8f2f0f0-14c4-49a1-be68-3c27c8add112
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541256191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1541256191
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.313363528
Short name T704
Test name
Test status
Simulation time 606347342356 ps
CPU time 1346.36 seconds
Started Jul 13 06:50:24 PM PDT 24
Finished Jul 13 07:12:51 PM PDT 24
Peak memory 201788 kb
Host smart-fd4b6f54-aa86-4a68-90cb-5c1379e1c5d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313363528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.313363528
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2296968929
Short name T608
Test name
Test status
Simulation time 80495973073 ps
CPU time 346.09 seconds
Started Jul 13 06:50:30 PM PDT 24
Finished Jul 13 06:56:17 PM PDT 24
Peak memory 202292 kb
Host smart-305ed6c2-e942-4a2e-b177-fbb76e808b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296968929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2296968929
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.4040728375
Short name T684
Test name
Test status
Simulation time 30541964789 ps
CPU time 36.36 seconds
Started Jul 13 06:50:33 PM PDT 24
Finished Jul 13 06:51:09 PM PDT 24
Peak memory 201980 kb
Host smart-4ab310a7-0080-43e8-8a36-a5e84f385f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040728375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.4040728375
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4285772495
Short name T729
Test name
Test status
Simulation time 3033496555 ps
CPU time 6.9 seconds
Started Jul 13 06:50:32 PM PDT 24
Finished Jul 13 06:50:39 PM PDT 24
Peak memory 201724 kb
Host smart-6ed72406-1bcc-4030-b3b1-47ee5dfd64de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285772495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4285772495
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1077543866
Short name T443
Test name
Test status
Simulation time 5825472002 ps
CPU time 2.21 seconds
Started Jul 13 06:50:24 PM PDT 24
Finished Jul 13 06:50:26 PM PDT 24
Peak memory 201728 kb
Host smart-56d59a34-4198-4dd6-8121-2e7f6a396a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077543866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1077543866
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.595940820
Short name T340
Test name
Test status
Simulation time 446044317772 ps
CPU time 572.81 seconds
Started Jul 13 06:50:30 PM PDT 24
Finished Jul 13 07:00:03 PM PDT 24
Peak memory 210400 kb
Host smart-bffee66a-efa3-4077-bcff-3398d6be2c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595940820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
595940820
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.734679830
Short name T666
Test name
Test status
Simulation time 429721006 ps
CPU time 1.02 seconds
Started Jul 13 06:50:41 PM PDT 24
Finished Jul 13 06:50:43 PM PDT 24
Peak memory 201664 kb
Host smart-d71464fb-45a0-4976-b132-5803a351f6e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734679830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.734679830
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2534219359
Short name T627
Test name
Test status
Simulation time 345146189245 ps
CPU time 96.22 seconds
Started Jul 13 06:50:38 PM PDT 24
Finished Jul 13 06:52:14 PM PDT 24
Peak memory 202004 kb
Host smart-7f164bf9-1dd4-4652-b04d-05ba2ed924bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534219359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2534219359
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2427689076
Short name T33
Test name
Test status
Simulation time 170435635111 ps
CPU time 419 seconds
Started Jul 13 06:50:39 PM PDT 24
Finished Jul 13 06:57:38 PM PDT 24
Peak memory 201912 kb
Host smart-12325849-0d63-4c6c-ae30-2326f214a270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427689076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2427689076
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.801421033
Short name T730
Test name
Test status
Simulation time 159062056258 ps
CPU time 97.08 seconds
Started Jul 13 06:50:30 PM PDT 24
Finished Jul 13 06:52:08 PM PDT 24
Peak memory 201972 kb
Host smart-2603b145-be93-4b9f-a08c-0146d092b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801421033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.801421033
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1457707331
Short name T552
Test name
Test status
Simulation time 327170156345 ps
CPU time 85.16 seconds
Started Jul 13 06:50:32 PM PDT 24
Finished Jul 13 06:51:57 PM PDT 24
Peak memory 201868 kb
Host smart-928241da-ab98-438f-9cef-c7b7495b05a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457707331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1457707331
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.97818401
Short name T794
Test name
Test status
Simulation time 162186568118 ps
CPU time 58.94 seconds
Started Jul 13 06:50:31 PM PDT 24
Finished Jul 13 06:51:30 PM PDT 24
Peak memory 201936 kb
Host smart-dc069c2f-6017-44dd-a79e-52b5c767349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97818401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.97818401
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.953714054
Short name T346
Test name
Test status
Simulation time 336402792993 ps
CPU time 195.79 seconds
Started Jul 13 06:50:30 PM PDT 24
Finished Jul 13 06:53:46 PM PDT 24
Peak memory 201904 kb
Host smart-e10a659c-a54b-412d-92de-b30769141de1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=953714054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.953714054
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2985918473
Short name T308
Test name
Test status
Simulation time 181512720156 ps
CPU time 86.32 seconds
Started Jul 13 06:50:29 PM PDT 24
Finished Jul 13 06:51:56 PM PDT 24
Peak memory 201904 kb
Host smart-275c96aa-f710-4a96-b90e-b82b4103bb33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985918473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2985918473
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2391125825
Short name T792
Test name
Test status
Simulation time 194971621233 ps
CPU time 440.45 seconds
Started Jul 13 06:50:31 PM PDT 24
Finished Jul 13 06:57:53 PM PDT 24
Peak memory 201920 kb
Host smart-e13e4579-bb33-43b4-b6df-d10c5f03da52
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391125825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2391125825
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3812270324
Short name T339
Test name
Test status
Simulation time 127967801773 ps
CPU time 530.21 seconds
Started Jul 13 06:50:38 PM PDT 24
Finished Jul 13 06:59:28 PM PDT 24
Peak memory 202288 kb
Host smart-eaaec903-fe93-4b1d-85ab-0a03839a30e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812270324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3812270324
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4087247606
Short name T440
Test name
Test status
Simulation time 28319199162 ps
CPU time 40.15 seconds
Started Jul 13 06:50:38 PM PDT 24
Finished Jul 13 06:51:18 PM PDT 24
Peak memory 201716 kb
Host smart-1788d8cd-bd26-4ba6-8c66-2f256da7872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087247606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4087247606
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3394649099
Short name T343
Test name
Test status
Simulation time 4568063086 ps
CPU time 3.27 seconds
Started Jul 13 06:50:39 PM PDT 24
Finished Jul 13 06:50:43 PM PDT 24
Peak memory 201704 kb
Host smart-9a02e555-6ac9-48e4-b40f-c50c42ee4a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394649099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3394649099
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3085911330
Short name T632
Test name
Test status
Simulation time 5654522669 ps
CPU time 13.8 seconds
Started Jul 13 06:50:31 PM PDT 24
Finished Jul 13 06:50:46 PM PDT 24
Peak memory 201744 kb
Host smart-ae7003fb-75cd-4ca9-812b-f6c7d6f1c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085911330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3085911330
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.4073178363
Short name T490
Test name
Test status
Simulation time 170429583789 ps
CPU time 126.41 seconds
Started Jul 13 06:50:39 PM PDT 24
Finished Jul 13 06:52:46 PM PDT 24
Peak memory 201928 kb
Host smart-f35afa0c-c237-40b8-845c-ed07a930b370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073178363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.4073178363
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3366677760
Short name T668
Test name
Test status
Simulation time 75960225053 ps
CPU time 82.67 seconds
Started Jul 13 06:50:39 PM PDT 24
Finished Jul 13 06:52:02 PM PDT 24
Peak memory 210408 kb
Host smart-0e97430a-e519-4b5b-8bce-f53f27d27412
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366677760 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3366677760
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.114357032
Short name T718
Test name
Test status
Simulation time 509195755 ps
CPU time 0.81 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 06:50:54 PM PDT 24
Peak memory 201656 kb
Host smart-71ab2c1d-defe-41ae-b0aa-5a5f74885963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114357032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.114357032
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1256159531
Short name T279
Test name
Test status
Simulation time 159663789162 ps
CPU time 271.65 seconds
Started Jul 13 06:50:53 PM PDT 24
Finished Jul 13 06:55:25 PM PDT 24
Peak memory 201952 kb
Host smart-0cca0385-4d18-4b29-b2ae-d5f5cea84d40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256159531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1256159531
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1862654034
Short name T317
Test name
Test status
Simulation time 495110965518 ps
CPU time 1119.87 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 07:09:33 PM PDT 24
Peak memory 201908 kb
Host smart-f581cde6-c862-4d7f-be99-8e732a263c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862654034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1862654034
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3814975458
Short name T88
Test name
Test status
Simulation time 488306099987 ps
CPU time 1024.53 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 07:07:57 PM PDT 24
Peak memory 201976 kb
Host smart-6c0c9889-de42-40bb-9600-aa330c1e8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814975458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3814975458
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3376085189
Short name T91
Test name
Test status
Simulation time 165978752827 ps
CPU time 201.71 seconds
Started Jul 13 06:50:53 PM PDT 24
Finished Jul 13 06:54:16 PM PDT 24
Peak memory 202152 kb
Host smart-7c5bd08b-588a-439e-8a23-5b506c437b5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376085189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3376085189
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1506542098
Short name T106
Test name
Test status
Simulation time 327984875029 ps
CPU time 197.03 seconds
Started Jul 13 06:50:38 PM PDT 24
Finished Jul 13 06:53:56 PM PDT 24
Peak memory 201936 kb
Host smart-ecbb5ee0-c40e-4374-9635-ac8451bfc073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506542098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1506542098
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3275163733
Short name T693
Test name
Test status
Simulation time 162265819582 ps
CPU time 89.72 seconds
Started Jul 13 06:50:40 PM PDT 24
Finished Jul 13 06:52:10 PM PDT 24
Peak memory 201868 kb
Host smart-2ab194f7-916b-45e8-9583-a88d2438a139
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275163733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3275163733
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1082325139
Short name T629
Test name
Test status
Simulation time 178176369100 ps
CPU time 123.66 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 06:52:56 PM PDT 24
Peak memory 201904 kb
Host smart-95a62c76-351a-4071-ae7b-900ac3e99e91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082325139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1082325139
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3312967647
Short name T521
Test name
Test status
Simulation time 594964523050 ps
CPU time 356.46 seconds
Started Jul 13 06:50:51 PM PDT 24
Finished Jul 13 06:56:48 PM PDT 24
Peak memory 201892 kb
Host smart-86beff52-56fa-4862-9e27-31f7300c1e76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312967647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3312967647
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2216330259
Short name T585
Test name
Test status
Simulation time 79186604174 ps
CPU time 316.38 seconds
Started Jul 13 06:50:53 PM PDT 24
Finished Jul 13 06:56:10 PM PDT 24
Peak memory 202232 kb
Host smart-6eb833a0-f556-4aa7-9ed5-24b3f87bb86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216330259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2216330259
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.316635261
Short name T373
Test name
Test status
Simulation time 42803529729 ps
CPU time 45.56 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 06:51:38 PM PDT 24
Peak memory 201696 kb
Host smart-2c1ea9ca-1c3e-4721-9b07-eec9b49db63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316635261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.316635261
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1358424129
Short name T555
Test name
Test status
Simulation time 4739346676 ps
CPU time 6.52 seconds
Started Jul 13 06:50:53 PM PDT 24
Finished Jul 13 06:51:00 PM PDT 24
Peak memory 201700 kb
Host smart-17e4b32f-fd1c-40c0-8d23-a90074528c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358424129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1358424129
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1207787782
Short name T111
Test name
Test status
Simulation time 5774424502 ps
CPU time 4.18 seconds
Started Jul 13 06:50:40 PM PDT 24
Finished Jul 13 06:50:44 PM PDT 24
Peak memory 201720 kb
Host smart-c87f3431-7fda-4ccb-84ff-fdfc5ba3463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207787782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1207787782
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2730621754
Short name T227
Test name
Test status
Simulation time 198593058985 ps
CPU time 412.73 seconds
Started Jul 13 06:50:53 PM PDT 24
Finished Jul 13 06:57:46 PM PDT 24
Peak memory 201968 kb
Host smart-e190d557-0a35-44d7-9f5c-c6c91a623123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730621754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2730621754
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.385875388
Short name T42
Test name
Test status
Simulation time 68571368745 ps
CPU time 149.77 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 06:53:23 PM PDT 24
Peak memory 210232 kb
Host smart-b83f3e45-bd56-4bb4-886f-42aad5852c22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385875388 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.385875388
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2916092247
Short name T4
Test name
Test status
Simulation time 430754937 ps
CPU time 1.03 seconds
Started Jul 13 06:51:04 PM PDT 24
Finished Jul 13 06:51:06 PM PDT 24
Peak memory 201568 kb
Host smart-72e41387-c812-4bbf-8809-06f912ced8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916092247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2916092247
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2725433352
Short name T274
Test name
Test status
Simulation time 165310611524 ps
CPU time 9.77 seconds
Started Jul 13 06:51:03 PM PDT 24
Finished Jul 13 06:51:13 PM PDT 24
Peak memory 201852 kb
Host smart-10c651cc-7c76-41dd-9cce-3d30c3d3aa56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725433352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2725433352
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3720094178
Short name T425
Test name
Test status
Simulation time 163239504032 ps
CPU time 182.77 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 06:53:55 PM PDT 24
Peak memory 201876 kb
Host smart-40b56bb5-3134-43a8-af60-121cd2cff329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720094178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3720094178
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2101891093
Short name T778
Test name
Test status
Simulation time 326390382150 ps
CPU time 168.27 seconds
Started Jul 13 06:50:52 PM PDT 24
Finished Jul 13 06:53:41 PM PDT 24
Peak memory 201892 kb
Host smart-1e43ff7b-588f-4fa4-a276-9a04b2b997a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101891093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2101891093
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1597793298
Short name T765
Test name
Test status
Simulation time 165509231113 ps
CPU time 91.84 seconds
Started Jul 13 06:50:51 PM PDT 24
Finished Jul 13 06:52:24 PM PDT 24
Peak memory 201972 kb
Host smart-203dffd8-0a1b-467f-97b7-09f32c8be9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597793298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1597793298
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2153004674
Short name T766
Test name
Test status
Simulation time 486899141725 ps
CPU time 1173.79 seconds
Started Jul 13 06:50:51 PM PDT 24
Finished Jul 13 07:10:25 PM PDT 24
Peak memory 201932 kb
Host smart-0cf14e15-a9cd-43b2-bbda-5c22f679ac67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153004674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2153004674
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.341796811
Short name T228
Test name
Test status
Simulation time 668509061636 ps
CPU time 1509.87 seconds
Started Jul 13 06:51:00 PM PDT 24
Finished Jul 13 07:16:11 PM PDT 24
Peak memory 201980 kb
Host smart-d3f35eb9-630a-4936-a50e-8e28b0929fb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341796811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.341796811
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.850730337
Short name T779
Test name
Test status
Simulation time 614545486413 ps
CPU time 684.95 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 07:02:27 PM PDT 24
Peak memory 201900 kb
Host smart-e129f0b5-8cc1-48c6-a08c-9ec0d3b217a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850730337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.850730337
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1999987674
Short name T44
Test name
Test status
Simulation time 72425172545 ps
CPU time 298.44 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:56:01 PM PDT 24
Peak memory 202240 kb
Host smart-e72ff3de-bdb7-408b-8463-c06ecb77ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999987674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1999987674
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3196729716
Short name T427
Test name
Test status
Simulation time 29279165222 ps
CPU time 18.3 seconds
Started Jul 13 06:51:05 PM PDT 24
Finished Jul 13 06:51:24 PM PDT 24
Peak memory 201616 kb
Host smart-0d1b3751-c81c-4c52-ab67-59d631bd005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196729716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3196729716
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3227462822
Short name T774
Test name
Test status
Simulation time 3132648216 ps
CPU time 1.45 seconds
Started Jul 13 06:51:06 PM PDT 24
Finished Jul 13 06:51:08 PM PDT 24
Peak memory 201624 kb
Host smart-28c412de-bd41-4c09-856f-5a47a3ecc719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227462822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3227462822
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2331834314
Short name T680
Test name
Test status
Simulation time 5666520638 ps
CPU time 4.77 seconds
Started Jul 13 06:50:53 PM PDT 24
Finished Jul 13 06:50:58 PM PDT 24
Peak memory 201720 kb
Host smart-43d41aff-45f8-41e2-80ca-cf4009156642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331834314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2331834314
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2356941160
Short name T674
Test name
Test status
Simulation time 335438328384 ps
CPU time 206.34 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:54:29 PM PDT 24
Peak memory 201984 kb
Host smart-7cdbe268-56d9-4057-9f4b-e95baffba090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356941160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2356941160
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1783496803
Short name T239
Test name
Test status
Simulation time 39666156880 ps
CPU time 88.15 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:52:29 PM PDT 24
Peak memory 210228 kb
Host smart-a0383ccd-9782-4a59-b6fa-446db95c67a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783496803 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1783496803
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.311259025
Short name T570
Test name
Test status
Simulation time 292820447 ps
CPU time 0.98 seconds
Started Jul 13 06:51:03 PM PDT 24
Finished Jul 13 06:51:04 PM PDT 24
Peak memory 201492 kb
Host smart-64b8b5a9-1781-4056-aff5-12de2aea7a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311259025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.311259025
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2955187073
Short name T581
Test name
Test status
Simulation time 217212016405 ps
CPU time 497.01 seconds
Started Jul 13 06:51:04 PM PDT 24
Finished Jul 13 06:59:21 PM PDT 24
Peak memory 201912 kb
Host smart-000c59cc-d0b7-4809-8c1f-ce02e7c9d17c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955187073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2955187073
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.111637450
Short name T157
Test name
Test status
Simulation time 176313602887 ps
CPU time 396.46 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:57:39 PM PDT 24
Peak memory 201916 kb
Host smart-b42436fb-9c48-4d01-900f-59ba632a2fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111637450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.111637450
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2589905562
Short name T93
Test name
Test status
Simulation time 162968940295 ps
CPU time 182.19 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:54:04 PM PDT 24
Peak memory 201864 kb
Host smart-6cfe6259-9109-4e4a-91ec-07ed83fc8dc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589905562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2589905562
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4192001708
Short name T507
Test name
Test status
Simulation time 167264776361 ps
CPU time 375.41 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:57:17 PM PDT 24
Peak memory 201920 kb
Host smart-bcaf21bd-0bec-4d76-a0d7-8ecf52d149f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192001708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4192001708
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3646879630
Short name T689
Test name
Test status
Simulation time 163242537012 ps
CPU time 89.15 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:52:32 PM PDT 24
Peak memory 201868 kb
Host smart-3b5522a7-8c09-49df-89fa-356783bd5a89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646879630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3646879630
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3414732436
Short name T691
Test name
Test status
Simulation time 426720340372 ps
CPU time 72.35 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:52:15 PM PDT 24
Peak memory 201976 kb
Host smart-a07e1855-6d14-45e4-a487-9ee6a2152420
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414732436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3414732436
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2262139230
Short name T771
Test name
Test status
Simulation time 103588265483 ps
CPU time 364.17 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:57:06 PM PDT 24
Peak memory 202300 kb
Host smart-be46480a-007e-45a3-9572-3829b721c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262139230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2262139230
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2842927166
Short name T455
Test name
Test status
Simulation time 27161500311 ps
CPU time 15.22 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:51:17 PM PDT 24
Peak memory 201732 kb
Host smart-5f5ddcc3-3856-4f84-bee0-6a956f4aed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842927166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2842927166
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3255833612
Short name T529
Test name
Test status
Simulation time 4239359149 ps
CPU time 2.79 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:51:06 PM PDT 24
Peak memory 201728 kb
Host smart-5674da6a-ce15-4c56-ba94-b285bdf7a7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255833612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3255833612
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4192039891
Short name T761
Test name
Test status
Simulation time 5899647880 ps
CPU time 3.26 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:51:04 PM PDT 24
Peak memory 201736 kb
Host smart-d205cce4-586d-47d8-8ebc-8d509873cc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192039891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4192039891
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2647470755
Short name T481
Test name
Test status
Simulation time 333977846064 ps
CPU time 399.09 seconds
Started Jul 13 06:51:02 PM PDT 24
Finished Jul 13 06:57:42 PM PDT 24
Peak memory 201920 kb
Host smart-9cbecad3-2739-465c-85fe-874defb3d8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647470755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2647470755
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2149843582
Short name T86
Test name
Test status
Simulation time 456531892 ps
CPU time 1.56 seconds
Started Jul 13 06:51:21 PM PDT 24
Finished Jul 13 06:51:23 PM PDT 24
Peak memory 201696 kb
Host smart-1fd2ff7f-276a-4a6d-b7ce-772e7ac91f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149843582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2149843582
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.223698691
Short name T642
Test name
Test status
Simulation time 164826794923 ps
CPU time 338.79 seconds
Started Jul 13 06:51:11 PM PDT 24
Finished Jul 13 06:56:50 PM PDT 24
Peak memory 201748 kb
Host smart-a1f229c3-b9f6-4bc0-82cd-efa6ca4350ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223698691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.223698691
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1180892832
Short name T542
Test name
Test status
Simulation time 333172035229 ps
CPU time 374.13 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 06:57:24 PM PDT 24
Peak memory 201868 kb
Host smart-4f8c5a6f-bce9-4815-9720-853ba3ccee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180892832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1180892832
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.529515544
Short name T721
Test name
Test status
Simulation time 494943621079 ps
CPU time 308.57 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 06:56:19 PM PDT 24
Peak memory 201880 kb
Host smart-4ea240d3-c75a-426c-8f36-08a5888ed392
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=529515544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.529515544
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3429849098
Short name T13
Test name
Test status
Simulation time 499414589465 ps
CPU time 1124.36 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 07:09:54 PM PDT 24
Peak memory 201968 kb
Host smart-5c06e7dd-cfd3-4e9f-b57b-a6a29ceb17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429849098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3429849098
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2832822439
Short name T599
Test name
Test status
Simulation time 327462662793 ps
CPU time 767.22 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 07:03:57 PM PDT 24
Peak memory 201872 kb
Host smart-7268141c-e5de-4b8f-ab01-4425b9d3b75c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832822439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2832822439
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1512516043
Short name T531
Test name
Test status
Simulation time 605029607015 ps
CPU time 720.01 seconds
Started Jul 13 06:51:12 PM PDT 24
Finished Jul 13 07:03:13 PM PDT 24
Peak memory 201800 kb
Host smart-6855190d-13be-4a67-b155-351acb28f24e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512516043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1512516043
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1947125760
Short name T708
Test name
Test status
Simulation time 118064111953 ps
CPU time 408.08 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 06:57:58 PM PDT 24
Peak memory 202200 kb
Host smart-4a306026-f969-4ea9-ae53-8a8a1cf6cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947125760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1947125760
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2246014454
Short name T578
Test name
Test status
Simulation time 40202644237 ps
CPU time 85.09 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 06:52:35 PM PDT 24
Peak memory 201700 kb
Host smart-8f0261d3-0c5b-441b-8ac3-9f21394601d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246014454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2246014454
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1332643395
Short name T85
Test name
Test status
Simulation time 3148147684 ps
CPU time 1.69 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 06:51:11 PM PDT 24
Peak memory 201692 kb
Host smart-c766de0a-275c-4fe0-ab84-f369a93103dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332643395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1332643395
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1675946409
Short name T517
Test name
Test status
Simulation time 6031722586 ps
CPU time 7.93 seconds
Started Jul 13 06:51:01 PM PDT 24
Finished Jul 13 06:51:10 PM PDT 24
Peak memory 201720 kb
Host smart-86979bda-c1fa-42bd-b17f-a948ef6bd048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675946409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1675946409
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1955174272
Short name T262
Test name
Test status
Simulation time 358275418190 ps
CPU time 759.68 seconds
Started Jul 13 06:51:22 PM PDT 24
Finished Jul 13 07:04:02 PM PDT 24
Peak memory 201996 kb
Host smart-4c033c1d-5a2f-439c-966f-6d399dce5410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955174272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1955174272
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.102322435
Short name T16
Test name
Test status
Simulation time 54549849058 ps
CPU time 56.5 seconds
Started Jul 13 06:51:09 PM PDT 24
Finished Jul 13 06:52:06 PM PDT 24
Peak memory 210216 kb
Host smart-4dcb5eef-79ae-41aa-a563-8ecc5a73939f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102322435 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.102322435
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4174844222
Short name T722
Test name
Test status
Simulation time 302754953 ps
CPU time 1.24 seconds
Started Jul 13 06:51:31 PM PDT 24
Finished Jul 13 06:51:33 PM PDT 24
Peak memory 201688 kb
Host smart-7ea15691-8101-4d02-a9a0-2ca496992e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174844222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4174844222
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4097082337
Short name T458
Test name
Test status
Simulation time 339554490056 ps
CPU time 174.97 seconds
Started Jul 13 06:51:26 PM PDT 24
Finished Jul 13 06:54:21 PM PDT 24
Peak memory 201908 kb
Host smart-d02f2bbf-f585-463c-8c2e-95726e8afafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097082337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4097082337
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3467984705
Short name T155
Test name
Test status
Simulation time 492838821821 ps
CPU time 530.38 seconds
Started Jul 13 06:51:21 PM PDT 24
Finished Jul 13 07:00:11 PM PDT 24
Peak memory 201924 kb
Host smart-1c76fbc9-06a5-4798-bd2a-77b0231469d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467984705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3467984705
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1630600506
Short name T593
Test name
Test status
Simulation time 331711751276 ps
CPU time 748.87 seconds
Started Jul 13 06:51:20 PM PDT 24
Finished Jul 13 07:03:49 PM PDT 24
Peak memory 201916 kb
Host smart-f41b723d-8e08-4160-88eb-b9cdd7e60855
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630600506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1630600506
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.609149332
Short name T705
Test name
Test status
Simulation time 489376838002 ps
CPU time 1131.31 seconds
Started Jul 13 06:51:21 PM PDT 24
Finished Jul 13 07:10:12 PM PDT 24
Peak memory 201960 kb
Host smart-79cd2048-98ab-4f6d-b4cc-93ce71e1193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609149332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.609149332
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1343675882
Short name T609
Test name
Test status
Simulation time 329723614523 ps
CPU time 727.84 seconds
Started Jul 13 06:51:26 PM PDT 24
Finished Jul 13 07:03:34 PM PDT 24
Peak memory 201912 kb
Host smart-fd8a526e-10e4-4a73-a66a-62cd375d83c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343675882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1343675882
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4274627440
Short name T400
Test name
Test status
Simulation time 611865784075 ps
CPU time 1307.59 seconds
Started Jul 13 06:51:20 PM PDT 24
Finished Jul 13 07:13:08 PM PDT 24
Peak memory 201852 kb
Host smart-0bf52370-08ee-4cbe-8b8c-e0922f751d45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274627440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4274627440
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.975691260
Short name T334
Test name
Test status
Simulation time 117851851426 ps
CPU time 399.31 seconds
Started Jul 13 06:51:26 PM PDT 24
Finished Jul 13 06:58:06 PM PDT 24
Peak memory 202208 kb
Host smart-cb22f435-d361-4ac5-9112-4fb44914bfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975691260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.975691260
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4058856147
Short name T402
Test name
Test status
Simulation time 32111587973 ps
CPU time 20.17 seconds
Started Jul 13 06:51:21 PM PDT 24
Finished Jul 13 06:51:42 PM PDT 24
Peak memory 201712 kb
Host smart-bd2c8d45-d67c-4288-a3f0-129a7bff34d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058856147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4058856147
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1545941940
Short name T504
Test name
Test status
Simulation time 4383909224 ps
CPU time 5.89 seconds
Started Jul 13 06:51:21 PM PDT 24
Finished Jul 13 06:51:27 PM PDT 24
Peak memory 201720 kb
Host smart-112379d6-6989-49c4-a005-34faa842a676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545941940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1545941940
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.384633273
Short name T613
Test name
Test status
Simulation time 6022283792 ps
CPU time 7.25 seconds
Started Jul 13 06:51:23 PM PDT 24
Finished Jul 13 06:51:30 PM PDT 24
Peak memory 201976 kb
Host smart-535849f2-445a-4e4e-930e-a8d566b7d426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384633273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.384633273
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.528491558
Short name T644
Test name
Test status
Simulation time 207684156699 ps
CPU time 418.8 seconds
Started Jul 13 06:51:21 PM PDT 24
Finished Jul 13 06:58:20 PM PDT 24
Peak memory 210552 kb
Host smart-452df6fb-c8b5-425a-8afd-dc5611f45b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528491558 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.528491558
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3276732924
Short name T793
Test name
Test status
Simulation time 364738105 ps
CPU time 1.4 seconds
Started Jul 13 06:51:41 PM PDT 24
Finished Jul 13 06:51:42 PM PDT 24
Peak memory 201832 kb
Host smart-90463768-c1a1-45fa-af5d-87df392b3ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276732924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3276732924
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3126115571
Short name T457
Test name
Test status
Simulation time 343433496998 ps
CPU time 629.8 seconds
Started Jul 13 06:51:30 PM PDT 24
Finished Jul 13 07:02:00 PM PDT 24
Peak memory 201940 kb
Host smart-83552d60-1f3b-4fa3-961d-9f457873079d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126115571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3126115571
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3866850461
Short name T551
Test name
Test status
Simulation time 517723738979 ps
CPU time 1151.23 seconds
Started Jul 13 06:51:30 PM PDT 24
Finished Jul 13 07:10:42 PM PDT 24
Peak memory 201964 kb
Host smart-7a4a4a5b-90da-4588-ba2b-82af55c9f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866850461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3866850461
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4184284808
Short name T591
Test name
Test status
Simulation time 492446479141 ps
CPU time 251.5 seconds
Started Jul 13 06:51:30 PM PDT 24
Finished Jul 13 06:55:42 PM PDT 24
Peak memory 201740 kb
Host smart-b46e196a-953f-42bf-b895-4d1f80ca4b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184284808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4184284808
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1816203744
Short name T445
Test name
Test status
Simulation time 324847957529 ps
CPU time 721.33 seconds
Started Jul 13 06:51:29 PM PDT 24
Finished Jul 13 07:03:31 PM PDT 24
Peak memory 201904 kb
Host smart-c26d7250-f846-478e-95b8-78a745349e65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816203744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1816203744
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3650621616
Short name T174
Test name
Test status
Simulation time 322659152626 ps
CPU time 92.23 seconds
Started Jul 13 06:51:29 PM PDT 24
Finished Jul 13 06:53:02 PM PDT 24
Peak memory 201948 kb
Host smart-b3cc1581-fbf8-4e39-8062-3ba6cec14f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650621616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3650621616
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3086024317
Short name T735
Test name
Test status
Simulation time 159272794354 ps
CPU time 177.23 seconds
Started Jul 13 06:51:30 PM PDT 24
Finished Jul 13 06:54:28 PM PDT 24
Peak memory 201872 kb
Host smart-0c45a120-1208-4873-8bf2-7346c0806719
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086024317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3086024317
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.337379767
Short name T92
Test name
Test status
Simulation time 557477665590 ps
CPU time 304.52 seconds
Started Jul 13 06:51:29 PM PDT 24
Finished Jul 13 06:56:34 PM PDT 24
Peak memory 201932 kb
Host smart-8948affa-ef62-4514-a729-40d12fc3437e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337379767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.337379767
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2105374944
Short name T377
Test name
Test status
Simulation time 608910516708 ps
CPU time 902.18 seconds
Started Jul 13 06:51:31 PM PDT 24
Finished Jul 13 07:06:33 PM PDT 24
Peak memory 201896 kb
Host smart-0ffdb0e1-c0b4-484c-99cf-6f348f944562
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105374944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2105374944
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2599741668
Short name T196
Test name
Test status
Simulation time 126435365809 ps
CPU time 428.91 seconds
Started Jul 13 06:51:28 PM PDT 24
Finished Jul 13 06:58:37 PM PDT 24
Peak memory 202280 kb
Host smart-4254aada-3ad3-46b6-bfad-cab1f5fccc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599741668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2599741668
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3624543959
Short name T444
Test name
Test status
Simulation time 43923009021 ps
CPU time 94.77 seconds
Started Jul 13 06:51:30 PM PDT 24
Finished Jul 13 06:53:05 PM PDT 24
Peak memory 201712 kb
Host smart-9c76d16c-5917-4bd4-81e3-2a62bc78a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624543959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3624543959
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2483306247
Short name T101
Test name
Test status
Simulation time 5000812179 ps
CPU time 11.69 seconds
Started Jul 13 06:51:28 PM PDT 24
Finished Jul 13 06:51:40 PM PDT 24
Peak memory 201716 kb
Host smart-23735481-e7a9-4ab4-a1da-6dbe02e3e892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483306247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2483306247
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1020482622
Short name T467
Test name
Test status
Simulation time 5759612030 ps
CPU time 7.5 seconds
Started Jul 13 06:51:29 PM PDT 24
Finished Jul 13 06:51:37 PM PDT 24
Peak memory 201720 kb
Host smart-d209b60d-b79a-41c8-82e0-0f03ce87dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020482622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1020482622
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3957273993
Short name T61
Test name
Test status
Simulation time 496727144734 ps
CPU time 833.65 seconds
Started Jul 13 06:51:29 PM PDT 24
Finished Jul 13 07:05:23 PM PDT 24
Peak memory 210536 kb
Host smart-e566378a-1104-473d-9631-91b5e2a92deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957273993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3957273993
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1725351366
Short name T459
Test name
Test status
Simulation time 518348458 ps
CPU time 0.92 seconds
Started Jul 13 06:46:55 PM PDT 24
Finished Jul 13 06:46:57 PM PDT 24
Peak memory 201596 kb
Host smart-9745b1c2-6b0a-4318-87ce-f75d6ebffdba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725351366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1725351366
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3402750725
Short name T785
Test name
Test status
Simulation time 162155979858 ps
CPU time 56.37 seconds
Started Jul 13 06:46:53 PM PDT 24
Finished Jul 13 06:47:50 PM PDT 24
Peak memory 201900 kb
Host smart-5a60e3ae-b087-4118-b802-419706e9270d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402750725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3402750725
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2359934458
Short name T310
Test name
Test status
Simulation time 163692467371 ps
CPU time 207.11 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:50:25 PM PDT 24
Peak memory 201740 kb
Host smart-133e3946-382f-41ac-a879-6dd0baceeafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359934458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2359934458
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.541132933
Short name T426
Test name
Test status
Simulation time 497377412320 ps
CPU time 1191.63 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 07:06:43 PM PDT 24
Peak memory 201860 kb
Host smart-48cfd650-da25-48dc-99b2-c00eea5c08de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=541132933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.541132933
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3296372230
Short name T746
Test name
Test status
Simulation time 332637246688 ps
CPU time 733.01 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:59:11 PM PDT 24
Peak memory 201980 kb
Host smart-ac16f3c2-bfd9-4162-9256-6875b52d9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296372230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3296372230
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.463841049
Short name T744
Test name
Test status
Simulation time 335397598248 ps
CPU time 168.51 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:49:37 PM PDT 24
Peak memory 201952 kb
Host smart-d77fe663-7f40-4e12-971d-c6de29638284
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=463841049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.463841049
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.981286615
Short name T553
Test name
Test status
Simulation time 585294487514 ps
CPU time 753.97 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:59:25 PM PDT 24
Peak memory 201080 kb
Host smart-e1fa0601-d9e3-4146-b256-56be3e91ed49
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981286615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.981286615
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4227467864
Short name T200
Test name
Test status
Simulation time 89805351060 ps
CPU time 326.31 seconds
Started Jul 13 06:46:54 PM PDT 24
Finished Jul 13 06:52:20 PM PDT 24
Peak memory 202224 kb
Host smart-10d150bf-2e8a-4c2d-a1a8-92f86aa15eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227467864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4227467864
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.570747077
Short name T527
Test name
Test status
Simulation time 27769617070 ps
CPU time 32.92 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:47:25 PM PDT 24
Peak memory 201720 kb
Host smart-bac38a18-7d26-4c2d-9d21-a9f9da5a2f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570747077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.570747077
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1622927829
Short name T565
Test name
Test status
Simulation time 5120459678 ps
CPU time 5.65 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:46:53 PM PDT 24
Peak memory 201704 kb
Host smart-551d559d-4d1a-45f8-a568-ca02d54f7d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622927829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1622927829
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.4167278547
Short name T363
Test name
Test status
Simulation time 5619334749 ps
CPU time 2.04 seconds
Started Jul 13 06:46:52 PM PDT 24
Finished Jul 13 06:46:55 PM PDT 24
Peak memory 201728 kb
Host smart-cb148f99-c41d-46ac-bca1-2dabdd898a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167278547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4167278547
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1297918655
Short name T66
Test name
Test status
Simulation time 26414947846 ps
CPU time 34.6 seconds
Started Jul 13 06:46:46 PM PDT 24
Finished Jul 13 06:47:21 PM PDT 24
Peak memory 210532 kb
Host smart-7c543abc-d758-4064-b6f2-52f5d269ab79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297918655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1297918655
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.312908605
Short name T595
Test name
Test status
Simulation time 514480815 ps
CPU time 0.68 seconds
Started Jul 13 06:47:03 PM PDT 24
Finished Jul 13 06:47:04 PM PDT 24
Peak memory 201660 kb
Host smart-20ac2ac6-db8d-4091-84bb-df56e948ff20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312908605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.312908605
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.514870324
Short name T742
Test name
Test status
Simulation time 489623530081 ps
CPU time 422.96 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:54:01 PM PDT 24
Peak memory 201920 kb
Host smart-96e3eecb-4cdc-46ea-942f-531d0b587f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514870324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.514870324
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3154584248
Short name T357
Test name
Test status
Simulation time 482935699671 ps
CPU time 555.64 seconds
Started Jul 13 06:46:50 PM PDT 24
Finished Jul 13 06:56:06 PM PDT 24
Peak memory 201908 kb
Host smart-f58b46ae-078d-48ca-a9e4-d12422d41fd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154584248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3154584248
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1485075368
Short name T104
Test name
Test status
Simulation time 488793821135 ps
CPU time 128.1 seconds
Started Jul 13 06:46:53 PM PDT 24
Finished Jul 13 06:49:01 PM PDT 24
Peak memory 201908 kb
Host smart-79eaac86-4f71-4bae-b95b-4b99b4e143f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485075368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1485075368
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3359686428
Short name T109
Test name
Test status
Simulation time 167408402501 ps
CPU time 99.88 seconds
Started Jul 13 06:46:48 PM PDT 24
Finished Jul 13 06:48:29 PM PDT 24
Peak memory 201900 kb
Host smart-d37fe8b4-11fb-49fb-93cb-ce4d79eea91a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359686428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3359686428
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1429141094
Short name T571
Test name
Test status
Simulation time 183185844564 ps
CPU time 429.88 seconds
Started Jul 13 06:46:55 PM PDT 24
Finished Jul 13 06:54:06 PM PDT 24
Peak memory 201932 kb
Host smart-77027d12-b371-461b-9ed1-3b2ef1506e4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429141094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1429141094
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1619328717
Short name T84
Test name
Test status
Simulation time 414021380067 ps
CPU time 439.12 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:54:16 PM PDT 24
Peak memory 201944 kb
Host smart-55d1b651-c8cb-4d4f-9431-282a63412e1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619328717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1619328717
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2084484808
Short name T201
Test name
Test status
Simulation time 107423773305 ps
CPU time 574.5 seconds
Started Jul 13 06:47:04 PM PDT 24
Finished Jul 13 06:56:39 PM PDT 24
Peak memory 202292 kb
Host smart-cbbd5891-336e-4e80-b3f0-8e46764dee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084484808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2084484808
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2573584903
Short name T418
Test name
Test status
Simulation time 26674554948 ps
CPU time 15.8 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:47:15 PM PDT 24
Peak memory 201720 kb
Host smart-cb619794-f504-4f17-98d6-e0a05bd59f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573584903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2573584903
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1031414736
Short name T350
Test name
Test status
Simulation time 5188874482 ps
CPU time 3.35 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:47:12 PM PDT 24
Peak memory 201664 kb
Host smart-4ea31f10-af92-4235-9956-5a23dce80ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031414736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1031414736
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2422079683
Short name T80
Test name
Test status
Simulation time 6033839616 ps
CPU time 14.16 seconds
Started Jul 13 06:46:51 PM PDT 24
Finished Jul 13 06:47:06 PM PDT 24
Peak memory 201728 kb
Host smart-9d296391-e673-4af4-97ef-825be7e49999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422079683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2422079683
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3637637883
Short name T204
Test name
Test status
Simulation time 579877173569 ps
CPU time 1536.52 seconds
Started Jul 13 06:47:03 PM PDT 24
Finished Jul 13 07:12:40 PM PDT 24
Peak memory 202212 kb
Host smart-2a84aace-675b-4dfc-b0ec-6eb3d40f71a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637637883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3637637883
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.565307248
Short name T296
Test name
Test status
Simulation time 25213486426 ps
CPU time 43.87 seconds
Started Jul 13 06:47:03 PM PDT 24
Finished Jul 13 06:47:47 PM PDT 24
Peak memory 202108 kb
Host smart-c77c57d8-98cb-4f50-b619-185647e7a2bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565307248 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.565307248
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.879560298
Short name T528
Test name
Test status
Simulation time 540381802 ps
CPU time 0.93 seconds
Started Jul 13 06:46:55 PM PDT 24
Finished Jul 13 06:46:57 PM PDT 24
Peak memory 201640 kb
Host smart-49b0cced-4bc3-4dc8-ac2e-8ce1191db2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879560298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.879560298
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1352522120
Short name T319
Test name
Test status
Simulation time 535398034725 ps
CPU time 550.38 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:56:09 PM PDT 24
Peak memory 201880 kb
Host smart-b5d98a52-2d17-4104-9a3d-e2c003e6575b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352522120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1352522120
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2722575183
Short name T321
Test name
Test status
Simulation time 180981872103 ps
CPU time 105.17 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:48:44 PM PDT 24
Peak memory 201916 kb
Host smart-bed7c3c7-762d-4244-8f4b-7c8ef925fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722575183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2722575183
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.915218318
Short name T433
Test name
Test status
Simulation time 164341219732 ps
CPU time 390.58 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:53:27 PM PDT 24
Peak memory 201892 kb
Host smart-cfce530d-2deb-4a77-8b2d-4b84f738261e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915218318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.915218318
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2294191101
Short name T782
Test name
Test status
Simulation time 499594283131 ps
CPU time 254.04 seconds
Started Jul 13 06:46:59 PM PDT 24
Finished Jul 13 06:51:13 PM PDT 24
Peak memory 201884 kb
Host smart-d875d1ac-8de5-421b-84c0-d114b2cca637
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294191101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2294191101
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.345463060
Short name T325
Test name
Test status
Simulation time 490091227456 ps
CPU time 1063.82 seconds
Started Jul 13 06:46:54 PM PDT 24
Finished Jul 13 07:04:39 PM PDT 24
Peak memory 201968 kb
Host smart-3ff63151-eb63-4a41-86f3-5c5e8832bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345463060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.345463060
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1464784392
Short name T526
Test name
Test status
Simulation time 322255380640 ps
CPU time 313.59 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:52:19 PM PDT 24
Peak memory 201876 kb
Host smart-dbb2058b-1775-4edd-9fa5-e5592417f31c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464784392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1464784392
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2561964898
Short name T176
Test name
Test status
Simulation time 573395461738 ps
CPU time 325.41 seconds
Started Jul 13 06:47:06 PM PDT 24
Finished Jul 13 06:52:32 PM PDT 24
Peak memory 201912 kb
Host smart-01cb0ae1-9dc6-429f-95fc-613955b7a479
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561964898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2561964898
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2832298821
Short name T479
Test name
Test status
Simulation time 407470197837 ps
CPU time 961.13 seconds
Started Jul 13 06:46:55 PM PDT 24
Finished Jul 13 07:02:58 PM PDT 24
Peak memory 201932 kb
Host smart-9685d130-1083-4531-81e0-ff68463ed95e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832298821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2832298821
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.935922390
Short name T332
Test name
Test status
Simulation time 108963733150 ps
CPU time 461.28 seconds
Started Jul 13 06:47:01 PM PDT 24
Finished Jul 13 06:54:42 PM PDT 24
Peak memory 202236 kb
Host smart-6aab641f-2574-4ea6-b1b9-671feddd9bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935922390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.935922390
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4144034202
Short name T435
Test name
Test status
Simulation time 46874048076 ps
CPU time 29.33 seconds
Started Jul 13 06:47:01 PM PDT 24
Finished Jul 13 06:47:31 PM PDT 24
Peak memory 201568 kb
Host smart-2c549722-e882-46e2-84ff-07fc9e71c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144034202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4144034202
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1936142550
Short name T468
Test name
Test status
Simulation time 5428301090 ps
CPU time 14.69 seconds
Started Jul 13 06:47:01 PM PDT 24
Finished Jul 13 06:47:16 PM PDT 24
Peak memory 201708 kb
Host smart-d7c84ee8-d52c-43a2-a45a-fe9cb211ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936142550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1936142550
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4134548031
Short name T462
Test name
Test status
Simulation time 5992675355 ps
CPU time 2.45 seconds
Started Jul 13 06:47:03 PM PDT 24
Finished Jul 13 06:47:06 PM PDT 24
Peak memory 201724 kb
Host smart-189c89d6-15ef-4c1b-bc0f-440db17b404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134548031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4134548031
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.358382781
Short name T304
Test name
Test status
Simulation time 174972040515 ps
CPU time 289.36 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:51:47 PM PDT 24
Peak memory 201892 kb
Host smart-34391c94-682a-44c4-ad84-c2071d270503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358382781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.358382781
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.986616136
Short name T569
Test name
Test status
Simulation time 70108554121 ps
CPU time 44.62 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:47:51 PM PDT 24
Peak memory 202036 kb
Host smart-1e474367-5edc-44e8-beb5-bb41cbb3c8b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986616136 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.986616136
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2488178532
Short name T769
Test name
Test status
Simulation time 376615904 ps
CPU time 1.5 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:47:07 PM PDT 24
Peak memory 201668 kb
Host smart-30a7a417-fbf5-45d4-a592-389a86d6e040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488178532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2488178532
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1400640128
Short name T186
Test name
Test status
Simulation time 505013201059 ps
CPU time 307.49 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:52:05 PM PDT 24
Peak memory 201984 kb
Host smart-e3f6a0b3-484d-436b-9046-ccf28d15283a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400640128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1400640128
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1971643662
Short name T663
Test name
Test status
Simulation time 164745387829 ps
CPU time 59.69 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:47:58 PM PDT 24
Peak memory 201872 kb
Host smart-de344159-4d38-49c4-90e0-fe1d281e5f51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971643662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1971643662
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2322524262
Short name T5
Test name
Test status
Simulation time 167916928388 ps
CPU time 361.25 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:53:00 PM PDT 24
Peak memory 201964 kb
Host smart-1a909c28-29fb-4a39-8daa-c99bd335b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322524262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2322524262
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3614900371
Short name T600
Test name
Test status
Simulation time 322749235654 ps
CPU time 192.23 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:50:18 PM PDT 24
Peak memory 201268 kb
Host smart-c3dc528b-72a8-435e-b160-7d1eea3163a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614900371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3614900371
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2807002101
Short name T307
Test name
Test status
Simulation time 538534836038 ps
CPU time 289.45 seconds
Started Jul 13 06:47:01 PM PDT 24
Finished Jul 13 06:51:51 PM PDT 24
Peak memory 201904 kb
Host smart-65c7a56c-51e9-4b35-ad60-87d80a564d93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807002101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2807002101
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3086947020
Short name T376
Test name
Test status
Simulation time 204871141685 ps
CPU time 474.75 seconds
Started Jul 13 06:47:09 PM PDT 24
Finished Jul 13 06:55:05 PM PDT 24
Peak memory 201808 kb
Host smart-b637ee23-2d2b-4aac-8350-559a7ccd0963
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086947020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3086947020
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.661001372
Short name T432
Test name
Test status
Simulation time 100461702432 ps
CPU time 414.27 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:54:01 PM PDT 24
Peak memory 202232 kb
Host smart-58cea5b7-8560-4138-bccc-bf41d1e2552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661001372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.661001372
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.453944954
Short name T749
Test name
Test status
Simulation time 37024938081 ps
CPU time 83.39 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:48:20 PM PDT 24
Peak memory 201732 kb
Host smart-8683058b-8899-467b-90c8-f643465998d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453944954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.453944954
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3059864200
Short name T367
Test name
Test status
Simulation time 4940005212 ps
CPU time 11.42 seconds
Started Jul 13 06:47:06 PM PDT 24
Finished Jul 13 06:47:18 PM PDT 24
Peak memory 201716 kb
Host smart-324753ec-3bcf-4ddd-aa9d-358219463149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059864200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3059864200
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1385957042
Short name T379
Test name
Test status
Simulation time 5925017020 ps
CPU time 14.26 seconds
Started Jul 13 06:47:02 PM PDT 24
Finished Jul 13 06:47:16 PM PDT 24
Peak memory 201652 kb
Host smart-30d01ee9-1a0f-4ba9-a941-7e50a209b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385957042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1385957042
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.29403457
Short name T396
Test name
Test status
Simulation time 440632321 ps
CPU time 1.58 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:47:07 PM PDT 24
Peak memory 201660 kb
Host smart-bad3a49b-69dd-44ee-8dcd-12c5e1789036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.29403457
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.733740860
Short name T758
Test name
Test status
Simulation time 329196273734 ps
CPU time 68.51 seconds
Started Jul 13 06:46:59 PM PDT 24
Finished Jul 13 06:48:08 PM PDT 24
Peak memory 201972 kb
Host smart-2d9d6e99-57eb-4d9b-a094-28bf6a88ed02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733740860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.733740860
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2437761280
Short name T658
Test name
Test status
Simulation time 238075509468 ps
CPU time 498.54 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:55:24 PM PDT 24
Peak memory 201912 kb
Host smart-c75197eb-375c-49af-9cb2-090594f46303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437761280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2437761280
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.278503493
Short name T189
Test name
Test status
Simulation time 491165034663 ps
CPU time 1034.88 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 07:04:21 PM PDT 24
Peak memory 201872 kb
Host smart-ef3558aa-7f69-4a10-9201-5f43cf6dcdad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=278503493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.278503493
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4198379245
Short name T140
Test name
Test status
Simulation time 324975820974 ps
CPU time 643.12 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:57:48 PM PDT 24
Peak memory 201912 kb
Host smart-2b367bb1-e956-4926-a814-4bde2002e250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198379245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4198379245
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3638962905
Short name T690
Test name
Test status
Simulation time 322066421197 ps
CPU time 49.23 seconds
Started Jul 13 06:47:01 PM PDT 24
Finished Jul 13 06:47:51 PM PDT 24
Peak memory 201696 kb
Host smart-59b22967-a806-427d-a59e-071d70b853ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638962905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3638962905
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2770230039
Short name T302
Test name
Test status
Simulation time 181560198833 ps
CPU time 136.63 seconds
Started Jul 13 06:47:05 PM PDT 24
Finished Jul 13 06:49:23 PM PDT 24
Peak memory 201212 kb
Host smart-6f1d4373-f92a-4401-9dcd-bb57ca827b5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770230039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2770230039
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3861848426
Short name T469
Test name
Test status
Simulation time 389355798426 ps
CPU time 222.06 seconds
Started Jul 13 06:46:56 PM PDT 24
Finished Jul 13 06:50:39 PM PDT 24
Peak memory 201904 kb
Host smart-bd4e5982-2270-4d6c-b0b2-600242c6a10f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861848426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3861848426
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2527215499
Short name T336
Test name
Test status
Simulation time 121149342060 ps
CPU time 630.01 seconds
Started Jul 13 06:46:55 PM PDT 24
Finished Jul 13 06:57:26 PM PDT 24
Peak memory 202268 kb
Host smart-96f70a7d-6237-475c-9af0-bfd16e2c192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527215499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2527215499
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4192435708
Short name T491
Test name
Test status
Simulation time 29848783122 ps
CPU time 65.25 seconds
Started Jul 13 06:47:01 PM PDT 24
Finished Jul 13 06:48:07 PM PDT 24
Peak memory 201704 kb
Host smart-13ddd05c-9d32-4f1f-a43e-62518828d06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192435708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4192435708
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1924206531
Short name T651
Test name
Test status
Simulation time 3318281111 ps
CPU time 7.94 seconds
Started Jul 13 06:46:57 PM PDT 24
Finished Jul 13 06:47:05 PM PDT 24
Peak memory 201708 kb
Host smart-b5640b0c-5b82-40ba-b29a-d94a933d3551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924206531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1924206531
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2448776689
Short name T383
Test name
Test status
Simulation time 5762663297 ps
CPU time 4.13 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:47:03 PM PDT 24
Peak memory 201696 kb
Host smart-d6704ccc-47d8-4ed2-9425-98100751ba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448776689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2448776689
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.845943271
Short name T628
Test name
Test status
Simulation time 140720815503 ps
CPU time 367.04 seconds
Started Jul 13 06:47:07 PM PDT 24
Finished Jul 13 06:53:15 PM PDT 24
Peak memory 218100 kb
Host smart-81ec46dd-7b02-4060-905b-9fb9cff689ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845943271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.845943271
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3978457840
Short name T538
Test name
Test status
Simulation time 49496948899 ps
CPU time 68.57 seconds
Started Jul 13 06:46:58 PM PDT 24
Finished Jul 13 06:48:07 PM PDT 24
Peak memory 210252 kb
Host smart-60f88581-4022-46e4-93ba-67ee42382aa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978457840 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3978457840
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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