Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7451	1			T2	41		T3	20		T9	10
testmodes[AdcCtrlTestmodeNormal]	5918	1			T1	1		T2	50		T9	9
testmodes[AdcCtrlTestmodeLowpower]	5837	1			T2	48		T5	3		T6	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4029	1			T2	15		T3	19		T9	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1868	1			T2	13		T9	4		T12	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1431	1			T2	13		T12	1		T54	11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1839	1			T2	13		T9	4		T12	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2167	1			T2	22		T9	4		T12	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1580	1			T2	14		T12	1		T54	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1468	1			T2	12		T12	1		T54	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1539	1			T2	15		T12	1		T54	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2585	1			T2	21		T5	2		T7	10