Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv



Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
testmode_cp 12 0 12 100.00 100 1 1 0


Summary for Variable testmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for testmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
testmodes[AdcCtrlTestmodeOneShot] 7451 1 T2 41 T3 20 T9 10
testmodes[AdcCtrlTestmodeNormal] 5918 1 T1 1 T2 50 T9 9
testmodes[AdcCtrlTestmodeLowpower] 5837 1 T2 48 T5 3 T6 1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot] 4029 1 T2 15 T3 19 T9 6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal] 1868 1 T2 13 T9 4 T12 2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower] 1431 1 T2 13 T12 1 T54 11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot] 1839 1 T2 13 T9 4 T12 2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal] 2167 1 T2 22 T9 4 T12 3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower] 1580 1 T2 14 T12 1 T54 18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot] 1468 1 T2 12 T12 1 T54 14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal] 1539 1 T2 15 T12 1 T54 16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower] 2585 1 T2 21 T5 2 T7 10

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%