Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23782

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3477

1

T1

3

T10

16

T12

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21649

1

T1

3

T2

139

T3

20

auto[1]

5610

1

T5

29

T10

12

T12

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T203	12		-	-		-	-
values[0]	59	1			T151	24		T182	14		T204	13
values[1]	693	1			T147	1		T148	10		T149	1
values[2]	559	1			T151	2		T84	13		T205	1
values[3]	642	1			T13	10		T14	10		T165	1
values[4]	769	1			T1	3		T6	15		T10	5
values[5]	806	1			T10	12		T14	10		T41	5
values[6]	689	1			T12	13		T13	18		T173	2
values[7]	764	1			T13	16		T74	38		T152	1
values[8]	629	1			T10	11		T44	1		T148	12
values[9]	3371	1			T5	29		T15	8		T16	35
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	779	1			T147	1		T148	10		T149	1
values[1]	760	1			T158	11		T151	2		T84	13
values[2]	583	1			T6	15		T13	10		T14	10
values[3]	759	1			T1	3		T10	17		T14	10
values[4]	742	1			T12	13		T41	5		T53	19
values[5]	800	1			T13	16		T173	1		T158	12
values[6]	2726	1			T5	29		T13	18		T15	8
values[7]	839	1			T10	11		T44	2		T148	12
values[8]	857	1			T45	1		T53	26		T177	19
values[9]	136	1			T164	1		T154	1		T177	2
minimum	18278	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T147	1		T151	13		T17	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T148	1		T149	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T205	1		T42	4		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T158	1		T151	1		T84	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	5		T13	4		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	10		T41	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	12		T46	13		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	1		T10	5		T14	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	1		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	10		T165	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T207	4		T157	10		T161	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	9		T173	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T5	29		T13	11		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T208	8		T209	1		T210	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T165	1		T17	17		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T10	11		T44	2		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T53	16		T84	9		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	1		T177	10		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T164	1		T154	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T211	1		T116	1		T212	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18129	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T151	11		T213	17		T214	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T148	9		T17	1		T170	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T42	1		T206	1		T104	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T158	10		T151	1		T84	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T6	10		T13	6		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T41	14		T39	2		T169	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T145	8		T158	3		T84	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	2		T17	15		T110	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	4		T53	9		T156	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	3		T169	7		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T207	2		T161	2		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	7		T158	11		T74	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T13	7		T216	18		T217	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T208	7		T210	1		T91	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	10		T108	9		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T148	10		T17	3		T219	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T53	10		T84	7		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T177	9		T168	11		T179	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T177	1		T167	1		T116	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T116	13		T22	1		T220	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T74	1		T39	5		T40	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T203	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T151	13		T221	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T182	6		T204	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T147	1		T222	1		T213	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T148	1		T149	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T205	1		T17	7		T42	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T151	1		T84	5		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	4		T145	10		T223	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	10		T165	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	5		T46	13		T53	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T10	5		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	12		T41	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	10		T165	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	11		T173	1		T207	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	10		T173	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T157	10		T224	1		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	9		T74	18		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T165	1		T32	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	11		T44	1		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1753	1			T5	29		T15	8		T16	35
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T44	1		T45	1		T177	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T203	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T151	11		T221	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T182	8		T204	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T213	17		T214	3		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T148	9		T17	1		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T42	1		T206	1		T104	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T151	1		T84	8		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	6		T145	8		T223	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T158	10		T169	8		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	10		T53	9		T158	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	2		T41	14		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	4		T156	3		T167	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T158	11		T17	7		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	7		T207	2		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	3		T156	4		T48	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T225	9		T37	14		T226	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	7		T74	20		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	3		T218	10		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T148	10		T17	3		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T53	10		T216	18		T177	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T177	9		T168	11		T170	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T147	1		T151	12		T17	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	10		T149	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T205	1		T42	3		T206	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T158	11		T151	2		T84	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	11		T13	7		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	1		T41	15		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	1		T46	1		T145	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	3		T10	1		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T41	5		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	10		T165	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T207	3		T157	1		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T13	8		T173	1		T158	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T5	3		T13	8		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T208	8		T209	1		T210	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T165	1		T17	12		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	1		T44	2		T148	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T53	11		T84	8		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T45	1		T177	10		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T164	1		T154	1		T177	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T211	1		T116	14		T212	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18278	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T151	12		T17	6		T213	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T227	12		T170	13		T105	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T42	2		T104	10		T161	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T84	4		T218	8		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	4		T13	3		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	9		T87	11		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	11		T46	12		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	4		T14	9		T46	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T53	9		T156	3		T215	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	3		T87	16		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T207	3		T157	9		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	8		T74	17		T156	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T5	26		T13	10		T15	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T208	7		T210	1		T91	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	15		T180	15		T108	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	10		T157	14		T153	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T53	15		T84	8		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T177	9		T168	9		T179	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T228	16		T229	7		T230	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T212	7		T22	1		T220	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T203	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T151	12		T221	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T182	9		T204	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T147	1		T222	1		T213	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	10		T149	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T205	1		T17	1		T42	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T151	2		T84	9		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	7		T145	9		T223	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	1		T165	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	11		T46	1		T53	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	3		T10	1		T41	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	1		T41	5		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T165	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	8		T173	1		T207	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	10		T173	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T157	1		T224	1		T225	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	8		T74	21		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T165	1		T32	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	1		T44	1		T148	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T5	3		T15	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T44	1		T45	1		T177	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T151	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T182	5		T204	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T213	10		T214	9		T231	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T227	12		T170	13		T105	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T17	6		T42	2		T104	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T84	4		T51	1		T94	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	3		T145	9		T223	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	9		T87	11		T218	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	4		T46	12		T53	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	4		T46	14		T39	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	11		T156	3		T218	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	9		T87	16		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	10		T207	3		T161	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	3		T156	6		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T157	9		T232	2		T233	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	8		T74	17		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T50	2		T161	10		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	10		T153	18		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T5	26		T15	7		T16	32
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T177	9		T157	14		T168	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23931

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3328

1

T1

3

T6

15

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21402

1

T1

3

T2

139

T3

20

auto[1]

5857

1

T5

29

T10

16

T13

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T189	1		T234	10		T235	1
values[0]	11	1			T222	1		T236	1		T237	1
values[1]	493	1			T13	10		T41	5		T165	1
values[2]	607	1			T148	10		T227	13		T223	33
values[3]	848	1			T10	11		T44	1		T165	1
values[4]	620	1			T13	18		T46	13		T53	19
values[5]	2882	1			T5	29		T12	13		T15	8
values[6]	752	1			T10	5		T14	10		T45	1
values[7]	734	1			T14	10		T148	7		T154	1
values[8]	707	1			T10	12		T41	15		T164	1
values[9]	1327	1			T1	3		T6	15		T13	16
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T13	10		T41	5		T165	1
values[1]	693	1			T10	11		T148	10		T149	2
values[2]	652	1			T13	18		T44	1		T165	1
values[3]	2821	1			T5	29		T15	8		T16	35
values[4]	794	1			T10	5		T12	13		T53	26
values[5]	714	1			T14	10		T45	1		T148	5
values[6]	705	1			T10	12		T14	10		T148	7
values[7]	717	1			T1	3		T13	16		T41	15
values[8]	962	1			T6	15		T44	1		T154	2
values[9]	243	1			T153	12		T107	2		T160	20
minimum	18285	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	4		T41	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T165	1		T227	13		T84	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T10	11		T148	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T149	1		T84	9		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	11		T44	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T165	1		T149	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T5	29		T15	8		T16	35
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T46	28		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	5		T53	16		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	10		T165	1		T84	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T14	10		T45	1		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T148	1		T151	13		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	10		T148	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	12		T156	4		T47	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T164	1		T150	1		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T13	9		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T44	1		T154	1		T74	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	5		T154	1		T156	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T160	1		T238	15		T114	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T153	12		T107	1		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18137	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T239	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	6		T41	4		T223	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T84	8		T207	2		T51	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T148	9		T167	1		T179	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T84	7		T17	8		T240	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	7		T104	11		T105	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T158	3		T208	7		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	865	1			T216	18		T217	24		T241	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T53	9		T177	9		T167	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T53	10		T158	10		T206	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	3		T84	11		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T145	8		T151	1		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T148	4		T151	11		T208	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T148	6		T161	12		T210	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T156	3		T47	2		T170	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	11		T39	2		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	2		T13	7		T41	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T74	20		T17	11		T105	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	10		T156	4		T168	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T160	19		T238	9		T114	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T107	1		T234	9		T242	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T189	1		T234	1		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T243	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T222	1		T236	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	4		T41	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T165	1		T207	4		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T148	1		T223	17		T167	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T227	13		T84	14		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T10	11		T44	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T165	1		T149	2		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	11		T145	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	13		T53	10		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T5	29		T15	8		T16	35
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	10		T46	15		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T10	5		T14	10		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T148	1		T151	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	10		T148	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T156	4		T17	9		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T164	1		T150	1		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	12		T41	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T44	1		T154	1		T74	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T1	1		T6	5		T13	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T234	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	6		T41	4		T219	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T207	2		T51	1		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T148	9		T223	16		T167	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T84	15		T17	8		T92	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T206	5		T170	9		T104	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T158	3		T208	7		T107	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T13	7		T158	10		T210	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T53	9		T84	11		T167	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T216	18		T217	24		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	3		T177	9		T208	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T53	10		T145	8		T151	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	4		T151	11		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T148	6		T214	3		T245	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T156	3		T17	7		T170	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T155	11		T39	2		T17	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	14		T158	11		T177	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T74	20		T17	3		T160	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T1	2		T6	10		T13	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1