Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23484

1

T1

3

T2

139

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3775

1

T10

17

T12

13

T13

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21170

1

T2

135

T3

20

T6

15

auto[1]

6089

1

T1

3

T2

4

T5

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	501	1			T2	4		T10	12		T12	2
values[0]	75	1			T53	19		T226	5		T193	6
values[1]	594	1			T13	18		T46	15		T53	26
values[2]	2939	1			T5	29		T10	11		T13	16
values[3]	528	1			T12	13		T13	10		T14	10
values[4]	746	1			T6	15		T165	1		T145	18
values[5]	698	1			T1	3		T10	5		T151	24
values[6]	825	1			T147	1		T158	11		T152	1
values[7]	668	1			T41	15		T165	1		T150	1
values[8]	494	1			T41	5		T165	1		T149	1
values[9]	1368	1			T45	1		T46	13		T148	7
minimum	17823	1			T2	135		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	853	1			T13	18		T14	10		T46	15
values[1]	2805	1			T5	29		T10	11		T13	16
values[2]	652	1			T12	13		T13	10		T44	2
values[3]	720	1			T6	15		T165	1		T154	1
values[4]	811	1			T1	3		T10	5		T147	1
values[5]	693	1			T165	1		T158	11		T152	1
values[6]	705	1			T41	20		T165	1		T149	1
values[7]	598	1			T173	1		T227	13		T157	10
values[8]	758	1			T10	12		T45	1		T46	13
values[9]	385	1			T17	29		T179	23		T170	27
minimum	18279	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	15		T164	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	11		T14	10		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T5	29		T10	11		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	9		T14	10		T53	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	4		T44	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	10		T44	1		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	5		T165	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T84	9		T251	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T147	1		T168	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	5		T151	13		T84	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T165	1		T152	1		T156	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T158	1		T223	8		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T165	1		T149	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	2		T90	1		T208	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T157	10		T153	19		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T173	1		T227	13		T180	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T46	13		T84	15		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	12		T45	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T17	17		T104	1		T118	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T17	1		T179	11		T170	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18130	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T250	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T148	4		T160	12		T226	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	7		T53	9		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	889	1			T216	18		T217	24		T241	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	7		T53	10		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	6		T158	11		T177	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	3		T145	8		T158	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	10		T177	9		T110	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T84	7		T168	10		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	2		T168	11		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T151	11		T84	8		T207	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T156	4		T167	7		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T158	10		T91	1		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T74	20		T215	8		T231	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T41	18		T208	21		T17	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T107	1		T269	11		T228	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T105	5		T240	10		T161	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T84	11		T39	2		T17	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T148	6		T223	16		T219	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T17	10		T104	1		T118	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T17	1		T179	12		T170	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T74	1		T39	5		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T250	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	471	1			T2	4		T12	2		T54	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T10	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T226	1		T311	1		T312	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T53	10		T193	1		T291	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	15		T164	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	11		T53	16		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T5	29		T10	11		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	9		T14	10		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	4		T44	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	10		T14	10		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	5		T165	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T145	10		T158	1		T84	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T17	7		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	5		T151	13		T84	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T147	1		T152	1		T156	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T158	1		T223	8		T179	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T165	1		T150	1		T74	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	1		T90	1		T208	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T165	1		T149	1		T153	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T41	1		T33	1		T180	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T46	13		T84	15		T157	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T45	1		T148	1		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17685	1			T2	135		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T104	1		T220	4		T295	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T226	4		T311	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T53	9		T193	5		T291	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T238	9		T279	16		T313	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	7		T53	10		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T148	4		T216	18		T217	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	7		T156	3		T17	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T13	6		T158	11		T177	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	3		T151	1		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	10		T177	9		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T145	8		T158	3		T84	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	2		T169	8		T206	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	11		T84	8		T207	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T156	4		T167	7		T168	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T158	10		T179	11		T105	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T74	20		T39	2		T226	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T41	14		T208	21		T17	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T215	8		T231	10		T269	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	4		T170	9		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T84	11		T39	2		T17	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T148	6		T223	16		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T46	1		T164	1		T148	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	8		T14	1		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T5	3		T10	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	8		T14	1		T53	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	7		T44	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	10		T44	1		T145	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	11		T165	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T84	8		T251	1		T168	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	3		T147	1		T168	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	1		T151	12		T84	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T165	1		T152	1		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T158	11		T223	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T165	1		T149	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T41	20		T90	1		T208	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T157	1		T153	1		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T173	1		T227	1		T180	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	1		T84	12		T39	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	1		T45	1		T148	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T17	12		T104	2		T118	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T17	2		T179	13		T170	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18269	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T250	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T46	14		T18	3		T238	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	10		T14	9		T53	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T5	26		T10	10		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	8		T14	9		T53	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	3		T17	3		T206	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	3		T145	9		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	4		T177	9		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T84	8		T161	7		T95	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T168	9		T49	2		T255	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	4		T151	12		T84	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T156	6		T17	6		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T223	7		T307	9		T91	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T74	17		T87	11		T215	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T208	22		T17	8		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T157	9		T153	18		T40	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T227	12		T180	15		T240	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	12		T84	14		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	11		T223	16		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T17	15		T118	4		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T179	10		T170	13		T107	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	464	1			T2	4		T12	2		T54	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T10	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T226	5		T311	4		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T53	10		T193	6		T291	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	1		T164	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	8		T53	11		T148	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T5	3		T10	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	8		T14	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	7		T44	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	10		T14	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	11		T165	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T145	9		T158	4		T84	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	3		T17	1		T169	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T151	12		T84	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T147	1		T152	1		T156	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T158	11		T223	1		T179	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T165	1		T150	1		T74	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T41	15		T90	1		T208	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T165	1		T149	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	5		T33	1		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T46	1		T84	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	472	1			T45	1		T148	7		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17823	1			T2	135		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T220	14		T295	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T10	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T312	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T53	9		T291	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T46	14		T238	14		T279	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	10		T53	15		T171	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T5	26		T10	10		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	8		T14	9		T156	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T13	3		T17	3		T206	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	3		T14	9		T155	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	4		T177	9		T49	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T145	9		T84	8		T104	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	6		T51	2		T255	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	4		T151	12		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T156	6		T168	9		T100	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T223	7		T179	11		T105	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T74	17		T87	11		T285	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T208	22		T17	8		T219	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T153	18		T40	2		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T180	15		T240	9		T161	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T46	12		T84	14		T157	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T227	12		T223	16		T153	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25