Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23335

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3924

1

T1

3

T10

23

T12

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21223

1

T2

139

T3

20

T7

11

auto[1]

6036

1

T1

3

T5

29

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	234	1			T155	25		T177	2		T156	11
values[0]	23	1			T161	22		T314	1		-	-
values[1]	753	1			T1	3		T6	15		T148	5
values[2]	710	1			T10	12		T13	16		T46	15
values[3]	785	1			T13	10		T44	1		T165	1
values[4]	660	1			T12	13		T148	10		T149	1
values[5]	2815	1			T5	29		T10	5		T15	8
values[6]	651	1			T45	1		T147	1		T152	1
values[7]	789	1			T14	10		T165	1		T223	33
values[8]	597	1			T41	5		T44	1		T145	1
values[9]	976	1			T10	11		T13	18		T14	10
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	761	1			T1	3		T6	15		T145	18
values[1]	778	1			T10	12		T13	16		T46	15
values[2]	671	1			T13	10		T44	1		T149	1
values[3]	2879	1			T5	29		T12	13		T15	8
values[4]	612	1			T10	5		T53	26		T149	1
values[5]	668	1			T45	1		T147	1		T152	1
values[6]	848	1			T14	10		T41	5		T44	1
values[7]	527	1			T14	10		T145	1		T158	12
values[8]	936	1			T10	11		T13	18		T53	19
values[9]	127	1			T164	1		T148	7		T179	23
minimum	18452	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	5		T209	1		T104	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T1	1		T145	10		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T46	15		T165	1		T208	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	12		T13	9		T84	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	1		T150	2		T84	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	4		T149	1		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T5	29		T15	8		T16	35
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	10		T41	1		T46	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	5		T149	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T53	16		T173	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T45	1		T167	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	1		T152	1		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	10		T41	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T74	18		T251	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	10		T158	1		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T145	1		T152	1		T315	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	11		T53	10		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T10	11		T165	1		T87	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T164	1		T148	1		T179	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T160	1		T316	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18170	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T18	4		T105	6		T161	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	10		T104	11		T110	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	2		T145	8		T167	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T208	7		T17	10		T50	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	7		T84	7		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T84	11		T208	14		T219	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	6		T151	11		T84	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	849	1			T158	10		T216	18		T217	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	3		T41	14		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T210	7		T264	15		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T53	10		T158	3		T17	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T167	7		T168	10		T265	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T177	9		T207	2		T170	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	4		T223	16		T214	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T74	20		T47	2		T170	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T158	11		T39	2		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T170	9		T49	3		T215	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	7		T53	9		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T169	8		T206	1		T104	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T148	6		T179	11		T317	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T160	9		T316	15		T266	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T148	4		T74	1		T151	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T105	4		T161	11		T229	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T155	14		T177	1		T156	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T169	1		T240	10		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T161	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	5		T148	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T145	10		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T46	15		T208	8		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	12		T13	9		T84	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	1		T165	1		T150	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	4		T149	1		T151	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T149	1		T158	1		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	10		T148	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T5	29		T10	5		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T41	1		T46	13		T53	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T45	1		T167	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T147	1		T152	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	10		T165	1		T223	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T251	1		T205	1		T47	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T41	1		T44	1		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T145	1		T74	18		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	11		T14	10		T53	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T10	11		T165	1		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T155	11		T177	1		T156	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T169	8		T240	10		T305	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T161	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	10		T148	4		T151	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	2		T145	8		T167	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T208	7		T17	10		T50	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	7		T84	7		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T84	11		T208	14		T219	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	6		T151	11		T84	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T158	10		T108	4		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	3		T148	9		T17	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	841	1			T216	18		T217	24		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	14		T53	10		T158	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T167	7		T168	10		T265	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T177	9		T207	2		T107	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T223	16		T214	3		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	2		T170	28		T108	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T41	4		T39	2		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T74	20		T170	9		T49	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	7		T53	9		T148	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T206	1		T104	10		T160	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	11		T209	1		T104	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	3		T145	9		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T46	1		T165	1		T208	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	1		T13	8		T84	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	1		T150	2		T84	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	7		T149	1		T151	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T5	3		T15	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T12	10		T41	15		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	1		T149	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T53	11		T173	1		T158	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T45	1		T167	8		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T147	1		T152	1		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	1		T41	5		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T74	21		T251	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T158	12		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T145	1		T152	1		T315	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	8		T53	10		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	1		T165	1		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T164	1		T148	7		T179	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T160	10		T316	16		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18347	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T18	1		T105	5		T161	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T6	4		T104	10		T118	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T145	9		T223	7		T87	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T46	14		T208	7		T17	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	11		T13	8		T84	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T84	14		T157	14		T208	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	3		T151	12		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T5	26		T15	7		T16	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	3		T46	12		T17	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T10	4		T210	9		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T53	15		T153	18		T17	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T180	15		T265	2		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T177	9		T207	3		T170	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	9		T223	16		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T74	17		T269	7		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T14	9		T40	2		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T49	2		T215	13		T270	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	10		T53	9		T155	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T10	10		T87	16		T104	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T179	11		T271	19		T317	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T266	10		T267	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T117	7		T182	12		T301	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T18	3		T105	5		T161	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T155	12		T177	2		T156	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T169	9		T240	11		T305	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T161	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	11		T148	5		T151	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	3		T145	9		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T46	1		T208	8		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T13	8		T84	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T44	1		T165	1		T150	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	7		T149	1		T151	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T149	1		T158	11		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	10		T148	10		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T5	3		T10	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T41	15		T46	1		T53	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	1		T167	8		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T147	1		T152	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	1		T165	1		T223	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T251	1		T205	1		T47	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	5		T44	1		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T145	1		T74	21		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	8		T14	1		T53	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T10	1		T165	1		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T155	13		T156	6		T179	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T240	9		T185	11		T318	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T161	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	4		T104	10		T117	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T145	9		T223	7		T87	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	14		T208	7		T17	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	11		T13	8		T84	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T84	14		T157	14		T208	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	3		T151	12		T84	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T108	2		T218	11		T319	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	3		T17	9		T218	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T5	26		T10	4		T15	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	12		T53	15		T153	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T180	15		T265	2		T98	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T177	9		T207	3		T107	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	9		T223	16		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T170	13		T108	7		T272	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T40	2		T42	2		T260	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T74	17		T49	2		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	10		T14	9		T53	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T10	10		T87	16		T104	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25