Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23937

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3322

1

T1

3

T10

16

T12

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21708

1

T1

3

T2

139

T3

20

auto[1]

5551

1

T5

29

T10

12

T12

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	302	1			T177	21		T167	2		T39	4
values[0]	37	1			T182	14		T320	2		T204	13
values[1]	687	1			T148	10		T149	1		T150	1
values[2]	561	1			T147	1		T151	2		T84	13
values[3]	702	1			T13	10		T14	10		T41	15
values[4]	687	1			T1	3		T6	15		T10	5
values[5]	843	1			T10	12		T12	13		T14	10
values[6]	677	1			T13	18		T173	2		T158	12
values[7]	749	1			T13	16		T74	38		T152	1
values[8]	597	1			T10	11		T44	1		T148	12
values[9]	3151	1			T5	29		T15	8		T16	35
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	574	1			T147	1		T148	10		T150	1
values[1]	737	1			T158	11		T151	2		T84	13
values[2]	631	1			T6	15		T13	10		T14	10
values[3]	717	1			T1	3		T10	17		T14	10
values[4]	792	1			T12	13		T41	5		T53	19
values[5]	755	1			T13	34		T173	1		T158	12
values[6]	2731	1			T5	29		T15	8		T16	35
values[7]	794	1			T10	11		T44	2		T148	12
values[8]	986	1			T45	1		T53	26		T164	1
values[9]	56	1			T177	2		T90	1		T167	2
minimum	18486	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	1		T150	1		T151	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T148	1		T227	13		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T205	1		T17	1		T42	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T158	1		T151	1		T84	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	5		T13	4		T154	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	10		T41	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T10	12		T46	28		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T10	5		T14	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T41	1		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	10		T165	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	11		T173	1		T157	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	9		T158	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T5	29		T15	8		T16	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T208	8		T209	1		T210	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T17	22		T32	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	11		T44	2		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T45	1		T53	16		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T154	1		T177	10		T157	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T177	1		T90	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T211	1		T212	8		T22	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18192	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T149	1		T277	1		T182	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T151	11		T206	1		T213	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T148	9		T17	1		T170	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T42	1		T104	12		T161	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T158	10		T151	1		T84	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	10		T13	6		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T41	14		T39	2		T169	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T145	8		T158	3		T208	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	2		T17	15		T110	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T41	4		T53	9		T207	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	3		T169	7		T160	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	7		T161	2		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	7		T158	11		T74	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T216	18		T217	24		T241	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T208	7		T210	1		T91	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T17	13		T108	9		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T148	10		T219	9		T179	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T53	10		T84	7		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T177	9		T168	11		T179	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T177	1		T167	1		T203	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T22	1		T242	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T74	1		T39	5		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T277	10		T182	8		T320	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T177	1		T167	1		T39	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T177	10		T168	10		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T221	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T182	6		T320	1		T204	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T150	1		T151	13		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T148	1		T149	1		T227	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T147	1		T205	1		T17	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T151	1		T84	5		T248	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T13	4		T145	10		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	10		T41	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	5		T46	28		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	1		T10	5		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	12		T41	1		T53	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	10		T14	10		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	11		T173	2		T207	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T158	1		T150	1		T156	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T157	10		T224	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	9		T74	18		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	5		T32	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	11		T44	1		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T5	29		T15	8		T16	35
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T44	1		T154	1		T157	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T177	1		T167	1		T39	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T177	9		T168	11		T231	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T221	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T182	8		T320	1		T204	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	11		T105	11		T213	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T148	9		T17	1		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T42	1		T206	1		T104	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T151	1		T84	8		T248	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	6		T145	8		T223	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T41	14		T158	10		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	10		T158	3		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	2		T39	2		T17	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	4		T53	9		T156	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	3		T17	7		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	7		T207	2		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T158	11		T156	4		T104	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	14		T195	13		T274	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	7		T74	20		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	3		T225	9		T50	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T148	10		T219	9		T179	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T53	10		T216	18		T84	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T170	9		T49	3		T107	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T147	1		T150	1		T151	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T148	10		T227	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T205	1		T17	1		T42	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T158	11		T151	2		T84	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	11		T13	7		T154	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	1		T41	15		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	1		T46	2		T145	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	3		T10	1		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T41	5		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	10		T165	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	8		T173	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	8		T158	12		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T5	3		T15	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T208	8		T209	1		T210	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T17	17		T32	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	1		T44	2		T148	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T45	1		T53	11		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T154	1		T177	10		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T177	2		T90	1		T167	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T211	1		T212	1		T22	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18356	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T149	1		T277	11		T182	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	12		T17	6		T213	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T227	12		T170	13		T52	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	2		T104	10		T161	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T84	4		T218	8		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	4		T13	3		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	9		T87	11		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	11		T46	26		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	4		T14	9		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T53	9		T207	3		T156	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	3		T87	16		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	10		T157	9		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	8		T74	17		T156	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T5	26		T15	7		T16	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T208	7		T210	1		T91	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	18		T180	15		T108	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	10		T153	18		T219	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T53	15		T84	8		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T177	9		T157	14		T168	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T212	7		T22	1		T242	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T105	20		T231	9		T279	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T182	5		T321	13		T312	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T177	2		T167	2		T39	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T177	10		T168	12		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T221	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T182	9		T320	2		T204	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T150	1		T151	12		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T148	10		T149	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T147	1		T205	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T151	2		T84	9		T248	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	7		T145	9		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T41	15		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	11		T46	2		T158	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	3		T10	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	1		T41	5		T53	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	10		T14	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	8		T173	2		T207	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T158	12		T150	1		T156	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T157	1		T224	1		T37	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	8		T74	21		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T17	5		T32	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	1		T44	1		T148	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T5	3		T15	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T44	1		T154	1		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T219	13		T184	10		T248	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T177	9		T168	9		T231	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T182	5		T204	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	12		T105	20		T213	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T227	12		T170	13		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	6		T42	2		T104	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T84	4		T248	18		T238	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	3		T145	9		T223	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	9		T87	11		T218	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	4		T46	26		T155	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T10	4		T39	3		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	11		T53	9		T156	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	3		T14	9		T87	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	10		T207	3		T161	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T156	6		T18	3		T104	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T157	9		T233	19		T195	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	8		T74	17		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T17	3		T50	2		T161	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	10		T153	18		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T5	26		T15	7		T16	32
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T157	14		T49	2		T108	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25