Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23520

1

T1

3

T2

139

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3739

1

T10

28

T12

13

T13

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21058

1

T2

135

T3

20

T6

15

auto[1]

6201

1

T1

3

T2

4

T5

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	778	1			T2	4		T10	12		T12	2
values[0]	31	1			T53	19		T322	1		T226	5
values[1]	600	1			T13	18		T14	10		T46	15
values[2]	2964	1			T5	29		T10	11		T13	16
values[3]	529	1			T12	13		T13	10		T14	10
values[4]	715	1			T6	15		T165	1		T145	18
values[5]	763	1			T1	3		T10	5		T151	24
values[6]	778	1			T147	1		T158	11		T152	1
values[7]	677	1			T41	20		T165	1		T149	1
values[8]	540	1			T165	1		T227	13		T153	19
values[9]	1061	1			T45	1		T46	13		T148	7
minimum	17823	1			T2	135		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T13	18		T14	10		T53	19
values[1]	2779	1			T5	29		T10	11		T12	13
values[2]	566	1			T13	10		T44	1		T145	19
values[3]	746	1			T6	15		T165	1		T154	1
values[4]	795	1			T1	3		T10	5		T147	1
values[5]	699	1			T165	1		T158	11		T152	1
values[6]	653	1			T41	20		T165	1		T149	1
values[7]	634	1			T173	1		T227	13		T157	10
values[8]	906	1			T45	1		T46	13		T148	7
values[9]	253	1			T10	12		T179	23		T170	27
minimum	18443	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T53	10		T148	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	11		T14	10		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T5	29		T13	9		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	11		T12	10		T14	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	4		T44	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T145	10		T158	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	5		T165	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T177	10		T255	1		T98	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T151	13		T207	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T10	5		T147	1		T84	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T165	1		T87	12		T156	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T158	1		T152	1		T223	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T165	1		T149	1		T74	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T41	2		T150	1		T208	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T227	13		T224	1		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T173	1		T157	10		T153	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T46	13		T152	1		T223	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T45	1		T148	1		T17	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T107	9		T218	1		T186	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T10	12		T179	11		T170	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18170	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T148	1		T171	8		T170	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T53	9		T148	4		T160	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	7		T17	8		T213	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T13	7		T216	18		T217	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	3		T53	10		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	6		T158	11		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	8		T158	3		T151	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	10		T84	7		T110	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T177	9		T255	9		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	2		T151	11		T207	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T84	8		T169	15		T179	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T156	4		T167	7		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T158	10		T52	2		T91	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T74	20		T215	8		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T41	18		T208	21		T17	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T105	5		T107	1		T323	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T170	9		T240	10		T161	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T223	16		T84	11		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T148	6		T17	10		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T107	14		T218	10		T186	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T179	12		T170	13		T159	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T74	1		T39	5		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T148	9		T170	15		T210	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	496	1			T2	4		T12	2		T54	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	12		T17	2		T170	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T53	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T322	1		T226	1		T193	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	15		T164	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	11		T14	10		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T5	29		T13	9		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T10	11		T44	1		T53	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	4		T44	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	10		T14	10		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	5		T165	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T145	10		T158	1		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	1		T151	13		T207	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	5		T84	5		T157	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T156	7		T167	1		T168	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T147	1		T158	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	1		T149	1		T74	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	2		T150	1		T208	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T165	1		T227	13		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T153	19		T180	16		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T46	13		T223	17		T84	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T45	1		T148	1		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17685	1			T2	135		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T219	8		T107	14		T108	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T170	13		T159	10		T248	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T53	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T226	4		T193	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T264	15		T238	9		T311	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	7		T148	9		T170	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T13	7		T148	4		T216	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T53	10		T156	3		T17	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	6		T158	11		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	3		T151	1		T167	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	10		T84	7		T218	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	8		T158	3		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	2		T151	11		T207	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T84	8		T169	15		T206	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T156	4		T167	7		T168	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	10		T179	11		T52	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T74	20		T39	2		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	18		T208	21		T17	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T105	5		T214	3		T323	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T170	9		T240	10		T161	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T223	16		T84	11		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T148	6		T17	10		T179	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T53	10		T148	5		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	8		T14	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T5	3		T13	8		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T12	10		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	7		T44	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T145	9		T158	4		T151	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	11		T165	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T177	10		T255	10		T98	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	3		T151	12		T207	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	1		T147	1		T84	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T165	1		T87	1		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T158	11		T152	1		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	1		T149	1		T74	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T41	20		T150	1		T208	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T227	1		T224	1		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T173	1		T157	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	1		T152	1		T223	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T45	1		T148	7		T17	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T107	15		T218	11		T186	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T10	1		T179	13		T170	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18300	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T148	10		T171	1		T170	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T53	9		T18	3		T270	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	10		T14	9		T17	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T5	26		T13	8		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	10		T12	3		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	3		T155	13		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T145	9		T104	14		T105	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	4		T84	8		T161	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T177	9		T98	11		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T151	12		T207	3		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	4		T84	4		T157	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T87	11		T156	6		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T223	7		T52	2		T91	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T74	17		T215	10		T214	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T208	22		T17	8		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T227	12		T40	2		T231	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T157	9		T153	18		T180	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T46	12		T223	16		T84	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	15		T210	1		T100	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T107	8		T186	2		T204	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T10	11		T179	10		T170	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T46	14		T187	2		T188	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T171	7		T210	9		T279	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	494	1			T2	4		T12	2		T54	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	1		T17	2		T170	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T53	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T322	1		T226	5		T193	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	1		T164	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	8		T14	1		T148	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T5	3		T13	8		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	1		T44	1		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	7		T44	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	10		T14	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	11		T165	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T145	9		T158	4		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	3		T151	12		T207	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T10	1		T84	9		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T156	5		T167	8		T168	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T147	1		T158	11		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T165	1		T149	1		T74	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T41	20		T150	1		T208	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T165	1		T227	1		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T153	1		T180	1		T170	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T46	1		T223	17		T84	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T45	1		T148	7		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17823	1			T2	135		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T219	13		T107	8		T108	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	11		T170	13		T248	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T53	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T46	14		T238	14		T195	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	10		T14	9		T171	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T5	26		T13	8		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	10		T53	15		T156	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	3		T155	13		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	3		T14	9		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	4		T84	8		T218	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T145	9		T177	9		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T151	12		T207	3		T51	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	4		T84	4		T157	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T156	6		T168	9		T94	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T223	7		T179	11		T52	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T74	17		T87	11		T307	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T208	22		T17	8		T219	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T227	12		T40	2		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T153	18		T180	15		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T46	12		T223	16		T84	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T157	9		T17	15		T179	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25