Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23773

1

T1

3

T2

139

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3486

1

T10

5

T12

13

T13

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21236

1

T2

139

T3

20

T7

11

auto[1]

6023

1

T1

3

T5

29

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	277	1			T154	1		T151	2		T153	19
values[0]	28	1			T167	1		T269	2		T325	13
values[1]	798	1			T1	3		T12	13		T14	10
values[2]	2807	1			T5	29		T10	11		T15	8
values[3]	710	1			T45	1		T53	19		T165	1
values[4]	768	1			T6	15		T44	1		T46	13
values[5]	735	1			T14	10		T41	5		T46	15
values[6]	513	1			T10	12		T13	10		T165	1
values[7]	553	1			T13	16		T148	10		T149	1
values[8]	697	1			T10	5		T13	18		T147	1
values[9]	1107	1			T44	1		T164	1		T148	7
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T1	3		T14	10		T148	5
values[1]	2873	1			T5	29		T10	11		T15	8
values[2]	601	1			T44	1		T45	1		T53	19
values[3]	832	1			T6	15		T14	10		T46	13
values[4]	687	1			T41	5		T46	15		T165	1
values[5]	614	1			T10	12		T13	10		T149	1
values[6]	542	1			T13	16		T147	1		T148	10
values[7]	778	1			T10	5		T13	18		T145	18
values[8]	1028	1			T44	1		T164	1		T148	7
values[9]	81	1			T173	1		T48	11		T52	6
minimum	18550	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T14	10		T156	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T148	1		T165	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T5	29		T10	11		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T53	16		T40	5		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T44	1		T45	1		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T154	1		T84	15		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	5		T14	10		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T46	13		T149	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T165	1		T167	1		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	1		T46	15		T17	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	12		T149	1		T155	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	4		T151	13		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	9		T147	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T148	1		T145	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	11		T158	1		T208	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T10	5		T145	10		T150	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T44	1		T164	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T148	1		T151	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T173	1		T48	6		T52	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T290	14		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18191	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	10		T152	1		T17	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	2		T156	3		T210	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T148	4		T39	2		T169	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T41	14		T216	18		T217	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	10		T169	3		T179	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T53	9		T168	10		T108	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T84	11		T214	3		T245	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	10		T158	11		T104	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	1		T50	3		T213	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T167	7		T39	2		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T41	4		T17	8		T105	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T155	11		T17	10		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	6		T151	11		T177	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	7		T84	8		T207	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T148	9		T158	10		T84	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	7		T158	3		T208	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T145	8		T177	9		T105	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T74	20		T223	16		T219	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T148	6		T151	1		T208	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T48	5		T52	2		T203	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T74	1		T39	5		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T12	3		T17	8		T179	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T154	1		T18	4		T49	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T151	1		T153	19		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T167	1		T295	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T269	1		T325	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T14	10		T156	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T12	10		T148	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T5	29		T10	11		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	16		T40	5		T169	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T45	1		T53	10		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T84	15		T183	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	5		T44	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T46	13		T149	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	10		T167	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	1		T46	15		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	12		T165	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	4		T151	13		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	9		T149	1		T84	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T148	1		T152	1		T223	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	11		T147	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	5		T145	11		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T44	1		T164	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T148	1		T227	13		T177	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T49	3		T160	9		T52	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T151	1		T277	10		T324	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T295	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T269	1		T325	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T1	2		T156	3		T206	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	3		T148	4		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T41	14		T216	18		T217	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T53	10		T169	11		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T53	9		T17	7		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T84	11		T214	3		T264	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	10		T158	11		T104	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	1		T215	8		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T167	7		T39	2		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	4		T17	8		T50	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T155	11		T47	2		T206	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	6		T151	11		T105	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	7		T84	8		T207	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T148	9		T177	1		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	7		T158	3		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T145	8		T158	10		T84	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T74	20		T223	16		T219	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T148	6		T177	9		T208	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	3		T14	1		T156	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T148	5		T165	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T5	3		T10	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T53	11		T40	3		T169	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	1		T45	1		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T154	1		T84	12		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	11		T14	1		T158	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T46	1		T149	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T165	1		T167	8		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T41	5		T46	1		T17	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	1		T149	1		T155	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	7		T151	12		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	8		T147	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T148	10		T145	1		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	8		T158	4		T208	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	1		T145	9		T150	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T44	1		T164	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T148	7		T151	2		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T173	1		T48	8		T52	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T290	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18313	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T12	10		T152	1		T17	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	9		T156	3		T210	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T157	14		T39	3		T107	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T5	26		T10	10		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	15		T40	2		T179	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T53	9		T108	13		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T84	14		T214	9		T326	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	4		T14	9		T87	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	12		T42	2		T50	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T153	11		T17	9		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	14		T17	6		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	11		T155	13		T17	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	3		T151	12		T156	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	8		T84	4		T207	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T223	7		T84	8		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	10		T208	7		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	4		T145	9		T227	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T74	17		T223	16		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T208	15		T153	18		T168	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T48	3		T52	2		T22	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T290	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T296	15		T118	3		T290	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	3		T17	8		T179	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T154	1		T18	1		T49	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T151	2		T153	1		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T167	1		T295	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T269	2		T325	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	3		T14	1		T156	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	10		T148	5		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T5	3		T10	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T53	11		T40	3		T169	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T45	1		T53	10		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T84	12		T183	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	11		T44	1		T158	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T46	1		T149	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	1		T167	8		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T41	5		T46	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	1		T165	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	7		T151	12		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	8		T149	1		T84	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T148	10		T152	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	8		T147	1		T158	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	1		T145	10		T158	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T44	1		T164	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T148	7		T227	1		T177	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T18	3		T49	2		T52	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T153	18		T324	9		T327	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T295	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T325	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	9		T156	3		T210	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	3		T157	14		T39	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T5	26		T10	10		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T53	15		T40	2		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T53	9		T17	8		T108	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T84	14		T214	9		T328	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	4		T87	16		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	12		T42	2		T215	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	9		T153	11		T17	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	14		T17	6		T50	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T10	11		T155	13		T206	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	3		T151	12		T105	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	8		T84	4		T207	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T223	7		T156	6		T297	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	10		T208	7		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	4		T145	9		T84	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T74	17		T223	16		T219	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T227	12		T177	9		T208	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25