Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21842

1

T1

3

T2

139

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

5417

1

T5

29

T6

15

T13

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21345

1

T1

3

T2

139

T3

20

auto[1]

5914

1

T5

29

T6

15

T10

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	188	1			T1	3		T13	10		T154	1
values[0]	34	1			T17	17		T232	17		-	-
values[1]	956	1			T10	11		T12	13		T46	15
values[2]	581	1			T44	1		T167	1		T208	30
values[3]	475	1			T10	5		T44	1		T46	13
values[4]	813	1			T145	18		T74	38		T151	24
values[5]	512	1			T13	16		T147	1		T148	7
values[6]	877	1			T177	2		T84	16		T87	29
values[7]	621	1			T6	15		T10	12		T173	1
values[8]	658	1			T14	10		T165	1		T145	1
values[9]	3278	1			T5	29		T13	18		T14	10
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	905	1			T46	15		T164	1		T173	1
values[1]	2644	1			T5	29		T15	8		T16	35
values[2]	507	1			T10	5		T44	1		T46	13
values[3]	797	1			T147	1		T150	1		T154	1
values[4]	635	1			T13	16		T148	7		T150	1
values[5]	829	1			T6	15		T10	12		T177	2
values[6]	638	1			T145	1		T149	2		T173	1
values[7]	569	1			T14	10		T165	1		T227	13
values[8]	1053	1			T13	10		T41	20		T45	1
values[9]	146	1			T1	3		T13	18		T14	10
minimum	18536	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T164	1		T158	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T46	15		T173	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T44	1		T208	16		T17	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1516	1			T5	29		T15	8		T16	35
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	5		T149	1		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T44	1		T46	13		T148	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T156	7		T167	1		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T147	1		T150	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T150	1		T33	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	9		T148	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	12		T177	1		T84	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	5		T39	6		T168	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T145	1		T149	1		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T149	1		T173	1		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T165	1		T227	13		T207	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	10		T84	15		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T13	4		T41	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T41	1		T165	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T1	1		T13	11		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T14	10		T33	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18227	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T167	1		T17	9		T51	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T158	10		T223	16		T168	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T158	11		T17	1		T107	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T208	14		T17	8		T169	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	859	1			T216	18		T217	24		T241	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T177	9		T219	9		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T148	13		T145	8		T206	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T156	4		T167	7		T208	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T74	20		T151	11		T84	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T170	15		T110	5		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	7		T148	6		T179	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T177	1		T84	7		T95	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	10		T39	4		T168	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T206	1		T50	3		T108	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T155	11		T17	10		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T207	2		T17	7		T104	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T84	11		T218	10		T253	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	6		T41	14		T158	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T41	4		T151	1		T160	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T1	2		T13	7		T255	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T256	2		T249	1		T257	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	3		T53	19		T74	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T167	1		T17	8		T51	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T1	1		T13	4		T154	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T319	3		T256	1		T300	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T232	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T17	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T10	11		T12	10		T53	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T46	15		T173	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	1		T167	1		T208	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	5		T105	1		T161	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	5		T149	1		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	1		T46	13		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T167	1		T208	8		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T145	10		T74	18		T151	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T150	1		T156	7		T218	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	9		T147	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T177	1		T84	9		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T87	29		T39	6		T168	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	12		T205	1		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	5		T173	1		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T165	1		T145	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	10		T149	1		T84	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T13	11		T41	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1658	1			T5	29		T14	10		T15	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T1	2		T13	6		T231	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T319	4		T256	2		T300	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T232	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T17	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	3		T53	19		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T158	11		T167	1		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T208	14		T17	8		T169	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	3		T105	5		T161	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T177	9		T108	13		T329	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T148	13		T206	5		T48	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T167	7		T208	7		T219	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T145	8		T74	20		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T156	4		T218	10		T94	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	7		T148	6		T84	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T177	1		T84	7		T170	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T39	4		T168	11		T49	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T206	1		T50	3		T108	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	10		T155	11		T17	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T207	2		T17	7		T104	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T84	11		T160	9		T218	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T13	7		T41	14		T158	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	988	1			T41	4		T216	18		T151	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T164	1		T158	11		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T46	1		T173	1		T158	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	1		T208	15		T17	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1195	1			T5	3		T15	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	1		T149	1		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T44	1		T46	1		T148	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T156	5		T167	8		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	1		T150	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T150	1		T33	1		T170	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	8		T148	7		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	1		T177	2		T84	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T6	11		T39	7		T168	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T145	1		T149	1		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T149	1		T173	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T165	1		T227	1		T207	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T14	1		T84	12		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T13	7		T41	15		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T41	5		T165	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T1	3		T13	8		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T14	1		T33	1		T256	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18344	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T167	2		T17	9		T51	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T223	16		T17	6		T42	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T46	14		T153	18		T215	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T208	15		T17	6		T161	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1180	1			T5	26		T15	7		T16	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	4		T177	9		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T46	12		T145	9		T206	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T156	6		T208	7		T171	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T74	17		T151	12		T223	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T218	11		T100	2		T202	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	8		T87	27		T179	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	11		T84	8		T95	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	4		T39	3		T168	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T50	2		T108	7		T111	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T155	13		T17	15		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T227	12		T207	3		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T14	9		T84	14		T98	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	3		T156	3		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T157	14		T153	11		T185	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T13	10		T231	9		T266	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T14	9		T249	2		T229	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T10	10		T12	3		T53	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T17	8		T51	1		T231	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T1	3		T13	7		T154	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T319	5		T256	3		T300	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T232	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T17	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T10	1		T12	10		T53	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T46	1		T173	1		T158	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T44	1		T167	1		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	5		T105	6		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T10	1		T149	1		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	1		T46	1		T148	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T167	8		T208	8		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T145	9		T74	21		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T150	1		T156	5		T218	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	8		T147	1		T148	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T177	2		T84	8		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T87	2		T39	7		T168	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	1		T205	1		T206	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	11		T173	1		T155	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T165	1		T145	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	1		T149	1		T84	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T13	8		T41	15		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1350	1			T5	3		T14	1		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T13	3		T231	9		T20	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T319	2		T300	12		T299	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T232	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T17	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	10		T12	3		T53	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T46	14		T153	18		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T208	15		T17	6		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T17	3		T161	10		T307	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	4		T177	9		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T46	12		T206	4		T48	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T208	7		T171	7		T219	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T145	9		T74	17		T151	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T156	6		T218	11		T94	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T13	8		T84	4		T179	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T84	8		T111	6		T214	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T87	27		T39	3		T168	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	11		T50	2		T108	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	4		T155	13		T17	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T227	12		T207	3		T157	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T14	9		T84	14		T98	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	10		T156	3		T219	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1296	1			T5	26		T14	9		T15	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25