Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	7		T41	5		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T165	1		T227	1		T84	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	1		T148	10		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T149	1		T84	8		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	8		T44	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T165	1		T149	1		T158	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T5	3		T15	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	2		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	1		T53	11		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	10		T165	1		T84	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	1		T45	1		T145	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T148	5		T151	12		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T148	7		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	1		T156	4		T47	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T164	1		T150	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	3		T13	8		T41	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T44	1		T154	1		T74	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	11		T154	1		T156	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T160	20		T238	10		T114	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T153	1		T107	2		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18268	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T239	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	3		T223	16		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T227	12		T84	4		T207	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	10		T179	11		T206	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T84	8		T17	6		T240	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	10		T104	14		T218	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T208	7		T168	9		T107	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T5	26		T15	7		T16	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T46	26		T53	9		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	4		T53	15		T87	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	3		T84	14		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	9		T145	9		T223	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T151	12		T208	15		T17	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	9		T171	7		T161	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	11		T156	3		T105	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T155	13		T101	14		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	8		T17	15		T184	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T74	17		T87	16		T17	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	4		T156	6		T179	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T238	14		T114	4		T188	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T153	11		T247	2		T242	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T243	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T239	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T189	1		T234	10		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T243	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T222	1		T236	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	7		T41	5		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T165	1		T207	3		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T148	10		T223	17		T167	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T227	1		T84	17		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T10	1		T44	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T165	1		T149	2		T158	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	8		T145	1		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	1		T53	10		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T5	3		T15	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	10		T46	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T10	1		T14	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T148	5		T151	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T148	7		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T156	4		T17	8		T170	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T164	1		T150	1		T155	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	1		T41	15		T158	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T44	1		T154	1		T74	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T1	3		T6	11		T13	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T243	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	3		T219	9		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T207	3		T51	1		T248	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T223	16		T40	2		T179	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T227	12		T84	12		T17	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	10		T153	18		T206	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T157	14		T208	7		T107	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	10		T180	15		T210	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T46	12		T53	9		T84	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T5	26		T15	7		T16	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	3		T46	14		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	4		T14	9		T53	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T151	12		T49	2		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	9		T171	7		T214	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	3		T17	8		T108	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	13		T17	8		T105	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	11		T105	20		T184	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T74	17		T87	16		T17	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	4		T13	8		T156	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25