Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21813

1

T1

3

T2

139

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

5446

1

T5

29

T13

16

T14

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21382

1

T1

3

T2

139

T3

20

auto[1]

5877

1

T5

29

T6

15

T10

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T191	1		T249	4		T250	14
values[0]	57	1			T17	17		T105	10		T232	17
values[1]	938	1			T10	11		T12	13		T46	15
values[2]	579	1			T44	1		T158	11		T167	1
values[3]	484	1			T10	5		T44	1		T148	5
values[4]	796	1			T46	13		T148	10		T145	18
values[5]	509	1			T13	16		T147	1		T148	7
values[6]	870	1			T177	2		T84	16		T87	29
values[7]	613	1			T6	15		T10	12		T165	1
values[8]	652	1			T14	10		T145	1		T149	2
values[9]	3476	1			T1	3		T5	29		T13	28
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1181	1			T10	11		T12	13		T46	15
values[1]	2640	1			T5	29		T15	8		T16	35
values[2]	514	1			T10	5		T44	1		T46	13
values[3]	798	1			T147	1		T150	2		T154	1
values[4]	601	1			T13	16		T148	7		T152	1
values[5]	804	1			T10	12		T177	2		T251	1
values[6]	649	1			T6	15		T145	1		T149	2
values[7]	570	1			T14	10		T165	1		T227	13
values[8]	1022	1			T13	10		T41	20		T45	1
values[9]	199	1			T1	3		T13	18		T14	10
minimum	18281	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T10	11		T12	10		T53	26
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T46	15		T173	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T44	1		T149	1		T208	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1499	1			T5	29		T15	8		T16	35
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	5		T177	10		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T44	1		T46	13		T148	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T150	1		T156	7		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	1		T150	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T84	9		T209	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	9		T148	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	12		T177	1		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T39	6		T168	10		T49	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	5		T145	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T149	1		T173	1		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T165	1		T227	13		T207	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	10		T84	15		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T13	4		T41	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T41	1		T165	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T1	1		T13	11		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T14	10		T33	1		T252	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18130	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	3		T53	19		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T158	11		T167	1		T17	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T208	14		T17	8		T169	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	862	1			T216	18		T217	24		T241	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T177	9		T167	7		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T148	13		T145	8		T219	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T156	4		T208	7		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T74	20		T151	11		T84	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T84	7		T170	15		T110	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	7		T148	6		T179	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T177	1		T95	5		T214	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T39	4		T168	11		T49	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	10		T206	1		T50	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T155	11		T17	10		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T207	2		T17	7		T104	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T84	11		T253	1		T254	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	6		T41	14		T158	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T41	4		T151	1		T160	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T1	2		T13	7		T255	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T256	2		T249	1		T257	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T74	1		T39	5		T40	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T191	1		T249	3		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T105	6		T232	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T17	9		T258	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T10	11		T12	10		T53	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T46	15		T173	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T44	1		T158	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	5		T206	5		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	5		T149	1		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	1		T148	1		T74	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T167	1		T208	8		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T46	13		T148	1		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T150	1		T156	7		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	9		T147	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T177	1		T84	9		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T87	29		T39	6		T168	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	5		T10	12		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T173	1		T155	14		T17	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T145	1		T149	1		T227	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	10		T149	1		T84	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	452	1			T1	1		T13	15		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1680	1			T5	29		T14	10		T15	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T249	1		T250	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T105	4		T232	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T17	8		T258	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	3		T53	19		T223	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T158	11		T167	1		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T158	10		T208	14		T169	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	3		T206	5		T105	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T177	9		T17	8		T108	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T148	4		T74	20		T48	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T167	7		T208	7		T170	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T148	9		T145	8		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T156	4		T218	10		T94	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	7		T148	6		T84	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T177	1		T84	7		T170	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T39	4		T168	11		T49	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	10		T206	1		T50	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T155	11		T17	10		T169	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T207	2		T17	7		T104	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T84	11		T160	9		T218	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T1	2		T13	13		T41	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	981	1			T41	4		T216	18		T151	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T10	1		T12	10		T53	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T46	1		T173	1		T158	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T44	1		T149	1		T208	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1202	1			T5	3		T15	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	1		T177	10		T167	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	1		T46	1		T148	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T150	1		T156	5		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T147	1		T150	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T84	8		T209	1		T170	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	8		T148	7		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	1		T177	2		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T39	7		T168	12		T49	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	11		T145	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T149	1		T173	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T165	1		T227	1		T207	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T14	1		T84	12		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T13	7		T41	15		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T41	5		T165	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T1	3		T13	8		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T14	1		T33	1		T252	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18281	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T10	10		T12	3		T53	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T46	14		T153	18		T17	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T208	15		T17	6		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1159	1			T5	26		T15	7		T16	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	4		T177	9		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	12		T145	9		T219	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T156	6		T208	7		T171	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T74	17		T151	12		T223	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T84	8		T218	11		T100	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	8		T87	27		T179	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	11		T95	2		T214	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	3		T168	9		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	4		T50	2		T111	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T155	13		T17	15		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T227	12		T207	3		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T14	9		T84	14		T98	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T13	3		T156	3		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T157	14		T153	11		T185	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T13	10		T231	9		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T14	9		T259	8		T249	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T191	1		T249	2		T250	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T105	5		T232	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T17	9		T258	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T10	1		T12	10		T53	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T46	1		T173	1		T158	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T44	1		T158	11		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	5		T206	6		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	1		T149	1		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T44	1		T148	5		T74	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T167	8		T208	8		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	1		T148	10		T145	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T150	1		T156	5		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	8		T147	1		T148	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T177	2		T84	8		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T87	2		T39	7		T168	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	11		T10	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T173	1		T155	12		T17	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T145	1		T149	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T149	1		T84	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	451	1			T1	3		T13	15		T41	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1346	1			T5	3		T14	1		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T105	5		T232	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T17	8		T258	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	10		T12	3		T53	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	14		T153	18		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T208	15		T161	17		T91	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	3		T206	4		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	4		T177	9		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T74	17		T48	3		T260	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T208	7		T171	7		T180	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	12		T145	9		T151	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T156	6		T218	11		T94	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	8		T84	4		T179	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T84	8		T111	6		T214	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T87	27		T39	3		T168	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	4		T10	11		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T155	13		T17	15		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T227	12		T207	3		T17	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	9		T84	14		T98	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T13	13		T156	3		T219	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1315	1			T5	26		T14	9		T15	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25