Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23567

1

T1

3

T2

139

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3692

1

T10

11

T12

13

T13

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21132

1

T2

139

T3

20

T7

11

auto[1]

6127

1

T1

3

T5

29

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	51	1			T169	9		T104	25		T261	17
values[0]	65	1			T161	22		T182	21		T262	4
values[1]	677	1			T1	3		T6	15		T148	5
values[2]	666	1			T10	12		T13	16		T46	15
values[3]	837	1			T13	10		T44	1		T149	1
values[4]	651	1			T10	5		T12	13		T148	10
values[5]	2827	1			T5	29		T15	8		T16	35
values[6]	687	1			T45	1		T147	1		T152	1
values[7]	731	1			T223	33		T251	1		T157	10
values[8]	641	1			T14	10		T41	5		T44	1
values[9]	1160	1			T10	11		T13	18		T14	10
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	965	1			T6	15		T148	5		T145	18
values[1]	740	1			T1	3		T10	12		T13	16
values[2]	715	1			T13	10		T44	1		T165	1
values[3]	2883	1			T5	29		T12	13		T15	8
values[4]	552	1			T10	5		T46	13		T53	26
values[5]	749	1			T45	1		T147	1		T152	1
values[6]	792	1			T14	10		T41	5		T44	1
values[7]	559	1			T10	11		T14	10		T145	1
values[8]	857	1			T13	18		T53	19		T165	1
values[9]	181	1			T164	1		T148	7		T155	25
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	5		T148	1		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T145	10		T154	1		T223	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	1		T10	12		T46	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	9		T149	1		T84	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T165	1		T150	2		T84	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	4		T44	1		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T5	29		T15	8		T16	35
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T12	10		T41	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	5		T149	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	13		T53	16		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	1		T33	1		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T147	1		T152	1		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	10		T41	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T251	1		T167	1		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	10		T145	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	11		T74	18		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T53	10		T177	1		T87	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T13	11		T165	1		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T164	1		T148	1		T155	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T160	1		T263	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	10		T148	4		T151	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T145	8		T167	1		T169	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	2		T17	10		T169	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	7		T84	7		T206	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T84	11		T208	21		T219	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	6		T151	11		T84	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T158	10		T216	18		T217	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	3		T41	14		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T158	3		T210	7		T264	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T53	10		T17	7		T107	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T168	10		T170	13		T265	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T177	9		T207	2		T167	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T41	4		T223	16		T170	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	2		T160	12		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T158	11		T185	12		T253	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T74	20		T39	2		T42	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T53	9		T177	1		T156	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	7		T169	8		T206	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T148	6		T155	11		T219	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T160	9		T266	11		T267	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T261	17		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T169	1		T104	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T182	13		T254	1		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T161	11		T262	1		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	1		T6	5		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T154	1		T223	8		T87	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	12		T46	15		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	9		T145	10		T84	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T150	2		T84	15		T157	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	4		T44	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T10	5		T149	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	10		T148	1		T84	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T5	29		T15	8		T16	35
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T41	1		T46	13		T53	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	1		T168	1		T180	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T147	1		T152	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T223	17		T157	10		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T251	1		T205	1		T47	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	10		T41	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T74	18		T167	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T14	10		T53	10		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T10	11		T13	11		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T169	8		T104	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T182	8		T254	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T161	11		T262	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	2		T6	10		T148	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T179	12		T105	4		T161	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T208	7		T169	7		T50	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	7		T145	8		T84	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T84	11		T208	14		T17	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	6		T151	11		T105	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T158	10		T225	9		T108	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	3		T148	9		T84	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	846	1			T158	3		T216	18		T217	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	14		T53	10		T17	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T168	10		T265	12		T231	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T177	9		T207	2		T167	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T223	16		T170	28		T214	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T47	2		T108	6		T255	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T41	4		T185	12		T269	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T74	20		T39	2		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T53	9		T148	6		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T13	7		T206	1		T160	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T6	11		T148	5		T151	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T145	9		T154	1		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	3		T10	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	8		T149	1		T84	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T165	1		T150	2		T84	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	7		T44	1		T151	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T5	3		T15	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	10		T41	15		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	1		T149	1		T158	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T46	1		T53	11		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T45	1		T33	1		T168	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T147	1		T152	1		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	1		T41	5		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T251	1		T167	1		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T145	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	1		T74	21		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T53	10		T177	2		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	8		T165	1		T169	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T164	1		T148	7		T155	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T160	10		T263	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	4		T168	9		T104	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T145	9		T223	7		T87	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	11		T46	14		T17	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	8		T84	8		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T84	14		T157	14		T208	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	3		T151	12		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T5	26		T15	7		T16	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	3		T17	9		T218	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T10	4		T210	9		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	12		T53	15		T153	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T180	15		T170	13		T265	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T177	9		T207	3		T108	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	9		T223	16		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T215	13		T270	8		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T14	9		T40	2		T260	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T10	10		T74	17		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T53	9		T87	16		T156	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	10		T104	14		T51	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T155	13		T219	9		T271	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T266	10		T267	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T261	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T169	9		T104	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T182	9		T254	15		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T161	12		T262	4		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	3		T6	11		T148	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T154	1		T223	1		T87	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	1		T46	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	8		T145	9		T84	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T150	2		T84	12		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	7		T44	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T149	1		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	10		T148	10		T84	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T5	3		T15	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T41	15		T46	1		T53	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T45	1		T168	11		T180	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T147	1		T152	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T223	17		T157	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T251	1		T205	1		T47	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	1		T41	5		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T74	21		T167	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T14	1		T53	10		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T10	1		T13	8		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T261	16		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T104	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T182	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T161	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	4		T168	9		T104	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T223	7		T87	11		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	11		T46	14		T208	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	8		T145	9		T84	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T84	14		T157	14		T208	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	3		T151	12		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T10	4		T108	2		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	3		T84	4		T17	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T5	26		T15	7		T16	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	12		T53	15		T153	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T180	15		T265	2		T98	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T177	9		T207	3		T107	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T223	16		T157	9		T170	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T108	7		T272	9		T273	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T14	9		T40	2		T260	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T74	17		T42	2		T49	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	9		T53	9		T155	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T10	10		T13	10		T51	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25