Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23440

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3819

1

T1

3

T6

15

T10

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21687

1

T1

3

T2

139

T3

20

auto[1]

5572

1

T5

29

T6

15

T10

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T33	1		T210	3		T259	9
values[0]	27	1			T150	1		T39	6		T118	9
values[1]	767	1			T10	12		T13	34		T53	45
values[2]	723	1			T6	15		T14	10		T45	1
values[3]	595	1			T44	1		T148	10		T145	19
values[4]	648	1			T41	15		T158	11		T40	5
values[5]	812	1			T44	1		T165	1		T173	1
values[6]	648	1			T149	1		T154	1		T251	1
values[7]	628	1			T1	3		T10	5		T41	5
values[8]	2827	1			T5	29		T13	10		T14	10
values[9]	1305	1			T10	11		T12	13		T148	7
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	905	1			T10	12		T13	34		T14	10
values[1]	791	1			T45	1		T46	28		T148	10
values[2]	639	1			T6	15		T44	1		T145	1
values[3]	689	1			T41	15		T145	18		T158	11
values[4]	676	1			T44	1		T165	1		T173	1
values[5]	629	1			T1	3		T10	5		T41	5
values[6]	2773	1			T5	29		T15	8		T16	35
values[7]	781	1			T13	10		T14	10		T148	7
values[8]	815	1			T10	11		T12	13		T165	1
values[9]	278	1			T90	1		T17	7		T169	4
minimum	18283	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T10	12		T13	20		T53	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	10		T53	16		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	15		T173	1		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T45	1		T46	13		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T158	1		T227	13		T17	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	5		T44	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T150	1		T152	1		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T41	1		T145	10		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T165	1		T150	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T44	1		T173	1		T18	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T148	1		T251	1		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T10	5		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T5	29		T15	8		T16	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T147	1		T223	17		T84	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	10		T148	1		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	4		T207	4		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	11		T12	10		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T149	1		T155	14		T87	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T90	1		T17	7		T179	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T169	1		T215	1		T100	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18130	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T52	4		T118	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	14		T53	9		T84	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	10		T158	11		T74	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T208	14		T47	2		T107	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T148	9		T177	9		T17	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T158	3		T17	11		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T6	10		T179	12		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T208	7		T169	8		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T41	14		T145	8		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T151	1		T177	1		T94	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T108	4		T110	5		T265	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T148	4		T17	10		T104	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T1	2		T41	4		T17	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	866	1			T216	18		T84	8		T217	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T223	16		T84	7		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T148	6		T151	11		T167	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	6		T207	2		T50	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	3		T156	4		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T155	11		T104	11		T218	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T179	11		T170	13		T117	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T169	3		T274	12		T275	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T52	2		T118	5		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T33	1		T210	2		T259	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T150	1		T39	4		T276	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T118	4		T38	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	12		T13	20		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T53	16		T158	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	15		T173	1		T156	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	5		T14	10		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T158	1		T227	13		T180	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T44	1		T148	1		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T17	14		T169	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T41	1		T158	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T165	1		T150	2		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T44	1		T173	1		T153	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T149	1		T251	1		T17	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T154	1		T17	9		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T148	1		T84	5		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T10	5		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T5	29		T14	10		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	4		T149	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T10	11		T12	10		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	493	1			T155	14		T87	17		T207	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T210	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T39	2		T276	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T118	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	14		T53	9		T84	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	10		T158	11		T167	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T156	3		T208	14		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	10		T74	20		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T158	3		T47	2		T104	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T148	9		T145	8		T231	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T17	11		T169	8		T255	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	14		T158	10		T179	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	1		T177	1		T208	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T105	11		T108	4		T110	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	10		T104	10		T277	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	7		T170	9		T48	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T148	4		T84	8		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	2		T41	4		T223	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T216	18		T151	11		T217	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	6		T50	3		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	3		T148	6		T156	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T155	11		T207	2		T169	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T10	1		T13	16		T53	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	1		T53	11		T158	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	1		T173	1		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T45	1		T46	1		T148	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T158	4		T227	1		T17	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	11		T44	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T150	1		T152	1		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T41	15		T145	9		T158	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T165	1		T150	1		T151	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T44	1		T173	1		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T148	5		T251	1		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	3		T10	1		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T5	3		T15	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T147	1		T223	17		T84	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T148	7		T151	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	7		T207	3		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	1		T12	10		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T149	1		T155	12		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T90	1		T17	1		T179	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T169	4		T215	1		T100	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18268	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T52	4		T118	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	11		T13	18		T53	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	9		T53	15		T74	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T46	14		T208	15		T107	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	12		T177	9		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T227	12		T17	11		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	4		T179	10		T218	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T208	7		T272	9		T255	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T145	9		T153	18		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T94	12		T232	14		T186	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	3		T108	2		T265	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	15		T104	14		T101	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T10	4		T17	8		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T5	26		T15	7		T16	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T223	16		T84	8		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	9		T151	12		T87	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	3		T207	3		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T10	10		T12	3		T223	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T155	13		T87	16		T104	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T17	6		T179	11		T170	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T100	22		T278	11		T258	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T52	2		T118	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T33	1		T210	2		T259	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T150	1		T39	3		T276	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T118	6		T38	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	1		T13	16		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	11		T158	12		T167	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	1		T173	1		T156	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	11		T14	1		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T158	4		T227	1		T180	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	1		T148	10		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	14		T169	9		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T41	15		T158	11		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T165	1		T150	2		T151	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T44	1		T173	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T149	1		T251	1		T17	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T154	1		T17	8		T170	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T148	5		T84	9		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	3		T10	1		T41	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T5	3		T14	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	7		T149	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T10	1		T12	10		T148	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	424	1			T155	12		T87	1		T207	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T210	1		T259	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T39	3		T276	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T118	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	11		T13	18		T53	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T53	15		T17	6		T206	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	14		T156	3		T208	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	4		T14	9		T46	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T227	12		T180	15		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T145	9		T153	11		T231	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T17	11		T272	9		T255	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	2		T18	3		T179	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T208	7		T94	12		T100	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T153	18		T105	20		T108	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T17	15		T104	14		T101	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T17	8		T48	3		T279	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T84	4		T161	7		T215	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	4		T223	16		T84	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T5	26		T14	9		T15	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	3		T50	2		T108	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	10		T12	3		T223	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	411	1			T155	13		T87	16		T207	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25