Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23596

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3663

1

T1

3

T13

28

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21260

1

T1

3

T2

139

T3

20

auto[1]

5999

1

T5

29

T10

23

T12

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T150	1		T255	6		T277	11
values[0]	49	1			T185	7		T181	3		T280	6
values[1]	676	1			T13	10		T14	10		T41	15
values[2]	424	1			T41	5		T53	19		T149	1
values[3]	727	1			T1	3		T12	13		T13	18
values[4]	2693	1			T5	29		T6	15		T15	8
values[5]	625	1			T10	11		T46	15		T53	26
values[6]	841	1			T44	1		T148	7		T149	1
values[7]	890	1			T45	1		T148	10		T173	1
values[8]	677	1			T14	10		T165	1		T145	18
values[9]	1360	1			T10	17		T13	16		T46	13
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T13	10		T14	10		T41	20
values[1]	677	1			T1	3		T53	19		T149	2
values[2]	566	1			T12	13		T13	18		T158	12
values[3]	2661	1			T5	29		T6	15		T15	8
values[4]	684	1			T10	11		T44	1		T46	15
values[5]	897	1			T53	26		T148	17		T158	4
values[6]	847	1			T14	10		T45	1		T149	1
values[7]	714	1			T10	5		T147	1		T165	1
values[8]	884	1			T10	12		T13	16		T46	13
values[9]	285	1			T155	25		T105	32		T215	19
minimum	18285	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	10		T41	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	4		T41	1		T44	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T149	1		T17	5		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T53	10		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	10		T158	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	11		T151	13		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T5	29		T6	5		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T150	1		T168	1		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	11		T44	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	15		T165	1		T84	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T53	16		T158	1		T227	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T148	2		T74	18		T84	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T45	1		T149	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	10		T158	1		T156	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	5		T165	1		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T147	1		T173	1		T153	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T10	12		T13	9		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T46	13		T152	1		T157	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T155	14		T215	11		T255	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T105	21		T281	1		T270	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18139	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	4		T148	4		T39	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	6		T41	14		T156	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T17	3		T50	3		T161	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	2		T53	9		T223	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	3		T158	11		T169	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	7		T151	11		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	810	1			T6	10		T216	18		T217	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T168	10		T169	8		T104	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T47	2		T161	11		T210	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T84	7		T207	2		T110	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	10		T158	3		T177	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T148	15		T74	20		T84	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T151	1		T17	8		T206	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T158	10		T156	4		T17	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T145	8		T84	8		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T108	9		T265	12		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	7		T17	17		T179	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T42	1		T48	5		T91	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T155	11		T215	8		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T105	11		T270	5		T277	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T74	1		T39	5		T40	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T150	1		T255	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T277	1		T229	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T185	1		T181	1		T282	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T280	6		T249	1		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	10		T148	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	4		T41	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T41	1		T179	11		T284	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	10		T149	1		T223	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	10		T158	1		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T13	11		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T5	29		T6	5		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T168	11		T169	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	11		T53	16		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	15		T165	1		T84	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T44	1		T149	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T148	1		T74	18		T84	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T45	1		T158	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T148	1		T173	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T165	1		T145	10		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	10		T153	19		T17	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	423	1			T10	17		T13	9		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T46	13		T147	1		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T255	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T277	10		T229	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T185	6		T181	2		T282	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T249	2		T283	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T148	4		T39	2		T245	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	6		T41	14		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T41	4		T179	12		T284	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T53	9		T223	16		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	3		T158	11		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	2		T13	7		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	830	1			T6	10		T216	18		T217	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T168	21		T169	8		T170	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T53	10		T177	1		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T84	7		T207	2		T104	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T169	3		T206	1		T225	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T148	6		T74	20		T84	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T158	3		T151	1		T17	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T148	9		T158	10		T167	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T145	8		T84	8		T170	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	8		T108	9		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T13	7		T155	11		T17	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T42	1		T48	5		T105	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	1		T41	5		T148	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	7		T41	15		T44	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T149	1		T17	5		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	3		T53	10		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	10		T158	12		T169	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	8		T151	12		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T5	3		T6	11		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T150	1		T168	11		T169	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	1		T44	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	1		T165	1		T84	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T53	11		T158	4		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T148	17		T74	21		T84	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T45	1		T149	1		T151	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	1		T158	11		T156	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T10	1		T165	1		T145	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	1		T173	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T13	8		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	1		T152	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T155	12		T215	9		T255	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T105	12		T281	1		T270	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18276	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	9		T17	6		T179	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	3		T156	3		T39	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	3		T50	2		T161	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T53	9		T223	16		T208	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T12	3		T20	1		T285	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	10		T151	12		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T5	26		T6	4		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T104	10		T108	2		T218	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T10	10		T223	7		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T46	14		T84	8		T207	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T53	15		T227	12		T215	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T74	17		T84	14		T87	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	8		T206	4		T170	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	9		T156	6		T17	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	4		T145	9		T84	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T153	18		T108	11		T111	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	11		T13	8		T157	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T46	12		T157	9		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T155	13		T215	10		T255	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T105	20		T270	8		T286	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T287	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T150	1		T255	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T277	11		T229	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T185	7		T181	3		T282	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T280	1		T249	3		T283	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	1		T148	5		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	7		T41	15		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T41	5		T179	13		T284	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	10		T149	1		T223	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	10		T158	12		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	3		T13	8		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T5	3		T6	11		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T168	23		T169	9		T170	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	1		T53	11		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	1		T165	1		T84	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	1		T149	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T148	7		T74	21		T84	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T45	1		T158	4		T151	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T148	10		T173	1		T158	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T165	1		T145	9		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	1		T153	1		T17	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T10	2		T13	8		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T46	1		T147	1		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T255	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T229	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T280	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	9		T17	6		T180	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	3		T156	3		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T179	10		T284	11		T288	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T53	9		T223	16		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	3		T17	3		T50	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	10		T151	12		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1129	1			T5	26		T6	4		T15	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T168	9		T49	2		T108	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	10		T53	15		T161	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T46	14		T84	8		T207	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T223	7		T231	15		T273	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T74	17		T84	14		T156	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T227	12		T17	8		T206	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T87	16		T98	11		T287	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T145	9		T84	4		T87	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	9		T153	18		T17	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T10	15		T13	8		T155	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T46	12		T157	9		T153	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25