Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23807

1

T1

3

T2

139

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3452

1

T10

5

T12

13

T13

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21197

1

T2

139

T3

20

T7

11

auto[1]

6062

1

T1

3

T5

29

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T48	11		T289	10		-	-
values[0]	74	1			T167	1		T111	7		T37	15
values[1]	746	1			T1	3		T12	13		T148	5
values[2]	2748	1			T5	29		T10	11		T14	10
values[3]	768	1			T45	1		T53	19		T165	1
values[4]	744	1			T6	15		T44	1		T46	13
values[5]	742	1			T14	10		T41	5		T173	1
values[6]	553	1			T10	12		T13	10		T46	15
values[7]	479	1			T13	16		T148	10		T149	1
values[8]	774	1			T10	5		T13	18		T147	1
values[9]	1344	1			T44	1		T164	1		T148	7
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	956	1			T1	3		T12	13		T14	10
values[1]	2826	1			T5	29		T10	11		T15	8
values[2]	673	1			T44	1		T45	1		T53	19
values[3]	831	1			T6	15		T14	10		T46	13
values[4]	626	1			T41	5		T46	15		T165	1
values[5]	665	1			T10	12		T13	10		T149	1
values[6]	516	1			T13	16		T147	1		T148	10
values[7]	807	1			T10	5		T13	18		T145	18
values[8]	953	1			T44	1		T164	1		T148	7
values[9]	140	1			T173	1		T48	11		T218	22
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	1		T14	10		T156	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T12	10		T148	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T5	29		T10	11		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T53	16		T40	5		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T44	1		T45	1		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T154	1		T84	15		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	5		T14	10		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T46	13		T149	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T165	1		T167	1		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T41	1		T46	15		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	12		T149	1		T155	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	4		T151	13		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	9		T147	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	1		T145	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	11		T158	1		T84	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T10	5		T145	10		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T44	1		T164	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T148	1		T151	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T173	1		T48	6		T52	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T218	12		T290	14		T291	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	2		T156	3		T17	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	3		T148	4		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T41	14		T216	18		T217	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T53	10		T159	10		T231	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T53	9		T168	10		T108	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T84	11		T215	8		T214	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	10		T158	11		T104	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	1		T50	3		T110	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T167	7		T39	2		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T41	4		T17	8		T105	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T155	11		T207	2		T17	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	6		T151	11		T177	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	7		T167	1		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T148	9		T158	10		T84	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	7		T158	3		T84	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T145	8		T177	9		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T74	20		T223	16		T219	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T148	6		T151	1		T208	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T48	5		T52	2		T279	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T218	10		T291	1		T292	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T48	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T289	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T167	1		T293	1		T294	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T111	7		T37	1		T279	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T156	4		T17	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	10		T148	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T5	29		T10	11		T14	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	16		T40	5		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T45	1		T53	10		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T84	15		T183	1		T42	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	5		T44	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T46	13		T149	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	10		T167	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T41	1		T173	1		T17	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	12		T165	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	4		T46	15		T151	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	9		T149	1		T207	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T148	1		T150	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	11		T147	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	5		T145	11		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T44	1		T164	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T148	1		T151	1		T227	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T48	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T289	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T295	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T37	14		T279	16		T269	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	2		T156	3		T17	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	3		T148	4		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T41	14		T216	18		T217	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	10		T169	8		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T53	9		T17	7		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T84	11		T42	1		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	10		T158	11		T104	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T245	12		T296	12		T185	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T167	7		T39	2		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	4		T17	8		T50	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T155	11		T47	2		T170	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	6		T151	11		T105	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	7		T207	2		T167	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T148	9		T177	1		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	7		T158	3		T84	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T145	8		T158	10		T84	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T74	20		T223	16		T219	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T148	6		T151	1		T177	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	3		T14	1		T156	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T12	10		T148	5		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T5	3		T10	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T53	11		T40	3		T159	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	1		T45	1		T53	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T154	1		T84	12		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	11		T14	1		T158	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T46	1		T149	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T165	1		T167	8		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T41	5		T46	1		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	1		T149	1		T155	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	7		T151	12		T177	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	8		T147	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T148	10		T145	1		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	8		T158	4		T84	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	1		T145	9		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T44	1		T164	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T148	7		T151	2		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T173	1		T48	8		T52	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T218	11		T290	1		T291	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	9		T156	3		T17	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	3		T157	14		T39	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T5	26		T10	10		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	15		T40	2		T231	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T53	9		T108	13		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T84	14		T215	10		T214	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	4		T14	9		T87	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T46	12		T42	2		T50	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T153	11		T17	9		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	14		T17	6		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	11		T155	13		T207	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	3		T151	12		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T13	8		T240	9		T98	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T223	7		T84	8		T156	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	10		T84	4		T208	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	4		T145	9		T227	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T74	17		T223	16		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T208	15		T153	18		T168	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T48	3		T52	2		T279	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T218	11		T290	13		T292	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T48	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T289	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T167	1		T293	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T111	1		T37	15		T279	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	3		T156	4		T17	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	10		T148	5		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T5	3		T10	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	11		T40	3		T169	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T45	1		T53	10		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T84	12		T183	1		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	11		T44	1		T158	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T46	1		T149	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	1		T167	8		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T41	5		T173	1		T17	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	1		T165	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	7		T46	1		T151	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	8		T149	1		T207	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T148	10		T150	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	8		T147	1		T158	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	1		T145	10		T158	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	395	1			T44	1		T164	1		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T148	7		T151	2		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T48	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T289	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T294	5		T295	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T111	6		T279	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T156	3		T17	8		T210	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	3		T157	14		T39	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T5	26		T10	10		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T53	15		T40	2		T179	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T53	9		T17	8		T108	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T84	14		T42	2		T215	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	4		T87	16		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T46	12		T296	13		T185	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	9		T153	11		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	6		T50	2		T213	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	11		T155	13		T108	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	3		T46	14		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	8		T207	3		T17	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T223	7		T156	6		T297	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	10		T84	4		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	4		T145	9		T84	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T74	17		T223	16		T219	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T227	12		T177	9		T208	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25