Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23370

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3889

1

T1

3

T6

15

T10

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21719

1

T1

3

T2

139

T3

20

auto[1]

5540

1

T5

29

T6

15

T10

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T152	1		T156	11		T224	1
values[0]	6	1			T39	6		-	-		-	-
values[1]	733	1			T10	12		T13	34		T53	45
values[2]	766	1			T14	10		T45	1		T46	28
values[3]	602	1			T6	15		T44	1		T148	10
values[4]	640	1			T41	15		T145	19		T158	11
values[5]	866	1			T44	1		T165	1		T150	1
values[6]	583	1			T149	1		T173	1		T154	1
values[7]	617	1			T1	3		T10	5		T41	5
values[8]	2881	1			T5	29		T13	10		T14	10
values[9]	1057	1			T10	11		T12	13		T148	7
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	701	1			T10	12		T13	34		T14	10
values[1]	812	1			T45	1		T46	13		T148	10
values[2]	579	1			T6	15		T145	1		T158	4
values[3]	693	1			T41	15		T44	1		T165	1
values[4]	721	1			T44	1		T173	1		T150	1
values[5]	654	1			T1	3		T10	5		T41	5
values[6]	2729	1			T5	29		T15	8		T16	35
values[7]	741	1			T13	10		T14	10		T151	24
values[8]	951	1			T10	11		T12	13		T148	7
values[9]	195	1			T169	4		T170	27		T100	23
minimum	18483	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	12		T13	20		T46	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	10		T53	16		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T173	1		T167	1		T208	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T45	1		T46	13		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T158	1		T227	13		T17	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	5		T145	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T165	1		T150	1		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T41	1		T44	1		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T150	1		T151	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T44	1		T173	1		T153	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T148	1		T251	1		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	1		T10	5		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T5	29		T15	8		T16	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T147	1		T223	17		T84	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	10		T151	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	4		T209	1		T50	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	11		T12	10		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T149	1		T155	14		T87	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T170	14		T117	8		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T169	1		T100	23		T278	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18197	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T164	1		T154	1		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	14		T84	11		T156	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T53	10		T158	11		T74	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T208	14		T168	11		T107	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T148	9		T177	9		T17	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T158	3		T17	3		T47	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	10		T179	12		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T208	7		T17	8		T169	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	14		T145	8		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T151	1		T177	1		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T48	5		T108	4		T110	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T148	4		T17	10		T104	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T1	2		T41	4		T17	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	845	1			T216	18		T84	8		T217	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T223	16		T84	7		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T151	11		T167	1		T210	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	6		T50	3		T108	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	3		T148	6		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T155	11		T207	2		T104	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T170	13		T117	2		T188	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T169	3		T298	13		T299	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T53	9		T74	1		T39	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T52	2		T91	1		T37	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T152	1		T156	7		T224	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T218	12		T51	2		T161	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T39	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	12		T13	20		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	16		T164	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T46	15		T173	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	10		T45	1		T46	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T158	1		T227	13		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	5		T44	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T150	1		T208	8		T17	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T41	1		T145	11		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T165	1		T150	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T44	1		T153	19		T18	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T149	1		T251	1		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T173	1		T154	1		T17	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T148	1		T84	5		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T10	5		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T5	29		T14	10		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	4		T33	1		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	11		T12	10		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T149	1		T155	14		T87	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T156	4		T210	1		T188	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T218	10		T51	1		T161	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	14		T53	9		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T53	10		T158	11		T167	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T84	11		T156	3		T208	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T74	20		T177	9		T17	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T158	3		T17	3		T47	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	10		T148	9		T179	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T208	7		T17	8		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	14		T145	8		T158	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T151	1		T177	1		T159	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T105	11		T108	4		T110	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	10		T104	10		T277	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T17	7		T170	9		T48	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T148	4		T84	8		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	2		T41	4		T223	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	896	1			T216	18		T151	11		T217	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	6		T169	7		T50	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	3		T148	6		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T155	11		T207	2		T169	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	1		T13	16		T46	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T53	11		T158	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T173	1		T167	1		T208	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T45	1		T46	1		T148	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T158	4		T227	1		T17	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	11		T145	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T165	1		T150	1		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T41	15		T44	1		T145	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T150	1		T151	2		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T44	1		T173	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T148	5		T251	1		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	3		T10	1		T41	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T5	3		T15	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T147	1		T223	17		T84	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	1		T151	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	7		T209	1		T50	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	1		T12	10		T148	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T149	1		T155	12		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T170	14		T117	3		T188	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T169	4		T100	1		T278	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18346	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T164	1		T154	1		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	11		T13	18		T46	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	9		T53	15		T74	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T208	15		T168	9		T107	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	12		T177	9		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T227	12		T17	3		T108	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	4		T179	10		T180	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T208	7		T17	8		T272	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T145	9		T40	2		T105	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T94	12		T232	14		T186	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T153	18		T18	3		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T17	15		T104	14		T101	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T10	4		T17	8		T279	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T5	26		T15	7		T16	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T223	16		T84	8		T157	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T14	9		T151	12		T87	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	3		T50	2		T108	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	10		T12	3		T223	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T155	13		T87	16		T207	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T170	13		T117	7		T300	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T100	22		T278	11		T299	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T53	9		T39	3		T219	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T52	2		T91	2		T301	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T152	1		T156	5		T224	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T218	11		T51	2		T161	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T39	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	1		T13	16		T53	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T53	11		T164	1		T158	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T46	1		T173	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	1		T45	1		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T158	4		T227	1		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	11		T44	1		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T150	1		T208	8		T17	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T41	15		T145	10		T158	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T165	1		T150	1		T151	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T44	1		T153	1		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	1		T251	1		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T173	1		T154	1		T17	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T148	5		T84	9		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	3		T10	1		T41	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T5	3		T14	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T13	7		T33	1		T169	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	1		T12	10		T148	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T149	1		T155	12		T87	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T156	6		T210	1		T259	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T218	11		T51	1		T161	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T39	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	11		T13	18		T53	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T53	15		T206	4		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	14		T84	14		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	9		T46	12		T74	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T227	12		T17	3		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	4		T153	11		T179	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T208	7		T17	8		T272	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T145	9		T40	2		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T94	12		T232	14		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T153	18		T18	3		T105	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	15		T104	14		T101	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T17	8		T48	3		T279	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T84	4		T161	7		T302	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	4		T223	16		T84	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T5	26		T14	9		T15	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	3		T50	2		T108	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	10		T12	3		T223	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T155	13		T87	16		T207	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25