Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27259

1

T1

3

T2

139

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23948

1

T2

139

T3

20

T5

29

auto[ADC_CTRL_FILTER_COND_OUT]

3311

1

T1

3

T6

15

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21402

1

T1

3

T2

139

T3

20

auto[1]

5857

1

T5

29

T10

16

T13

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23334

1

T1

1

T2

139

T3

20

auto[1]

3925

1

T1

2

T6

10

T12

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	360	1			T154	1		T74	38		T17	15
values[0]	36	1			T239	10		T303	26		-	-
values[1]	473	1			T13	10		T41	5		T165	1
values[2]	615	1			T148	10		T149	2		T227	13
values[3]	805	1			T10	11		T165	1		T149	1
values[4]	695	1			T13	18		T44	1		T46	28
values[5]	2803	1			T5	29		T12	13		T15	8
values[6]	773	1			T10	5		T14	10		T45	1
values[7]	706	1			T14	10		T148	7		T154	1
values[8]	752	1			T10	12		T41	15		T164	1
values[9]	975	1			T1	3		T6	15		T13	16
minimum	18266	1			T2	139		T3	20		T7	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	556	1			T41	5		T165	1		T150	1
values[1]	727	1			T148	10		T149	2		T84	16
values[2]	626	1			T10	11		T13	18		T44	1
values[3]	2875	1			T5	29		T15	8		T16	35
values[4]	679	1			T12	13		T53	26		T165	1
values[5]	820	1			T10	5		T14	10		T45	1
values[6]	617	1			T14	10		T148	7		T154	1
values[7]	764	1			T1	3		T10	12		T13	16
values[8]	1041	1			T6	15		T44	1		T154	2
values[9]	162	1			T153	12		T238	24		T182	21
minimum	18392	1			T2	139		T3	20		T7	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

4128

1

T5

26

T6

4

T10

25

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T41	1		T150	1		T223	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T165	1		T227	13		T84	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T148	1		T149	1		T167	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T149	1		T84	9		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	11		T13	11		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T165	1		T149	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T5	29		T15	8		T16	35
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	28		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T53	16		T87	12		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	10		T165	1		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T10	5		T14	10		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T148	1		T151	13		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	10		T148	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T156	4		T47	2		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T164	1		T150	1		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T10	12		T13	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T44	1		T154	1		T74	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	5		T154	1		T156	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T238	15		T182	13		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T153	12		T234	1		T291	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18161	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T207	4		T239	10		T202	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T41	4		T223	16		T219	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T84	8		T51	1		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T148	9		T167	1		T179	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T84	7		T17	8		T240	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	7		T104	11		T105	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T158	3		T208	7		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	880	1			T158	10		T216	18		T217	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	9		T177	9		T84	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T53	10		T206	1		T104	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	3		T17	1		T110	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T145	8		T151	1		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	4		T151	11		T208	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T148	6		T210	1		T265	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	3		T47	2		T170	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T155	11		T39	2		T17	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	2		T13	7		T41	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T74	20		T17	3		T105	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	10		T156	4		T168	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T238	9		T182	8		T188	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T234	9		T291	1		T304	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	6		T74	1		T39	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T207	2		T202	9		T298	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T154	1		T74	18		T17	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T179	11		T189	1		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T239	10		T303	17		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	4		T41	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T165	1		T207	4		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T148	1		T149	1		T223	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T149	1		T227	13		T84	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T10	11		T152	1		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T165	1		T149	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	11		T44	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T46	28		T53	10		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T5	29		T15	8		T16	35
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	10		T165	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T10	5		T14	10		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T148	1		T151	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	10		T148	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T156	4		T17	9		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T164	1		T150	1		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	12		T41	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T44	1		T87	17		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T6	5		T13	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18128	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T74	20		T17	3		T305	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T179	12		T234	9		T306	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T303	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	6		T41	4		T219	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T207	2		T51	1		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T148	9		T223	16		T167	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T84	15		T17	8		T92	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T170	9		T104	11		T105	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T158	3		T208	7		T107	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	7		T158	10		T210	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T53	9		T177	9		T84	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	857	1			T216	18		T217	24		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	3		T110	5		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T53	10		T145	8		T151	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T148	4		T151	11		T208	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T148	6		T52	2		T214	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T156	3		T17	7		T170	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T155	11		T39	2		T17	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	14		T158	11		T177	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T160	19		T218	10		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	2		T6	10		T13	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T74	1		T39	5		T40	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	5		T150	1		T223	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T165	1		T227	1		T84	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T148	10		T149	1		T167	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T149	1		T84	8		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	1		T13	8		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T165	1		T149	1		T158	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T5	3		T15	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T46	2		T53	10		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T53	11		T87	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	10		T165	1		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	1		T14	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T148	5		T151	12		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	1		T148	7		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T156	4		T47	4		T170	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T164	1		T150	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	3		T10	1		T13	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T44	1		T154	1		T74	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	11		T154	1		T156	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T238	10		T182	9		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T153	1		T234	10		T291	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T2	139		T3	20		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T207	3		T239	1		T202	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T223	16		T40	2		T219	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T227	12		T84	4		T51	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T179	11		T206	4		T111	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T84	8		T17	6		T240	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	10		T13	10		T153	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T208	7		T168	9		T107	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T5	26		T15	7		T16	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	26		T53	9		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T53	15		T87	11		T18	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	3		T51	1		T307	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	4		T14	9		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T151	12		T208	15		T17	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T14	9		T171	7		T210	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T156	3		T105	20		T108	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T155	13		T17	8		T255	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	11		T13	8		T17	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T74	17		T87	16		T17	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	4		T156	6		T179	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T238	14		T182	12		T188	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T153	11		T308	10		T309	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T13	3		T117	7		T24	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T207	3		T239	9		T202	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T154	1		T74	21		T17	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T179	13		T189	1		T234	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T239	1		T303	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	7		T41	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T165	1		T207	3		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T148	10		T149	1		T223	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T149	1		T227	1		T84	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T10	1		T152	1		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T165	1		T149	1		T158	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	8		T44	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	2		T53	10		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T5	3		T15	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	10		T165	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T10	1		T14	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	5		T151	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	1		T148	7		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T156	4		T17	8		T170	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T164	1		T150	1		T155	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	1		T41	15		T158	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T44	1		T87	1		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	3		T6	11		T13	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T2	139		T3	20		T7	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T74	17		T17	9		T20	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T179	10		T306	11		T310	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T239	9		T303	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	3		T219	9		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T207	3		T51	1		T248	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T223	16		T40	2		T179	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T227	12		T84	12		T17	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T10	10		T153	18		T104	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T208	7		T107	8		T240	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	10		T180	15		T210	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	26		T53	9		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T5	26		T15	7		T16	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	3		T161	7		T307	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	4		T14	9		T53	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T151	12		T208	15		T49	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	9		T171	7		T52	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T156	3		T17	8		T108	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T155	13		T17	8		T105	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	11		T105	20		T100	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T87	16		T218	11		T101	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	4		T13	8		T156	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23131

1

T1

3

T2

139

T3

20

auto[1]

auto[0]

4128

1

T5

26

T6

4

T10

25