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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.29


Total test records in report: 920
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T795 /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4272682880 Jul 14 07:02:20 PM PDT 24 Jul 14 07:03:57 PM PDT 24 41585799952 ps
T796 /workspace/coverage/default/36.adc_ctrl_filters_polled.1652497938 Jul 14 07:01:47 PM PDT 24 Jul 14 07:04:46 PM PDT 24 162264645630 ps
T797 /workspace/coverage/default/37.adc_ctrl_poweron_counter.4139073926 Jul 14 07:01:50 PM PDT 24 Jul 14 07:01:54 PM PDT 24 5372623374 ps
T798 /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1307376289 Jul 14 07:01:32 PM PDT 24 Jul 14 07:01:44 PM PDT 24 24330396506 ps
T799 /workspace/coverage/default/44.adc_ctrl_poweron_counter.1878322844 Jul 14 07:02:25 PM PDT 24 Jul 14 07:02:35 PM PDT 24 4148296862 ps
T59 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1072399763 Jul 14 07:00:43 PM PDT 24 Jul 14 07:00:52 PM PDT 24 2122041227 ps
T72 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2997960685 Jul 14 07:00:29 PM PDT 24 Jul 14 07:00:35 PM PDT 24 472373445 ps
T60 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2883382866 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:23 PM PDT 24 2738021416 ps
T65 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3096723554 Jul 14 07:00:06 PM PDT 24 Jul 14 07:00:16 PM PDT 24 427926805 ps
T143 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1352513523 Jul 14 07:00:31 PM PDT 24 Jul 14 07:00:36 PM PDT 24 378718145 ps
T138 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.77185807 Jul 14 07:00:08 PM PDT 24 Jul 14 07:00:16 PM PDT 24 415807085 ps
T66 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3619118885 Jul 14 06:59:55 PM PDT 24 Jul 14 07:00:03 PM PDT 24 718094840 ps
T67 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3076223089 Jul 14 07:00:16 PM PDT 24 Jul 14 07:00:22 PM PDT 24 1001026132 ps
T62 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3962158236 Jul 14 07:00:30 PM PDT 24 Jul 14 07:00:56 PM PDT 24 8784745649 ps
T61 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1488605253 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:31 PM PDT 24 2354329322 ps
T113 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.775953443 Jul 14 07:00:19 PM PDT 24 Jul 14 07:00:25 PM PDT 24 321084689 ps
T78 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3219535647 Jul 14 07:00:25 PM PDT 24 Jul 14 07:00:31 PM PDT 24 917389555 ps
T800 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.285890715 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:29 PM PDT 24 290895590 ps
T73 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4161896611 Jul 14 07:00:02 PM PDT 24 Jul 14 07:00:13 PM PDT 24 367795348 ps
T63 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.556436289 Jul 14 06:59:54 PM PDT 24 Jul 14 07:00:05 PM PDT 24 4667044855 ps
T801 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2351294752 Jul 14 07:00:12 PM PDT 24 Jul 14 07:00:18 PM PDT 24 425444927 ps
T802 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2566764089 Jul 14 07:00:09 PM PDT 24 Jul 14 07:00:17 PM PDT 24 493100831 ps
T803 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1984444088 Jul 14 07:00:24 PM PDT 24 Jul 14 07:00:31 PM PDT 24 419036409 ps
T139 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1510858338 Jul 14 07:00:27 PM PDT 24 Jul 14 07:00:42 PM PDT 24 4665469346 ps
T804 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2656201047 Jul 14 07:00:23 PM PDT 24 Jul 14 07:00:31 PM PDT 24 412260237 ps
T140 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2211311303 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:23 PM PDT 24 2142369525 ps
T64 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2318815573 Jul 14 07:00:07 PM PDT 24 Jul 14 07:00:18 PM PDT 24 4404961849 ps
T68 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.949213171 Jul 14 07:00:08 PM PDT 24 Jul 14 07:00:21 PM PDT 24 4387388854 ps
T144 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3235877433 Jul 14 06:59:56 PM PDT 24 Jul 14 07:01:02 PM PDT 24 26714722580 ps
T805 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.806842005 Jul 14 07:00:15 PM PDT 24 Jul 14 07:00:20 PM PDT 24 511400605 ps
T103 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4184154649 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:29 PM PDT 24 632110842 ps
T77 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1614334686 Jul 14 07:00:05 PM PDT 24 Jul 14 07:00:14 PM PDT 24 553355033 ps
T79 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3091348148 Jul 14 07:00:13 PM PDT 24 Jul 14 07:00:19 PM PDT 24 982151890 ps
T806 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.902383627 Jul 14 07:00:23 PM PDT 24 Jul 14 07:00:45 PM PDT 24 7711307973 ps
T807 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.879706956 Jul 14 06:59:54 PM PDT 24 Jul 14 07:00:00 PM PDT 24 622193549 ps
T330 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3227365969 Jul 14 07:00:00 PM PDT 24 Jul 14 07:00:16 PM PDT 24 8634291554 ps
T808 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3751531507 Jul 14 07:00:23 PM PDT 24 Jul 14 07:00:30 PM PDT 24 391514275 ps
T141 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1659755490 Jul 14 07:00:08 PM PDT 24 Jul 14 07:00:23 PM PDT 24 2184881851 ps
T142 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2192287120 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:18 PM PDT 24 2044388102 ps
T809 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2493222984 Jul 14 07:00:15 PM PDT 24 Jul 14 07:00:22 PM PDT 24 462762550 ps
T810 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.279524035 Jul 14 06:59:57 PM PDT 24 Jul 14 07:00:06 PM PDT 24 622070155 ps
T123 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2371932960 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:28 PM PDT 24 463537462 ps
T811 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1581690833 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:13 PM PDT 24 383715817 ps
T812 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4222588104 Jul 14 07:00:05 PM PDT 24 Jul 14 07:00:14 PM PDT 24 515142491 ps
T331 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2777691809 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:33 PM PDT 24 4412952098 ps
T813 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2855086189 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:25 PM PDT 24 483117356 ps
T814 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1823482211 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:29 PM PDT 24 520901254 ps
T124 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1061061172 Jul 14 07:00:14 PM PDT 24 Jul 14 07:00:21 PM PDT 24 448387947 ps
T815 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4138301054 Jul 14 07:00:14 PM PDT 24 Jul 14 07:00:20 PM PDT 24 460644287 ps
T816 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3167630421 Jul 14 07:00:19 PM PDT 24 Jul 14 07:00:27 PM PDT 24 488697812 ps
T817 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1506962859 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:24 PM PDT 24 614686895 ps
T818 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3702043931 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:24 PM PDT 24 438845399 ps
T819 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4022986895 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:14 PM PDT 24 546538713 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3107096573 Jul 14 07:00:19 PM PDT 24 Jul 14 07:00:26 PM PDT 24 431076706 ps
T821 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.414739070 Jul 14 07:00:01 PM PDT 24 Jul 14 07:01:39 PM PDT 24 26247075640 ps
T125 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3385949269 Jul 14 07:00:44 PM PDT 24 Jul 14 07:00:47 PM PDT 24 502024919 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.806937044 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:33 PM PDT 24 2348620999 ps
T823 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4168557972 Jul 14 07:00:40 PM PDT 24 Jul 14 07:00:42 PM PDT 24 333330382 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2909339476 Jul 14 07:00:34 PM PDT 24 Jul 14 07:00:40 PM PDT 24 483253072 ps
T825 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1657279325 Jul 14 07:00:12 PM PDT 24 Jul 14 07:00:30 PM PDT 24 4839306512 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4273986529 Jul 14 07:00:14 PM PDT 24 Jul 14 07:00:21 PM PDT 24 863298298 ps
T827 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2637677894 Jul 14 07:00:49 PM PDT 24 Jul 14 07:00:53 PM PDT 24 2758528312 ps
T332 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.845823980 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:39 PM PDT 24 4323143843 ps
T126 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.947618751 Jul 14 06:59:53 PM PDT 24 Jul 14 07:00:01 PM PDT 24 1005707873 ps
T828 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3370589017 Jul 14 07:00:24 PM PDT 24 Jul 14 07:00:30 PM PDT 24 478645270 ps
T829 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2350848025 Jul 14 07:00:14 PM PDT 24 Jul 14 07:00:28 PM PDT 24 2422739022 ps
T830 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3791911177 Jul 14 07:00:13 PM PDT 24 Jul 14 07:00:18 PM PDT 24 534323647 ps
T831 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1007106137 Jul 14 07:00:02 PM PDT 24 Jul 14 07:00:11 PM PDT 24 530950351 ps
T832 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3580884664 Jul 14 07:00:08 PM PDT 24 Jul 14 07:00:18 PM PDT 24 581072025 ps
T127 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.756306477 Jul 14 07:00:17 PM PDT 24 Jul 14 07:00:27 PM PDT 24 1014953743 ps
T833 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3712251893 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:14 PM PDT 24 2725408963 ps
T834 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3407061231 Jul 14 07:00:06 PM PDT 24 Jul 14 07:00:34 PM PDT 24 7672833829 ps
T835 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1898204966 Jul 14 07:00:09 PM PDT 24 Jul 14 07:00:17 PM PDT 24 438012512 ps
T836 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.690206212 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:28 PM PDT 24 435121842 ps
T837 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2760892207 Jul 14 07:00:13 PM PDT 24 Jul 14 07:00:20 PM PDT 24 545565254 ps
T838 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2237652066 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:13 PM PDT 24 564493852 ps
T839 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1529501122 Jul 14 07:00:01 PM PDT 24 Jul 14 07:00:14 PM PDT 24 4789743719 ps
T128 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1637854832 Jul 14 07:00:19 PM PDT 24 Jul 14 07:00:25 PM PDT 24 549096027 ps
T840 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2561132373 Jul 14 06:59:55 PM PDT 24 Jul 14 07:00:05 PM PDT 24 2265868034 ps
T841 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.466351541 Jul 14 07:00:14 PM PDT 24 Jul 14 07:00:23 PM PDT 24 4386037861 ps
T842 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.74997253 Jul 14 07:00:16 PM PDT 24 Jul 14 07:00:23 PM PDT 24 449823586 ps
T843 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1409973061 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:27 PM PDT 24 397401701 ps
T844 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.594506952 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:29 PM PDT 24 307480927 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3095185849 Jul 14 07:00:16 PM PDT 24 Jul 14 07:00:22 PM PDT 24 1169033632 ps
T846 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.390106912 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:28 PM PDT 24 530630193 ps
T847 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2370064427 Jul 14 07:00:42 PM PDT 24 Jul 14 07:00:45 PM PDT 24 520191465 ps
T848 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.238921497 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:24 PM PDT 24 383865871 ps
T849 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.32897228 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:25 PM PDT 24 531103649 ps
T850 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1031301330 Jul 14 07:00:02 PM PDT 24 Jul 14 07:00:15 PM PDT 24 4522904806 ps
T851 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1560988506 Jul 14 07:00:35 PM PDT 24 Jul 14 07:00:38 PM PDT 24 546334007 ps
T852 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3113680893 Jul 14 07:00:07 PM PDT 24 Jul 14 07:00:20 PM PDT 24 4593353624 ps
T853 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3614406989 Jul 14 07:00:25 PM PDT 24 Jul 14 07:00:31 PM PDT 24 527928454 ps
T854 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.192441316 Jul 14 07:00:27 PM PDT 24 Jul 14 07:00:33 PM PDT 24 303402194 ps
T855 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2291197061 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:17 PM PDT 24 600748259 ps
T856 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1967136369 Jul 14 07:00:17 PM PDT 24 Jul 14 07:00:24 PM PDT 24 410387713 ps
T333 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2644796341 Jul 14 06:59:57 PM PDT 24 Jul 14 07:00:16 PM PDT 24 8119584518 ps
T857 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.707552681 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:24 PM PDT 24 342791569 ps
T129 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3131575255 Jul 14 07:00:35 PM PDT 24 Jul 14 07:00:39 PM PDT 24 453891051 ps
T858 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2715494200 Jul 14 07:00:31 PM PDT 24 Jul 14 07:00:35 PM PDT 24 425264843 ps
T859 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3619525374 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:32 PM PDT 24 658322084 ps
T860 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3764082562 Jul 14 07:00:27 PM PDT 24 Jul 14 07:00:32 PM PDT 24 329056111 ps
T861 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.896756488 Jul 14 07:00:05 PM PDT 24 Jul 14 07:00:14 PM PDT 24 291288903 ps
T862 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4146092051 Jul 14 07:00:12 PM PDT 24 Jul 14 07:00:36 PM PDT 24 8450363104 ps
T863 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1244448922 Jul 14 07:00:07 PM PDT 24 Jul 14 07:00:15 PM PDT 24 688884136 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.731641781 Jul 14 07:00:17 PM PDT 24 Jul 14 07:00:24 PM PDT 24 1327778640 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3696591905 Jul 14 07:00:30 PM PDT 24 Jul 14 07:00:36 PM PDT 24 1010253660 ps
T130 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2851416961 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:25 PM PDT 24 354290429 ps
T866 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1870759467 Jul 14 07:00:37 PM PDT 24 Jul 14 07:00:42 PM PDT 24 2343679838 ps
T867 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3563328675 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:26 PM PDT 24 2467157783 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.887766868 Jul 14 07:00:17 PM PDT 24 Jul 14 07:00:23 PM PDT 24 409321226 ps
T131 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2643612353 Jul 14 06:59:57 PM PDT 24 Jul 14 07:00:07 PM PDT 24 684572824 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.577429953 Jul 14 07:00:35 PM PDT 24 Jul 14 07:00:40 PM PDT 24 359672399 ps
T870 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2598800262 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:14 PM PDT 24 459027030 ps
T871 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3466144730 Jul 14 07:00:24 PM PDT 24 Jul 14 07:00:31 PM PDT 24 502326049 ps
T872 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.461251759 Jul 14 06:59:59 PM PDT 24 Jul 14 07:00:09 PM PDT 24 407817462 ps
T873 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3160003464 Jul 14 06:59:55 PM PDT 24 Jul 14 07:00:14 PM PDT 24 8159927420 ps
T874 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2955488443 Jul 14 07:00:20 PM PDT 24 Jul 14 07:00:26 PM PDT 24 311673256 ps
T875 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.146995672 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:24 PM PDT 24 735842618 ps
T876 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2296549253 Jul 14 07:00:03 PM PDT 24 Jul 14 07:00:12 PM PDT 24 343806966 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1773524627 Jul 14 07:00:25 PM PDT 24 Jul 14 07:00:33 PM PDT 24 639278417 ps
T80 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.329812724 Jul 14 06:59:54 PM PDT 24 Jul 14 07:00:06 PM PDT 24 8557077596 ps
T878 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2974321050 Jul 14 07:00:09 PM PDT 24 Jul 14 07:00:30 PM PDT 24 4013617573 ps
T132 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2946842601 Jul 14 07:00:26 PM PDT 24 Jul 14 07:01:04 PM PDT 24 26256963268 ps
T879 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3241802207 Jul 14 07:00:54 PM PDT 24 Jul 14 07:01:01 PM PDT 24 324053568 ps
T133 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1178090507 Jul 14 07:00:00 PM PDT 24 Jul 14 07:00:09 PM PDT 24 589989583 ps
T880 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3365762419 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:30 PM PDT 24 485172139 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.486493597 Jul 14 07:00:02 PM PDT 24 Jul 14 07:00:12 PM PDT 24 424901186 ps
T134 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1414767101 Jul 14 06:59:55 PM PDT 24 Jul 14 07:00:06 PM PDT 24 1005134763 ps
T882 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2876272371 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:31 PM PDT 24 587051896 ps
T883 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2698897165 Jul 14 07:00:29 PM PDT 24 Jul 14 07:00:34 PM PDT 24 430166043 ps
T135 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2225954629 Jul 14 07:00:32 PM PDT 24 Jul 14 07:00:37 PM PDT 24 364528241 ps
T884 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2067822915 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:33 PM PDT 24 2249103164 ps
T885 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.695473689 Jul 14 07:00:12 PM PDT 24 Jul 14 07:00:20 PM PDT 24 4606135234 ps
T886 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.877176795 Jul 14 07:00:01 PM PDT 24 Jul 14 07:00:11 PM PDT 24 536924963 ps
T887 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2544278826 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:24 PM PDT 24 579637024 ps
T888 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.531128652 Jul 14 07:00:46 PM PDT 24 Jul 14 07:00:51 PM PDT 24 430751846 ps
T889 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4162788280 Jul 14 07:00:19 PM PDT 24 Jul 14 07:00:26 PM PDT 24 2934968270 ps
T890 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3395907629 Jul 14 07:00:17 PM PDT 24 Jul 14 07:00:29 PM PDT 24 4378073031 ps
T891 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2512417203 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:30 PM PDT 24 502836104 ps
T892 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1666714208 Jul 14 07:00:31 PM PDT 24 Jul 14 07:00:36 PM PDT 24 425163862 ps
T893 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1110186882 Jul 14 07:00:20 PM PDT 24 Jul 14 07:00:27 PM PDT 24 383560409 ps
T136 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2121584858 Jul 14 06:59:58 PM PDT 24 Jul 14 07:00:07 PM PDT 24 430035547 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.370695144 Jul 14 07:00:19 PM PDT 24 Jul 14 07:00:26 PM PDT 24 426319396 ps
T895 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2449974009 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:25 PM PDT 24 431852757 ps
T896 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1691459752 Jul 14 07:00:22 PM PDT 24 Jul 14 07:00:29 PM PDT 24 431465931 ps
T897 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1192893481 Jul 14 07:00:20 PM PDT 24 Jul 14 07:00:28 PM PDT 24 601074279 ps
T898 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3955026872 Jul 14 07:00:06 PM PDT 24 Jul 14 07:00:14 PM PDT 24 628977749 ps
T899 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3548484354 Jul 14 07:00:07 PM PDT 24 Jul 14 07:00:17 PM PDT 24 5528210061 ps
T900 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1863842799 Jul 14 07:00:18 PM PDT 24 Jul 14 07:00:25 PM PDT 24 518307251 ps
T901 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2378630565 Jul 14 07:00:14 PM PDT 24 Jul 14 07:00:20 PM PDT 24 350605519 ps
T902 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2155574644 Jul 14 07:00:04 PM PDT 24 Jul 14 07:00:14 PM PDT 24 413610324 ps
T137 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2397767378 Jul 14 06:59:58 PM PDT 24 Jul 14 07:00:10 PM PDT 24 816474083 ps
T903 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4061014997 Jul 14 07:00:26 PM PDT 24 Jul 14 07:00:32 PM PDT 24 492812661 ps
T904 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.797504996 Jul 14 07:00:17 PM PDT 24 Jul 14 07:00:26 PM PDT 24 2453249543 ps
T905 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.782432781 Jul 14 07:00:36 PM PDT 24 Jul 14 07:00:39 PM PDT 24 623240645 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.389405500 Jul 14 07:00:17 PM PDT 24 Jul 14 07:00:24 PM PDT 24 748533138 ps
T907 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3960419854 Jul 14 07:00:50 PM PDT 24 Jul 14 07:00:55 PM PDT 24 482305198 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2043774305 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:29 PM PDT 24 379624482 ps
T909 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1371631554 Jul 14 06:59:54 PM PDT 24 Jul 14 07:00:31 PM PDT 24 26664593705 ps
T910 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4134516319 Jul 14 07:00:01 PM PDT 24 Jul 14 07:00:11 PM PDT 24 365219971 ps
T911 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1295950592 Jul 14 06:59:52 PM PDT 24 Jul 14 06:59:54 PM PDT 24 608190162 ps
T912 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2795907837 Jul 14 06:59:56 PM PDT 24 Jul 14 07:00:05 PM PDT 24 596882098 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2579499905 Jul 14 07:00:14 PM PDT 24 Jul 14 07:00:57 PM PDT 24 53285126160 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2573824554 Jul 14 07:00:16 PM PDT 24 Jul 14 07:00:21 PM PDT 24 632674387 ps
T915 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1837037133 Jul 14 07:00:06 PM PDT 24 Jul 14 07:00:14 PM PDT 24 367542288 ps
T916 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2338572864 Jul 14 07:00:42 PM PDT 24 Jul 14 07:00:44 PM PDT 24 294481301 ps
T917 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2578287434 Jul 14 07:00:19 PM PDT 24 Jul 14 07:00:25 PM PDT 24 468463964 ps
T918 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1642646429 Jul 14 07:00:21 PM PDT 24 Jul 14 07:00:29 PM PDT 24 518778538 ps
T919 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2983077416 Jul 14 07:00:27 PM PDT 24 Jul 14 07:00:43 PM PDT 24 4447841449 ps
T920 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1882308385 Jul 14 07:00:36 PM PDT 24 Jul 14 07:00:39 PM PDT 24 506209813 ps

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2919158528
Short name T10
Test name
Test status
Simulation time 624328357932 ps
CPU time 1385.35 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:23:49 PM PDT 24
Peak memory 201976 kb
Host smart-d41046a0-b930-4d23-8ce9-76634c32696a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919158528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2919158528
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.807459133
Short name T2
Test name
Test status
Simulation time 96517881412 ps
CPU time 514.71 seconds
Started Jul 14 07:01:18 PM PDT 24
Finished Jul 14 07:09:57 PM PDT 24
Peak memory 202264 kb
Host smart-4e213145-8d26-4607-a8c3-33896afd9aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807459133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.807459133
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1607563845
Short name T17
Test name
Test status
Simulation time 3183261453003 ps
CPU time 1435.79 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:25:32 PM PDT 24
Peak memory 210592 kb
Host smart-ab97b293-12f7-40d4-87b3-e2c061d209d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607563845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1607563845
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2512556646
Short name T13
Test name
Test status
Simulation time 559749055827 ps
CPU time 319.44 seconds
Started Jul 14 07:01:36 PM PDT 24
Finished Jul 14 07:06:56 PM PDT 24
Peak memory 201900 kb
Host smart-62f66d29-ccdf-497a-a239-3ed325ebb6ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512556646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2512556646
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1423813156
Short name T84
Test name
Test status
Simulation time 493774976363 ps
CPU time 292.32 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:06:57 PM PDT 24
Peak memory 201912 kb
Host smart-23a2b23f-a1e5-4557-a7d7-0ddb53d0230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423813156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1423813156
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2540819989
Short name T168
Test name
Test status
Simulation time 513621794017 ps
CPU time 313 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:06:18 PM PDT 24
Peak memory 201960 kb
Host smart-df4fbf08-e0ca-41d1-8a79-fc6b9bd2326c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540819989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2540819989
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.452262342
Short name T22
Test name
Test status
Simulation time 286189621528 ps
CPU time 336.42 seconds
Started Jul 14 07:00:58 PM PDT 24
Finished Jul 14 07:06:43 PM PDT 24
Peak memory 210580 kb
Host smart-46c367e8-4233-4703-8b92-20d97fc2498b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452262342 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.452262342
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3619118885
Short name T66
Test name
Test status
Simulation time 718094840 ps
CPU time 2.64 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:03 PM PDT 24
Peak memory 201780 kb
Host smart-17038d08-d994-4cd0-8cc3-3a4020e66f99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619118885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3619118885
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1597442493
Short name T161
Test name
Test status
Simulation time 561519080111 ps
CPU time 1111.54 seconds
Started Jul 14 07:02:14 PM PDT 24
Finished Jul 14 07:20:46 PM PDT 24
Peak memory 201912 kb
Host smart-1c5044af-97f8-4c05-839f-a7c232656f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597442493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1597442493
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3766616240
Short name T158
Test name
Test status
Simulation time 490228435707 ps
CPU time 1183.5 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:20:36 PM PDT 24
Peak memory 201960 kb
Host smart-0fc8be16-b8ec-4a72-8034-b6079960f12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766616240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3766616240
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.200012342
Short name T69
Test name
Test status
Simulation time 3997420798 ps
CPU time 8.79 seconds
Started Jul 14 07:00:37 PM PDT 24
Finished Jul 14 07:00:48 PM PDT 24
Peak memory 217124 kb
Host smart-38461760-006b-442b-afab-fcb88cb29584
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200012342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.200012342
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1466212737
Short name T16
Test name
Test status
Simulation time 619118159079 ps
CPU time 213.65 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:04:32 PM PDT 24
Peak memory 201852 kb
Host smart-c734922f-6b1a-4bb6-adc9-dfa6a251acb6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466212737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1466212737
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1948015349
Short name T215
Test name
Test status
Simulation time 553650339773 ps
CPU time 122.84 seconds
Started Jul 14 07:01:06 PM PDT 24
Finished Jul 14 07:03:11 PM PDT 24
Peak memory 201828 kb
Host smart-6dda882b-2d4f-40a9-8501-29e0cdc8ecc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948015349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1948015349
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3836288032
Short name T39
Test name
Test status
Simulation time 406511048724 ps
CPU time 474.53 seconds
Started Jul 14 07:01:36 PM PDT 24
Finished Jul 14 07:09:32 PM PDT 24
Peak memory 211604 kb
Host smart-d3975269-aa31-4d9d-bf72-18838b1e74a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836288032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3836288032
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.83783654
Short name T151
Test name
Test status
Simulation time 359171437480 ps
CPU time 114.48 seconds
Started Jul 14 07:01:05 PM PDT 24
Finished Jul 14 07:03:02 PM PDT 24
Peak memory 201844 kb
Host smart-311adf59-5777-404f-9aaa-17cf57514870
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83783654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gatin
g.83783654
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1983206248
Short name T238
Test name
Test status
Simulation time 348473548445 ps
CPU time 206.43 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 201888 kb
Host smart-9ed40b05-b690-410a-9431-b971e3787b35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983206248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1983206248
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2371932960
Short name T123
Test name
Test status
Simulation time 463537462 ps
CPU time 1.04 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:28 PM PDT 24
Peak memory 201484 kb
Host smart-c3371d21-026a-488b-818a-5106a9556d0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371932960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2371932960
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.883063129
Short name T156
Test name
Test status
Simulation time 342411848016 ps
CPU time 209.67 seconds
Started Jul 14 07:02:58 PM PDT 24
Finished Jul 14 07:06:28 PM PDT 24
Peak memory 202004 kb
Host smart-a9588d65-93ce-4ee4-87e2-1bac232658fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883063129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.883063129
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3510512419
Short name T108
Test name
Test status
Simulation time 511111170627 ps
CPU time 107.7 seconds
Started Jul 14 07:01:04 PM PDT 24
Finished Jul 14 07:02:55 PM PDT 24
Peak memory 201896 kb
Host smart-aa3f7344-e56c-496c-8c8f-fcccdea52ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510512419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3510512419
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.71093344
Short name T157
Test name
Test status
Simulation time 370104791517 ps
CPU time 825.5 seconds
Started Jul 14 07:01:24 PM PDT 24
Finished Jul 14 07:15:11 PM PDT 24
Peak memory 201860 kb
Host smart-6cb2042a-951e-4206-addd-bef0b1e0e5fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71093344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_w
akeup.71093344
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1647134990
Short name T279
Test name
Test status
Simulation time 495982213066 ps
CPU time 277.95 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:06:24 PM PDT 24
Peak memory 201880 kb
Host smart-e2e9d0b1-bd6b-46fc-9867-c1fae4b3de0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647134990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1647134990
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3312480297
Short name T185
Test name
Test status
Simulation time 534612262187 ps
CPU time 229.99 seconds
Started Jul 14 07:01:09 PM PDT 24
Finished Jul 14 07:05:00 PM PDT 24
Peak memory 201796 kb
Host smart-625d62e1-1e04-4651-a78a-d022ed108e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312480297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3312480297
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.582673263
Short name T218
Test name
Test status
Simulation time 772336371794 ps
CPU time 552.5 seconds
Started Jul 14 07:01:40 PM PDT 24
Finished Jul 14 07:10:53 PM PDT 24
Peak memory 202224 kb
Host smart-33d7616f-37f3-44f5-8719-969323f1e87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582673263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
582673263
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.799380761
Short name T182
Test name
Test status
Simulation time 360241650803 ps
CPU time 200.49 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:03:54 PM PDT 24
Peak memory 201908 kb
Host smart-293d0473-4a57-46da-8e86-ea6331fc36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799380761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.799380761
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4099622609
Short name T229
Test name
Test status
Simulation time 515975708754 ps
CPU time 274.77 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:06:04 PM PDT 24
Peak memory 201908 kb
Host smart-a428fc25-7f41-4914-bc72-4a77360b1086
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099622609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4099622609
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3643132195
Short name T179
Test name
Test status
Simulation time 325989720422 ps
CPU time 743.34 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:13:47 PM PDT 24
Peak memory 201956 kb
Host smart-0cd89f04-038f-4aa2-97bf-de0752b8891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643132195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3643132195
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.449470032
Short name T232
Test name
Test status
Simulation time 536157573013 ps
CPU time 752.78 seconds
Started Jul 14 07:01:58 PM PDT 24
Finished Jul 14 07:14:31 PM PDT 24
Peak memory 201892 kb
Host smart-e5a1bdd1-f77f-410c-8f69-b28f209e9222
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449470032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.449470032
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2410806722
Short name T356
Test name
Test status
Simulation time 462269593 ps
CPU time 0.87 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:01:00 PM PDT 24
Peak memory 201656 kb
Host smart-9e048406-01fa-4b44-b5e7-d7fce43ccbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410806722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2410806722
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1194830725
Short name T169
Test name
Test status
Simulation time 489265191837 ps
CPU time 1050.04 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:18:49 PM PDT 24
Peak memory 201960 kb
Host smart-dbc06140-09b1-4fd0-a5c3-d1ad06aa9c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194830725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1194830725
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2741399622
Short name T214
Test name
Test status
Simulation time 216259982154 ps
CPU time 134.98 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:03:23 PM PDT 24
Peak memory 201972 kb
Host smart-c82a3294-f2e2-4919-8afb-db5f2833778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741399622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2741399622
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.902383627
Short name T806
Test name
Test status
Simulation time 7711307973 ps
CPU time 11.49 seconds
Started Jul 14 07:00:23 PM PDT 24
Finished Jul 14 07:00:45 PM PDT 24
Peak memory 201828 kb
Host smart-968ac442-227b-4853-8481-c9f4650e8d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902383627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.902383627
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1717593107
Short name T53
Test name
Test status
Simulation time 367449616377 ps
CPU time 390.16 seconds
Started Jul 14 07:01:53 PM PDT 24
Finished Jul 14 07:08:23 PM PDT 24
Peak memory 201916 kb
Host smart-5a37c19c-c523-466f-96fb-9d5b2c1706c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717593107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1717593107
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2120526204
Short name T210
Test name
Test status
Simulation time 534750811928 ps
CPU time 337.67 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 201896 kb
Host smart-38d4987b-4c6c-4304-9e8d-3d47d1a741d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120526204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2120526204
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2430281991
Short name T52
Test name
Test status
Simulation time 24529494769 ps
CPU time 19.05 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:01:30 PM PDT 24
Peak memory 211284 kb
Host smart-3e2805be-3409-42a6-9a84-787583ca93e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430281991 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2430281991
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.4188181595
Short name T295
Test name
Test status
Simulation time 326064049858 ps
CPU time 62.72 seconds
Started Jul 14 07:01:04 PM PDT 24
Finished Jul 14 07:02:10 PM PDT 24
Peak memory 201884 kb
Host smart-3116c92a-1fa0-4c1a-af80-4e333b1b5297
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188181595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.4188181595
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.475062435
Short name T286
Test name
Test status
Simulation time 339482101812 ps
CPU time 784.76 seconds
Started Jul 14 07:02:49 PM PDT 24
Finished Jul 14 07:15:54 PM PDT 24
Peak memory 201808 kb
Host smart-0ad92865-8892-4080-bc17-3aeaf8d5cc1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475062435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.475062435
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2093870504
Short name T300
Test name
Test status
Simulation time 513223071891 ps
CPU time 1012.06 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:18:12 PM PDT 24
Peak memory 201904 kb
Host smart-5d002b6a-88c7-4091-9746-9271f3ac0ed2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093870504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2093870504
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.842103221
Short name T303
Test name
Test status
Simulation time 431660637542 ps
CPU time 1258.78 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:21:27 PM PDT 24
Peak memory 212624 kb
Host smart-2f64c0fb-e2ce-4f52-bd83-255354c10322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842103221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.842103221
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1102447636
Short name T234
Test name
Test status
Simulation time 329914256800 ps
CPU time 60.06 seconds
Started Jul 14 07:01:55 PM PDT 24
Finished Jul 14 07:02:56 PM PDT 24
Peak memory 201912 kb
Host smart-f2ce81ad-ea98-40a8-a378-c9b697e9bea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102447636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1102447636
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1510858338
Short name T139
Test name
Test status
Simulation time 4665469346 ps
CPU time 10.51 seconds
Started Jul 14 07:00:27 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 201764 kb
Host smart-83a77a88-f6f5-4d46-9653-32610ddfa9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510858338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1510858338
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3192080283
Short name T266
Test name
Test status
Simulation time 336961654986 ps
CPU time 131.73 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:03:20 PM PDT 24
Peak memory 201968 kb
Host smart-4ce0f907-31e4-41ab-9194-3ac8944a61a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192080283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3192080283
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2278851565
Short name T226
Test name
Test status
Simulation time 489227058092 ps
CPU time 432.37 seconds
Started Jul 14 07:01:43 PM PDT 24
Finished Jul 14 07:08:56 PM PDT 24
Peak memory 201892 kb
Host smart-f1973152-5618-4454-9f1d-1917d2d3ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278851565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2278851565
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1405390327
Short name T249
Test name
Test status
Simulation time 574663677402 ps
CPU time 337.49 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:06:32 PM PDT 24
Peak memory 201840 kb
Host smart-4947be78-3a6b-4d6b-8108-351755efeb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405390327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1405390327
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4194883243
Short name T203
Test name
Test status
Simulation time 495957894300 ps
CPU time 1224.47 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:20:51 PM PDT 24
Peak memory 201952 kb
Host smart-dec1633e-de21-440e-ba24-785af2d6ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194883243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4194883243
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3809523567
Short name T374
Test name
Test status
Simulation time 321755465923 ps
CPU time 691.47 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:12:42 PM PDT 24
Peak memory 201852 kb
Host smart-db37418c-6dca-4ac1-97e3-a0fb920fd4cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809523567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3809523567
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2098116938
Short name T170
Test name
Test status
Simulation time 500380563359 ps
CPU time 316.3 seconds
Started Jul 14 07:01:54 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 201804 kb
Host smart-cfc05e76-7d9c-4551-9dfa-3321e1e51ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098116938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2098116938
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2755830823
Short name T48
Test name
Test status
Simulation time 133975476844 ps
CPU time 72.88 seconds
Started Jul 14 07:03:00 PM PDT 24
Finished Jul 14 07:04:13 PM PDT 24
Peak memory 210284 kb
Host smart-e0a7cacf-4c59-4aac-9835-c0e9246ac61b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755830823 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2755830823
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.477095046
Short name T14
Test name
Test status
Simulation time 438091508155 ps
CPU time 761.07 seconds
Started Jul 14 07:01:06 PM PDT 24
Finished Jul 14 07:13:49 PM PDT 24
Peak memory 202028 kb
Host smart-8e4e24d1-e5ea-4e92-9179-b79ad61d051c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477095046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.477095046
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2624462881
Short name T261
Test name
Test status
Simulation time 372297756561 ps
CPU time 100.75 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:02:38 PM PDT 24
Peak memory 201896 kb
Host smart-0b5aae44-d7bd-45c4-8e13-1652a95222d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624462881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2624462881
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1653057041
Short name T243
Test name
Test status
Simulation time 612501375087 ps
CPU time 272.54 seconds
Started Jul 14 07:01:46 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 201820 kb
Host smart-15157ab2-ce46-4007-99b1-24066e3be777
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653057041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1653057041
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.173469157
Short name T58
Test name
Test status
Simulation time 111950855264 ps
CPU time 396.24 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 202220 kb
Host smart-546ab46f-ad4f-4dd2-8e44-661a819e89d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173469157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.173469157
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.142018262
Short name T289
Test name
Test status
Simulation time 500192668927 ps
CPU time 604.21 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:11:23 PM PDT 24
Peak memory 201880 kb
Host smart-7e911671-e210-411c-9772-6d2a0c0e479f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142018262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.142018262
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.323072222
Short name T255
Test name
Test status
Simulation time 4479390195723 ps
CPU time 1093.93 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:20:02 PM PDT 24
Peak memory 210420 kb
Host smart-71b9e53d-d2b2-4f5a-a3de-0bc0b90067ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323072222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
323072222
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3868439356
Short name T118
Test name
Test status
Simulation time 513968270366 ps
CPU time 589.08 seconds
Started Jul 14 07:01:59 PM PDT 24
Finished Jul 14 07:11:48 PM PDT 24
Peak memory 201796 kb
Host smart-1d7434c3-14dd-46f1-bb4c-cc61731df2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868439356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3868439356
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1201174206
Short name T187
Test name
Test status
Simulation time 562747595727 ps
CPU time 212.97 seconds
Started Jul 14 07:02:08 PM PDT 24
Finished Jul 14 07:05:42 PM PDT 24
Peak memory 201864 kb
Host smart-7f664f2f-3ece-4d63-bb3d-e194cd29845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201174206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1201174206
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.700844514
Short name T325
Test name
Test status
Simulation time 67377865568 ps
CPU time 78.68 seconds
Started Jul 14 07:02:32 PM PDT 24
Finished Jul 14 07:03:52 PM PDT 24
Peak memory 210556 kb
Host smart-2b1ecfcf-4ad4-498b-8bfc-008323a721cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700844514 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.700844514
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3350256156
Short name T153
Test name
Test status
Simulation time 344440152471 ps
CPU time 198.72 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:04:17 PM PDT 24
Peak memory 201860 kb
Host smart-2176d221-4a56-4f50-acb5-b52a26e98e45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350256156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3350256156
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.280084230
Short name T250
Test name
Test status
Simulation time 330075657462 ps
CPU time 92.32 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:02:52 PM PDT 24
Peak memory 201920 kb
Host smart-870ae2a3-bd13-4f07-b14c-96aeb9705b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280084230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.280084230
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1417124043
Short name T221
Test name
Test status
Simulation time 486165526527 ps
CPU time 1103.51 seconds
Started Jul 14 07:01:20 PM PDT 24
Finished Jul 14 07:19:47 PM PDT 24
Peak memory 201920 kb
Host smart-03c68d5c-0da6-4d75-8309-f94ae2217f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417124043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1417124043
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.885575711
Short name T239
Test name
Test status
Simulation time 172260182949 ps
CPU time 415.58 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:08:21 PM PDT 24
Peak memory 201872 kb
Host smart-aab185ef-0515-44f7-bd8d-68911ab4e804
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885575711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.885575711
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3336218353
Short name T290
Test name
Test status
Simulation time 538465786740 ps
CPU time 1103.51 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 201968 kb
Host smart-ee97ee2c-37de-45a8-9ee0-a62aae8a0e03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336218353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3336218353
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3922996595
Short name T312
Test name
Test status
Simulation time 441591222387 ps
CPU time 740.11 seconds
Started Jul 14 07:01:18 PM PDT 24
Finished Jul 14 07:13:42 PM PDT 24
Peak memory 201876 kb
Host smart-5146d6d5-a022-4dd7-b051-cef8612987af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922996595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3922996595
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1298421118
Short name T222
Test name
Test status
Simulation time 488916113812 ps
CPU time 1024.03 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:18:23 PM PDT 24
Peak memory 201916 kb
Host smart-bf342ad4-252b-4c74-9446-3b70f43baf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298421118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1298421118
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3988039919
Short name T314
Test name
Test status
Simulation time 496158916389 ps
CPU time 283.1 seconds
Started Jul 14 07:02:05 PM PDT 24
Finished Jul 14 07:06:49 PM PDT 24
Peak memory 201976 kb
Host smart-8017f3c3-4e2e-4040-9c7f-99dd6cd665ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988039919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3988039919
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.329812724
Short name T80
Test name
Test status
Simulation time 8557077596 ps
CPU time 7.37 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:06 PM PDT 24
Peak memory 201868 kb
Host smart-9c687f5e-dc75-4065-b49e-cb1d7dffa577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329812724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.329812724
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2777691809
Short name T331
Test name
Test status
Simulation time 4412952098 ps
CPU time 11.33 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:33 PM PDT 24
Peak memory 201844 kb
Host smart-8c358b25-d9b7-472b-a2bf-69471ecfd4fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777691809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2777691809
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3962158236
Short name T62
Test name
Test status
Simulation time 8784745649 ps
CPU time 22.47 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:00:56 PM PDT 24
Peak memory 201848 kb
Host smart-8d8e2aed-4393-4aa1-a2bf-4b10e5acc406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962158236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3962158236
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4111607409
Short name T776
Test name
Test status
Simulation time 126282725964 ps
CPU time 697.55 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:12:12 PM PDT 24
Peak memory 202224 kb
Host smart-33412181-e818-4f25-98ce-ea446e5e37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111607409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4111607409
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1139196021
Short name T173
Test name
Test status
Simulation time 332667310852 ps
CPU time 764.95 seconds
Started Jul 14 07:01:00 PM PDT 24
Finished Jul 14 07:13:50 PM PDT 24
Peak memory 201976 kb
Host smart-44b54d56-beff-4c93-9095-6fb48c3dadbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139196021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1139196021
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.538165695
Short name T335
Test name
Test status
Simulation time 372822492775 ps
CPU time 1486.98 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:25:44 PM PDT 24
Peak memory 202152 kb
Host smart-a76e7cbe-9f8c-4d8b-a088-062276cd3997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538165695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
538165695
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1126335229
Short name T337
Test name
Test status
Simulation time 86095128165 ps
CPU time 438.28 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:08:17 PM PDT 24
Peak memory 202208 kb
Host smart-b397be67-b36d-4da2-946e-7fc7f651d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126335229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1126335229
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2969691348
Short name T299
Test name
Test status
Simulation time 378257397925 ps
CPU time 112.69 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:03:08 PM PDT 24
Peak memory 210656 kb
Host smart-75194777-13e3-4f3c-8f12-150e99b1716d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969691348 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2969691348
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1587730925
Short name T104
Test name
Test status
Simulation time 621690431675 ps
CPU time 220.37 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:04:45 PM PDT 24
Peak memory 201852 kb
Host smart-cfbcae04-3883-4425-9160-f86b37adeaf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587730925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1587730925
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1322195438
Short name T517
Test name
Test status
Simulation time 81220219241 ps
CPU time 409.24 seconds
Started Jul 14 07:01:20 PM PDT 24
Finished Jul 14 07:08:12 PM PDT 24
Peak memory 202224 kb
Host smart-a8cb8c79-8b67-4e33-9d2b-ea89ceaf864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322195438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1322195438
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2941509739
Short name T204
Test name
Test status
Simulation time 332526052519 ps
CPU time 165.77 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:04:06 PM PDT 24
Peak memory 210676 kb
Host smart-4b330442-6687-413b-abd1-2c8661974cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941509739 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2941509739
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1790017302
Short name T21
Test name
Test status
Simulation time 126751022707 ps
CPU time 416.59 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:08:26 PM PDT 24
Peak memory 210408 kb
Host smart-4e73d62a-d0c0-4660-95e1-92e2e21ffcf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790017302 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1790017302
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.914670908
Short name T287
Test name
Test status
Simulation time 520520910705 ps
CPU time 1223.71 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:22:12 PM PDT 24
Peak memory 201868 kb
Host smart-1eea8982-1647-4619-9b0a-5230c5f82722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914670908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.914670908
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1388973170
Short name T280
Test name
Test status
Simulation time 385777443926 ps
CPU time 824.97 seconds
Started Jul 14 07:01:58 PM PDT 24
Finished Jul 14 07:15:43 PM PDT 24
Peak memory 201904 kb
Host smart-2f9db276-b534-4191-9c7d-942386ada295
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388973170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1388973170
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1317790305
Short name T317
Test name
Test status
Simulation time 138395503491 ps
CPU time 209.43 seconds
Started Jul 14 07:02:41 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 210548 kb
Host smart-2e11d718-fc35-4069-bb65-b182bf424273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317790305 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1317790305
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.756306477
Short name T127
Test name
Test status
Simulation time 1014953743 ps
CPU time 5.78 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:27 PM PDT 24
Peak memory 201668 kb
Host smart-5696a015-ebbd-4dce-9e0b-103a35a901d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756306477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.756306477
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1371631554
Short name T909
Test name
Test status
Simulation time 26664593705 ps
CPU time 32.69 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 201820 kb
Host smart-f46cc7b2-336c-458a-aa08-03ecefd5f0fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371631554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1371631554
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1506962859
Short name T817
Test name
Test status
Simulation time 614686895 ps
CPU time 2.13 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201524 kb
Host smart-7fee6c36-e0d3-414a-8be5-e0153dfed5a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506962859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1506962859
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2573824554
Short name T914
Test name
Test status
Simulation time 632674387 ps
CPU time 1.07 seconds
Started Jul 14 07:00:16 PM PDT 24
Finished Jul 14 07:00:21 PM PDT 24
Peak memory 201572 kb
Host smart-fe5b0993-4283-4c6d-a769-d75dfce45899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573824554 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2573824554
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1295950592
Short name T911
Test name
Test status
Simulation time 608190162 ps
CPU time 0.94 seconds
Started Jul 14 06:59:52 PM PDT 24
Finished Jul 14 06:59:54 PM PDT 24
Peak memory 201432 kb
Host smart-85297d84-4937-475d-99b3-4e1ea2470fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295950592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1295950592
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2378630565
Short name T901
Test name
Test status
Simulation time 350605519 ps
CPU time 0.84 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 201348 kb
Host smart-45d08475-22b6-46b8-b906-0d3ee8356750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378630565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2378630565
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2561132373
Short name T840
Test name
Test status
Simulation time 2265868034 ps
CPU time 3.22 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 201608 kb
Host smart-44ff3609-b551-47ff-be3e-4130713946e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561132373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2561132373
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1414767101
Short name T134
Test name
Test status
Simulation time 1005134763 ps
CPU time 4.2 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:06 PM PDT 24
Peak memory 201692 kb
Host smart-13b7d7c1-5e16-4d72-b0e4-98e61b1b206c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414767101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1414767101
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2579499905
Short name T913
Test name
Test status
Simulation time 53285126160 ps
CPU time 39.05 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:57 PM PDT 24
Peak memory 201876 kb
Host smart-d336ad33-de58-4490-8318-653fe59d0a42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579499905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2579499905
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3095185849
Short name T845
Test name
Test status
Simulation time 1169033632 ps
CPU time 1.05 seconds
Started Jul 14 07:00:16 PM PDT 24
Finished Jul 14 07:00:22 PM PDT 24
Peak memory 201528 kb
Host smart-15e73e20-4fef-48e6-adf8-4f15b6c07f10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095185849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3095185849
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.279524035
Short name T810
Test name
Test status
Simulation time 622070155 ps
CPU time 1.68 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:06 PM PDT 24
Peak memory 209952 kb
Host smart-9b083e89-8b76-4d61-aab0-7ff6bd1ba696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279524035 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.279524035
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2225954629
Short name T135
Test name
Test status
Simulation time 364528241 ps
CPU time 1.76 seconds
Started Jul 14 07:00:32 PM PDT 24
Finished Jul 14 07:00:37 PM PDT 24
Peak memory 201484 kb
Host smart-dabc1bb5-a03a-4b0d-ba4e-c9b8c39d046c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225954629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2225954629
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1967136369
Short name T856
Test name
Test status
Simulation time 410387713 ps
CPU time 1.59 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201412 kb
Host smart-539dc606-1e22-4f91-ae46-e5bc1eab11ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967136369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1967136369
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2493222984
Short name T809
Test name
Test status
Simulation time 462762550 ps
CPU time 2.68 seconds
Started Jul 14 07:00:15 PM PDT 24
Finished Jul 14 07:00:22 PM PDT 24
Peak memory 211008 kb
Host smart-8aae67b8-5bbc-4a8e-966e-580189bbd12b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493222984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2493222984
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2237652066
Short name T838
Test name
Test status
Simulation time 564493852 ps
CPU time 1.31 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:13 PM PDT 24
Peak memory 201552 kb
Host smart-7557952b-716e-4f8b-b209-00c25d6792c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237652066 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2237652066
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1061061172
Short name T124
Test name
Test status
Simulation time 448387947 ps
CPU time 1.88 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:21 PM PDT 24
Peak memory 201700 kb
Host smart-80881691-19ba-4650-a531-5e3d51e614f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061061172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1061061172
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1007106137
Short name T831
Test name
Test status
Simulation time 530950351 ps
CPU time 0.94 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:11 PM PDT 24
Peak memory 201392 kb
Host smart-845d2aef-f55f-46ed-a35d-64c722509a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007106137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1007106137
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3712251893
Short name T833
Test name
Test status
Simulation time 2725408963 ps
CPU time 1.95 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201800 kb
Host smart-2ac0bbb7-8c1c-434c-8df8-90fb546cd5a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712251893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3712251893
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3167630421
Short name T816
Test name
Test status
Simulation time 488697812 ps
CPU time 2.43 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:27 PM PDT 24
Peak memory 201784 kb
Host smart-bc5b6fb4-e8a8-462b-a24f-370cdf1e0829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167630421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3167630421
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2318815573
Short name T64
Test name
Test status
Simulation time 4404961849 ps
CPU time 3.93 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 201596 kb
Host smart-4b6ccaf0-0773-4444-973b-1b93ada5339f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318815573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2318815573
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2544278826
Short name T887
Test name
Test status
Simulation time 579637024 ps
CPU time 1.45 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201580 kb
Host smart-58fbd90c-97e1-426a-a24f-9c437db7254d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544278826 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2544278826
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.877176795
Short name T886
Test name
Test status
Simulation time 536924963 ps
CPU time 2.01 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:00:11 PM PDT 24
Peak memory 201496 kb
Host smart-c0a5839c-829c-4715-9fa2-2a3c2b5336b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877176795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.877176795
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2598800262
Short name T870
Test name
Test status
Simulation time 459027030 ps
CPU time 1.65 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201392 kb
Host smart-53006042-ec0c-4b43-9abd-420e2f88f099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598800262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2598800262
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2067822915
Short name T884
Test name
Test status
Simulation time 2249103164 ps
CPU time 9.24 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:33 PM PDT 24
Peak memory 201616 kb
Host smart-e2040fa8-2311-4b6d-93ba-01f7a5c1e338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067822915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2067822915
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2155574644
Short name T902
Test name
Test status
Simulation time 413610324 ps
CPU time 2.12 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201744 kb
Host smart-868b27c6-a369-4c90-ab2c-54e385290509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155574644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2155574644
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4146092051
Short name T862
Test name
Test status
Simulation time 8450363104 ps
CPU time 19.57 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:36 PM PDT 24
Peak memory 201896 kb
Host smart-b9c324f0-d06d-4be6-a59d-b571d4756033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146092051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.4146092051
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4134516319
Short name T910
Test name
Test status
Simulation time 365219971 ps
CPU time 1.13 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:00:11 PM PDT 24
Peak memory 201552 kb
Host smart-24ac5bfd-d683-4f4e-b44d-0bf25eadfca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134516319 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4134516319
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1244448922
Short name T863
Test name
Test status
Simulation time 688884136 ps
CPU time 0.93 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:15 PM PDT 24
Peak memory 201280 kb
Host smart-6edc3722-2176-4ea9-96c0-2e50283e65ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244448922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1244448922
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3702043931
Short name T818
Test name
Test status
Simulation time 438845399 ps
CPU time 0.9 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201452 kb
Host smart-ac6f6060-4497-46cb-965c-7208569fb7a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702043931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3702043931
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2883382866
Short name T60
Test name
Test status
Simulation time 2738021416 ps
CPU time 11.31 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:23 PM PDT 24
Peak memory 201592 kb
Host smart-adce0ca7-80cb-45c2-a473-64fb7f9aa1fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883382866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2883382866
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.577429953
Short name T869
Test name
Test status
Simulation time 359672399 ps
CPU time 2.21 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:00:40 PM PDT 24
Peak memory 201772 kb
Host smart-75b23be4-7aa2-4fc6-985e-76fdc7b98cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577429953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.577429953
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3113680893
Short name T852
Test name
Test status
Simulation time 4593353624 ps
CPU time 6.37 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 201780 kb
Host smart-f5c3ffe6-b1f8-40d9-b0cb-63448a5437b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113680893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3113680893
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4022986895
Short name T819
Test name
Test status
Simulation time 546538713 ps
CPU time 1.98 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201528 kb
Host smart-8f48c7e8-0a2f-4d04-8837-e3ee6b15f05e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022986895 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4022986895
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1637854832
Short name T128
Test name
Test status
Simulation time 549096027 ps
CPU time 1.29 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201500 kb
Host smart-405f25d4-0789-49a7-a3d6-51f40a5b866b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637854832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1637854832
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1409973061
Short name T843
Test name
Test status
Simulation time 397401701 ps
CPU time 0.71 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:27 PM PDT 24
Peak memory 201416 kb
Host smart-6fbb3565-db32-4f2f-9911-d0df554969d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409973061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1409973061
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1870759467
Short name T866
Test name
Test status
Simulation time 2343679838 ps
CPU time 3.53 seconds
Started Jul 14 07:00:37 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 201576 kb
Host smart-3f77fcae-7055-4fc7-b627-2d496e888c72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870759467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1870759467
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2876272371
Short name T882
Test name
Test status
Simulation time 587051896 ps
CPU time 3.08 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 217928 kb
Host smart-32a18e28-a0ce-4908-b58f-4b0a15d43285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876272371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2876272371
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3107096573
Short name T820
Test name
Test status
Simulation time 431076706 ps
CPU time 1.28 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 209712 kb
Host smart-58b16369-b172-4659-9eab-e9474be6d368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107096573 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3107096573
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.390106912
Short name T846
Test name
Test status
Simulation time 530630193 ps
CPU time 1.11 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:28 PM PDT 24
Peak memory 201384 kb
Host smart-c7c98e1c-1792-4380-ae5f-7f4ff6e4d85b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390106912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.390106912
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2566764089
Short name T802
Test name
Test status
Simulation time 493100831 ps
CPU time 1.72 seconds
Started Jul 14 07:00:09 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 201420 kb
Host smart-05e11742-3015-4203-b478-41c471dd546b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566764089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2566764089
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3563328675
Short name T867
Test name
Test status
Simulation time 2467157783 ps
CPU time 3.34 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 201632 kb
Host smart-5982fcb4-ff89-4797-8439-e47c50cdda6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563328675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3563328675
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3076223089
Short name T67
Test name
Test status
Simulation time 1001026132 ps
CPU time 2.04 seconds
Started Jul 14 07:00:16 PM PDT 24
Finished Jul 14 07:00:22 PM PDT 24
Peak memory 201816 kb
Host smart-450d5f7a-5c47-48f8-8325-581c91a9f186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076223089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3076223089
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.949213171
Short name T68
Test name
Test status
Simulation time 4387388854 ps
CPU time 6.38 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:21 PM PDT 24
Peak memory 201704 kb
Host smart-5cd378e2-ed31-4490-8996-6961d90a6368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949213171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.949213171
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2997960685
Short name T72
Test name
Test status
Simulation time 472373445 ps
CPU time 2.07 seconds
Started Jul 14 07:00:29 PM PDT 24
Finished Jul 14 07:00:35 PM PDT 24
Peak memory 201760 kb
Host smart-fb81796b-f558-4227-8cca-50482b55779a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997960685 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2997960685
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2851416961
Short name T130
Test name
Test status
Simulation time 354290429 ps
CPU time 1.52 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201472 kb
Host smart-9638e096-78ff-481d-a7e0-9b67a5fe91b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851416961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2851416961
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1823482211
Short name T814
Test name
Test status
Simulation time 520901254 ps
CPU time 1.62 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201440 kb
Host smart-fbefac5a-4703-486c-808e-744a08f8c0be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823482211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1823482211
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1659755490
Short name T141
Test name
Test status
Simulation time 2184881851 ps
CPU time 8.4 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:23 PM PDT 24
Peak memory 201604 kb
Host smart-ece9c4ed-3749-4fee-8897-ffd27b8efbf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659755490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1659755490
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3091348148
Short name T79
Test name
Test status
Simulation time 982151890 ps
CPU time 1.67 seconds
Started Jul 14 07:00:13 PM PDT 24
Finished Jul 14 07:00:19 PM PDT 24
Peak memory 201764 kb
Host smart-5772f738-b0b8-4714-8053-89c2e50f578d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091348148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3091348148
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.695473689
Short name T885
Test name
Test status
Simulation time 4606135234 ps
CPU time 3.19 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 201808 kb
Host smart-f5dd4394-e33a-404b-a491-924f3c4cbf1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695473689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.695473689
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1192893481
Short name T897
Test name
Test status
Simulation time 601074279 ps
CPU time 2.29 seconds
Started Jul 14 07:00:20 PM PDT 24
Finished Jul 14 07:00:28 PM PDT 24
Peak memory 201568 kb
Host smart-c770830f-143b-4044-bfa1-d073152a6754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192893481 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1192893481
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1352513523
Short name T143
Test name
Test status
Simulation time 378718145 ps
CPU time 1.57 seconds
Started Jul 14 07:00:31 PM PDT 24
Finished Jul 14 07:00:36 PM PDT 24
Peak memory 201464 kb
Host smart-c2e8d85c-3c07-4be8-acbe-5c7245767a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352513523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1352513523
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.896756488
Short name T861
Test name
Test status
Simulation time 291288903 ps
CPU time 1.3 seconds
Started Jul 14 07:00:05 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201388 kb
Host smart-34f2c714-e1e7-4790-a4d1-c26215173bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896756488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.896756488
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2974321050
Short name T878
Test name
Test status
Simulation time 4013617573 ps
CPU time 14.32 seconds
Started Jul 14 07:00:09 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 201836 kb
Host smart-d9a6da78-640e-47a9-9d02-7ea1a4db0064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974321050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2974321050
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3241802207
Short name T879
Test name
Test status
Simulation time 324053568 ps
CPU time 1.76 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:01:01 PM PDT 24
Peak memory 201740 kb
Host smart-01a5414c-328b-4d75-b27a-6f75de3ba7fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241802207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3241802207
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2983077416
Short name T919
Test name
Test status
Simulation time 4447841449 ps
CPU time 11.59 seconds
Started Jul 14 07:00:27 PM PDT 24
Finished Jul 14 07:00:43 PM PDT 24
Peak memory 201824 kb
Host smart-88d5547e-04c3-4dc9-9038-1a2456e1a0b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983077416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2983077416
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.690206212
Short name T836
Test name
Test status
Simulation time 435121842 ps
CPU time 1.22 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:28 PM PDT 24
Peak memory 201576 kb
Host smart-7de02dff-9593-44dd-b632-e557a6e0374f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690206212 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.690206212
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.594506952
Short name T844
Test name
Test status
Simulation time 307480927 ps
CPU time 1.33 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201444 kb
Host smart-f74b0962-5f44-472d-8e1b-6519a99dda36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594506952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.594506952
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2637677894
Short name T827
Test name
Test status
Simulation time 2758528312 ps
CPU time 1.46 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:00:53 PM PDT 24
Peak memory 201632 kb
Host smart-3876d12e-806a-4cfa-9641-27320b65c155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637677894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2637677894
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3096723554
Short name T65
Test name
Test status
Simulation time 427926805 ps
CPU time 2.61 seconds
Started Jul 14 07:00:06 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 201804 kb
Host smart-51c7dda8-0320-4076-9952-6bba30c80b58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096723554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3096723554
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3407061231
Short name T834
Test name
Test status
Simulation time 7672833829 ps
CPU time 20.31 seconds
Started Jul 14 07:00:06 PM PDT 24
Finished Jul 14 07:00:34 PM PDT 24
Peak memory 201836 kb
Host smart-42359817-a0ad-4967-8773-a14196ce46e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407061231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3407061231
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.531128652
Short name T888
Test name
Test status
Simulation time 430751846 ps
CPU time 1.42 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:00:51 PM PDT 24
Peak memory 201580 kb
Host smart-ec44e50b-eef3-42b7-b661-2260d767d5d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531128652 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.531128652
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3131575255
Short name T129
Test name
Test status
Simulation time 453891051 ps
CPU time 1.79 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:00:39 PM PDT 24
Peak memory 201476 kb
Host smart-381dae2c-a8db-42a0-bee7-370f74b7a2f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131575255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3131575255
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2955488443
Short name T874
Test name
Test status
Simulation time 311673256 ps
CPU time 0.99 seconds
Started Jul 14 07:00:20 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 201624 kb
Host smart-70d6931e-a6ce-406c-b43c-ba6ed598c19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955488443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2955488443
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2350848025
Short name T829
Test name
Test status
Simulation time 2422739022 ps
CPU time 10.02 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:28 PM PDT 24
Peak memory 201624 kb
Host smart-7988d2e1-79a1-4d0c-8d5b-0c555b2ff733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350848025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2350848025
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2909339476
Short name T824
Test name
Test status
Simulation time 483253072 ps
CPU time 3.2 seconds
Started Jul 14 07:00:34 PM PDT 24
Finished Jul 14 07:00:40 PM PDT 24
Peak memory 210024 kb
Host smart-476101ce-0b93-4b63-804e-d22afe78c5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909339476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2909339476
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4184154649
Short name T103
Test name
Test status
Simulation time 632110842 ps
CPU time 1.08 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201564 kb
Host smart-dc112d0a-9224-4168-a136-284b5a82d74b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184154649 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.4184154649
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3385949269
Short name T125
Test name
Test status
Simulation time 502024919 ps
CPU time 1.06 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:00:47 PM PDT 24
Peak memory 201500 kb
Host smart-3493f736-aed3-4d54-9841-8c12e4ff8ce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385949269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3385949269
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2578287434
Short name T917
Test name
Test status
Simulation time 468463964 ps
CPU time 0.88 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201408 kb
Host smart-375e0fd9-ac6d-4ac2-9331-f16f62ef4011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578287434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2578287434
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2211311303
Short name T140
Test name
Test status
Simulation time 2142369525 ps
CPU time 10.62 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:23 PM PDT 24
Peak memory 201480 kb
Host smart-8bf9a5b9-4a17-4452-94a9-794e4d907dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211311303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2211311303
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3580884664
Short name T832
Test name
Test status
Simulation time 581072025 ps
CPU time 3.67 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 210944 kb
Host smart-f6fde588-a9aa-47da-bcf1-109cb5e33be9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580884664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3580884664
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1657279325
Short name T825
Test name
Test status
Simulation time 4839306512 ps
CPU time 12.84 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 201780 kb
Host smart-83ccebf3-8d28-4af8-8ab2-fd939915012d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657279325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1657279325
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2397767378
Short name T137
Test name
Test status
Simulation time 816474083 ps
CPU time 4.19 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 201876 kb
Host smart-074cf728-848c-4941-954f-313612309b41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397767378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2397767378
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.414739070
Short name T821
Test name
Test status
Simulation time 26247075640 ps
CPU time 89.56 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:01:39 PM PDT 24
Peak memory 201804 kb
Host smart-f087e1e7-51f9-4be0-875f-73910dad6c13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414739070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.414739070
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.731641781
Short name T864
Test name
Test status
Simulation time 1327778640 ps
CPU time 2.17 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201552 kb
Host smart-436a9467-81d9-4434-9e70-6328845b87bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731641781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.731641781
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.879706956
Short name T807
Test name
Test status
Simulation time 622193549 ps
CPU time 0.94 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:00 PM PDT 24
Peak memory 201540 kb
Host smart-55089b65-ca9c-48bf-a2a7-7f272f30e8d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879706956 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.879706956
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.370695144
Short name T894
Test name
Test status
Simulation time 426319396 ps
CPU time 1.14 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 201452 kb
Host smart-e809644c-0293-40cb-b20c-4c3823e282bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370695144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.370695144
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2855086189
Short name T813
Test name
Test status
Simulation time 483117356 ps
CPU time 1.83 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201356 kb
Host smart-8f5b3061-4ecc-4614-b508-a7983a66caa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855086189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2855086189
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.797504996
Short name T904
Test name
Test status
Simulation time 2453249543 ps
CPU time 4.18 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 201632 kb
Host smart-de6941f1-37a9-4b29-a432-0fbc18e186e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797504996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.797504996
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2795907837
Short name T912
Test name
Test status
Simulation time 596882098 ps
CPU time 2.12 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 201804 kb
Host smart-9559dd02-b93a-4bc7-afcb-d72a5e0ea44b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795907837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2795907837
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2644796341
Short name T333
Test name
Test status
Simulation time 8119584518 ps
CPU time 11.72 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 201812 kb
Host smart-82d68fc7-3f4c-40ab-8d68-ab6d41f33239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644796341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2644796341
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4168557972
Short name T823
Test name
Test status
Simulation time 333330382 ps
CPU time 1.02 seconds
Started Jul 14 07:00:40 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 201416 kb
Host smart-07126e4d-4b5c-4ffe-8ba8-5f5edbd3d401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168557972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4168557972
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3791911177
Short name T830
Test name
Test status
Simulation time 534323647 ps
CPU time 0.91 seconds
Started Jul 14 07:00:13 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 201400 kb
Host smart-e06bc61e-a706-4d29-8323-409a0527ea86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791911177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3791911177
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1837037133
Short name T915
Test name
Test status
Simulation time 367542288 ps
CPU time 0.84 seconds
Started Jul 14 07:00:06 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201420 kb
Host smart-8a8504a4-bcea-4398-b0a7-f9c07e1c0213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837037133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1837037133
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.782432781
Short name T905
Test name
Test status
Simulation time 623240645 ps
CPU time 0.72 seconds
Started Jul 14 07:00:36 PM PDT 24
Finished Jul 14 07:00:39 PM PDT 24
Peak memory 201360 kb
Host smart-f393ba41-ced8-4c28-bf06-e6d0e95bc3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782432781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.782432781
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.238921497
Short name T848
Test name
Test status
Simulation time 383865871 ps
CPU time 0.91 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201400 kb
Host smart-0d5995d5-c360-4995-a010-a8518ca7815d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238921497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.238921497
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3365762419
Short name T880
Test name
Test status
Simulation time 485172139 ps
CPU time 1.32 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 201412 kb
Host smart-2fa6b918-d85b-4ae5-8cba-12ce38fb743b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365762419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3365762419
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4222588104
Short name T812
Test name
Test status
Simulation time 515142491 ps
CPU time 1.2 seconds
Started Jul 14 07:00:05 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201400 kb
Host smart-3cbe8f88-1caa-459d-a84e-f810a9ae0581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222588104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4222588104
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4138301054
Short name T815
Test name
Test status
Simulation time 460644287 ps
CPU time 1.66 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 201400 kb
Host smart-8345cb8f-5b92-4e26-abd8-7d3f76378736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138301054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.4138301054
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1984444088
Short name T803
Test name
Test status
Simulation time 419036409 ps
CPU time 1.57 seconds
Started Jul 14 07:00:24 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 201392 kb
Host smart-2c46b4f9-5ba0-411a-b259-ea299bb77398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984444088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1984444088
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2698897165
Short name T883
Test name
Test status
Simulation time 430166043 ps
CPU time 1.66 seconds
Started Jul 14 07:00:29 PM PDT 24
Finished Jul 14 07:00:34 PM PDT 24
Peak memory 201424 kb
Host smart-79ee9635-0019-4dad-b6e2-8ca2ab456453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698897165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2698897165
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2643612353
Short name T131
Test name
Test status
Simulation time 684572824 ps
CPU time 3.28 seconds
Started Jul 14 06:59:57 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 201688 kb
Host smart-f85ece00-1ecc-4e3a-a5d0-b5342a487f1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643612353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2643612353
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3235877433
Short name T144
Test name
Test status
Simulation time 26714722580 ps
CPU time 59.01 seconds
Started Jul 14 06:59:56 PM PDT 24
Finished Jul 14 07:01:02 PM PDT 24
Peak memory 201796 kb
Host smart-dd33bcd1-0ed5-41ee-9a68-e5453609aa2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235877433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3235877433
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.947618751
Short name T126
Test name
Test status
Simulation time 1005707873 ps
CPU time 2.95 seconds
Started Jul 14 06:59:53 PM PDT 24
Finished Jul 14 07:00:01 PM PDT 24
Peak memory 201508 kb
Host smart-d683eaa5-67cb-418c-a5d9-08c8dce7d790
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947618751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.947618751
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.775953443
Short name T113
Test name
Test status
Simulation time 321084689 ps
CPU time 1.54 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201568 kb
Host smart-73862d98-2ee5-48a5-a8d9-a8ce3fcc9558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775953443 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.775953443
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2121584858
Short name T136
Test name
Test status
Simulation time 430035547 ps
CPU time 1.77 seconds
Started Jul 14 06:59:58 PM PDT 24
Finished Jul 14 07:00:07 PM PDT 24
Peak memory 201480 kb
Host smart-f5cefaa9-45e9-461d-a076-cae47e3cbc9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121584858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2121584858
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.32897228
Short name T849
Test name
Test status
Simulation time 531103649 ps
CPU time 1.8 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201348 kb
Host smart-91aa9839-a47a-49a1-8e64-af99fd3b50e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32897228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.32897228
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1072399763
Short name T59
Test name
Test status
Simulation time 2122041227 ps
CPU time 7.6 seconds
Started Jul 14 07:00:43 PM PDT 24
Finished Jul 14 07:00:52 PM PDT 24
Peak memory 201480 kb
Host smart-9fde2565-bfbc-486d-955c-6a4f56122e89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072399763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1072399763
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3619525374
Short name T859
Test name
Test status
Simulation time 658322084 ps
CPU time 3.1 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:32 PM PDT 24
Peak memory 209840 kb
Host smart-3d7a58a5-1e43-4763-854f-51d8619fd047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619525374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3619525374
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.466351541
Short name T841
Test name
Test status
Simulation time 4386037861 ps
CPU time 3.74 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:23 PM PDT 24
Peak memory 201768 kb
Host smart-57b7dae6-b8c5-4c51-86b9-fbefc4d1f444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466351541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.466351541
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2449974009
Short name T895
Test name
Test status
Simulation time 431852757 ps
CPU time 1.47 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201424 kb
Host smart-d0a5fa81-2baf-476d-a2df-6e2ad5536a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449974009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2449974009
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2512417203
Short name T891
Test name
Test status
Simulation time 502836104 ps
CPU time 0.76 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 201624 kb
Host smart-81687393-229f-447f-90ba-9b70cdcf2e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512417203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2512417203
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4061014997
Short name T903
Test name
Test status
Simulation time 492812661 ps
CPU time 1.23 seconds
Started Jul 14 07:00:26 PM PDT 24
Finished Jul 14 07:00:32 PM PDT 24
Peak memory 201396 kb
Host smart-bfdcc14f-167c-46f0-97c0-92dbbb636d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061014997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.4061014997
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3764082562
Short name T860
Test name
Test status
Simulation time 329056111 ps
CPU time 0.91 seconds
Started Jul 14 07:00:27 PM PDT 24
Finished Jul 14 07:00:32 PM PDT 24
Peak memory 201436 kb
Host smart-b454e54f-e18b-4962-8cd1-9cfc5337ebf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764082562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3764082562
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1666714208
Short name T892
Test name
Test status
Simulation time 425163862 ps
CPU time 1.54 seconds
Started Jul 14 07:00:31 PM PDT 24
Finished Jul 14 07:00:36 PM PDT 24
Peak memory 201420 kb
Host smart-085bdf0d-49f9-42bc-ac29-1b4cbb3eace0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666714208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1666714208
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2656201047
Short name T804
Test name
Test status
Simulation time 412260237 ps
CPU time 1.57 seconds
Started Jul 14 07:00:23 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 201428 kb
Host smart-5f335e37-5ac8-49ed-a8e4-32baba5ad875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656201047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2656201047
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2351294752
Short name T801
Test name
Test status
Simulation time 425444927 ps
CPU time 0.87 seconds
Started Jul 14 07:00:12 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 201392 kb
Host smart-7b6721d5-f8a1-45e1-85f3-897b5ca26a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351294752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2351294752
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3466144730
Short name T871
Test name
Test status
Simulation time 502326049 ps
CPU time 0.91 seconds
Started Jul 14 07:00:24 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 201404 kb
Host smart-d24820c9-00e4-4bb5-afc2-fc4a8318009a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466144730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3466144730
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1560988506
Short name T851
Test name
Test status
Simulation time 546334007 ps
CPU time 0.96 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:00:38 PM PDT 24
Peak memory 201412 kb
Host smart-a38abfa7-30d7-4028-9120-39656eb47117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560988506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1560988506
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3751531507
Short name T808
Test name
Test status
Simulation time 391514275 ps
CPU time 0.86 seconds
Started Jul 14 07:00:23 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 201424 kb
Host smart-bc98cda6-0e05-4da1-8d40-6a27f848cd99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751531507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3751531507
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3696591905
Short name T865
Test name
Test status
Simulation time 1010253660 ps
CPU time 1.55 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:00:36 PM PDT 24
Peak memory 201652 kb
Host smart-efb2444d-2c6e-42bc-9a83-51b13448806f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696591905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3696591905
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2946842601
Short name T132
Test name
Test status
Simulation time 26256963268 ps
CPU time 32.54 seconds
Started Jul 14 07:00:26 PM PDT 24
Finished Jul 14 07:01:04 PM PDT 24
Peak memory 201708 kb
Host smart-6a677c97-2d42-4c02-a4f7-c58312b3afb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946842601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2946842601
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.146995672
Short name T875
Test name
Test status
Simulation time 735842618 ps
CPU time 1.27 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201480 kb
Host smart-65f549d8-618b-4f0c-9173-02effa476cd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146995672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.146995672
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.486493597
Short name T881
Test name
Test status
Simulation time 424901186 ps
CPU time 1.24 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 201576 kb
Host smart-b13fc62d-8a10-4dbc-ad79-8d4aa62a9cfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486493597 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.486493597
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1642646429
Short name T918
Test name
Test status
Simulation time 518778538 ps
CPU time 1.95 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201392 kb
Host smart-e9687e86-2050-411e-9fea-8959a577df20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642646429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1642646429
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.461251759
Short name T872
Test name
Test status
Simulation time 407817462 ps
CPU time 0.88 seconds
Started Jul 14 06:59:59 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 201428 kb
Host smart-02f386ca-d8d7-4970-9875-ea80c9ea3679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461251759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.461251759
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.806937044
Short name T822
Test name
Test status
Simulation time 2348620999 ps
CPU time 3.61 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:33 PM PDT 24
Peak memory 201592 kb
Host smart-eec4af45-fc99-4808-aa95-0b9fc88e1b9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806937044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.806937044
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.389405500
Short name T906
Test name
Test status
Simulation time 748533138 ps
CPU time 2.04 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201804 kb
Host smart-9c952210-5d29-4ec5-b025-accd31ccc124
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389405500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.389405500
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.556436289
Short name T63
Test name
Test status
Simulation time 4667044855 ps
CPU time 4.34 seconds
Started Jul 14 06:59:54 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 201820 kb
Host smart-25f160fa-351b-43fd-a145-4f6581614ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556436289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.556436289
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2338572864
Short name T916
Test name
Test status
Simulation time 294481301 ps
CPU time 1.32 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:00:44 PM PDT 24
Peak memory 201432 kb
Host smart-100189df-fbc4-484a-b60f-2b74c04fc13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338572864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2338572864
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1882308385
Short name T920
Test name
Test status
Simulation time 506209813 ps
CPU time 1.15 seconds
Started Jul 14 07:00:36 PM PDT 24
Finished Jul 14 07:00:39 PM PDT 24
Peak memory 201452 kb
Host smart-91b2b3d1-cdc0-477a-ac70-5d350f033651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882308385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1882308385
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1691459752
Short name T896
Test name
Test status
Simulation time 431465931 ps
CPU time 0.9 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201296 kb
Host smart-2f659830-a3d6-4a76-a3f5-ea7b95ad7b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691459752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1691459752
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3614406989
Short name T853
Test name
Test status
Simulation time 527928454 ps
CPU time 0.95 seconds
Started Jul 14 07:00:25 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 201624 kb
Host smart-3abee6c7-5861-4f7f-a739-9f3dee861cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614406989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3614406989
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1110186882
Short name T893
Test name
Test status
Simulation time 383560409 ps
CPU time 0.87 seconds
Started Jul 14 07:00:20 PM PDT 24
Finished Jul 14 07:00:27 PM PDT 24
Peak memory 201428 kb
Host smart-8b4a01d9-d704-4319-b6fc-5607f8d449fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110186882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1110186882
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.285890715
Short name T800
Test name
Test status
Simulation time 290895590 ps
CPU time 1 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201352 kb
Host smart-871e2adc-ea82-461f-89e9-33ab1479b4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285890715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.285890715
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.192441316
Short name T854
Test name
Test status
Simulation time 303402194 ps
CPU time 1.42 seconds
Started Jul 14 07:00:27 PM PDT 24
Finished Jul 14 07:00:33 PM PDT 24
Peak memory 201392 kb
Host smart-02237cf6-2f10-4ab1-b514-b13d2d8b42e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192441316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.192441316
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3960419854
Short name T907
Test name
Test status
Simulation time 482305198 ps
CPU time 0.94 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:00:55 PM PDT 24
Peak memory 201360 kb
Host smart-3576bebb-006e-4abb-af17-6720c05c9449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960419854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3960419854
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2715494200
Short name T858
Test name
Test status
Simulation time 425264843 ps
CPU time 0.84 seconds
Started Jul 14 07:00:31 PM PDT 24
Finished Jul 14 07:00:35 PM PDT 24
Peak memory 201404 kb
Host smart-a7fd3199-be3e-4b76-abff-a34d8cfeb591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715494200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2715494200
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2370064427
Short name T847
Test name
Test status
Simulation time 520191465 ps
CPU time 1.97 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:00:45 PM PDT 24
Peak memory 201444 kb
Host smart-c0514149-523e-44f1-afbd-a70f4c6f42d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370064427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2370064427
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2760892207
Short name T837
Test name
Test status
Simulation time 545565254 ps
CPU time 2.28 seconds
Started Jul 14 07:00:13 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 201592 kb
Host smart-ba83a507-0136-42e8-9080-18a7b83186c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760892207 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2760892207
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2296549253
Short name T876
Test name
Test status
Simulation time 343806966 ps
CPU time 1.52 seconds
Started Jul 14 07:00:03 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 201368 kb
Host smart-7c2e0a3c-d2cc-42be-bfd4-ad00f9c02b1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296549253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2296549253
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1898204966
Short name T835
Test name
Test status
Simulation time 438012512 ps
CPU time 1.49 seconds
Started Jul 14 07:00:09 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 201412 kb
Host smart-62ee2561-adeb-4783-b264-a9a2b313db9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898204966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1898204966
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1529501122
Short name T839
Test name
Test status
Simulation time 4789743719 ps
CPU time 3.77 seconds
Started Jul 14 07:00:01 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201856 kb
Host smart-c1d21e29-6d2c-4639-9d7b-009a64ef5ba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529501122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1529501122
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1614334686
Short name T77
Test name
Test status
Simulation time 553355033 ps
CPU time 1.91 seconds
Started Jul 14 07:00:05 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201424 kb
Host smart-b2938706-47d3-4308-9d63-0e3bb50ddf51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614334686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1614334686
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3160003464
Short name T873
Test name
Test status
Simulation time 8159927420 ps
CPU time 12.7 seconds
Started Jul 14 06:59:55 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201832 kb
Host smart-4961cfcd-d201-42fd-90c6-4c1ce1b3a444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160003464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3160003464
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.74997253
Short name T842
Test name
Test status
Simulation time 449823586 ps
CPU time 1.95 seconds
Started Jul 14 07:00:16 PM PDT 24
Finished Jul 14 07:00:23 PM PDT 24
Peak memory 201612 kb
Host smart-af529932-9107-4549-9955-0698bfab1e9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74997253 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.74997253
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.707552681
Short name T857
Test name
Test status
Simulation time 342791569 ps
CPU time 1.63 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 201484 kb
Host smart-4057a1ee-1319-4424-ae8f-70633301825c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707552681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.707552681
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.806842005
Short name T805
Test name
Test status
Simulation time 511400605 ps
CPU time 0.89 seconds
Started Jul 14 07:00:15 PM PDT 24
Finished Jul 14 07:00:20 PM PDT 24
Peak memory 201464 kb
Host smart-f8d6c58d-7603-4f9b-a7c5-5af92e89bfeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806842005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.806842005
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3548484354
Short name T899
Test name
Test status
Simulation time 5528210061 ps
CPU time 3.01 seconds
Started Jul 14 07:00:07 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 201804 kb
Host smart-492a32ea-bf25-4b2e-915b-52cba8816312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548484354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3548484354
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4273986529
Short name T826
Test name
Test status
Simulation time 863298298 ps
CPU time 2.17 seconds
Started Jul 14 07:00:14 PM PDT 24
Finished Jul 14 07:00:21 PM PDT 24
Peak memory 201856 kb
Host smart-91b49269-9350-4a88-ac72-6bfcf54aaf7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273986529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.4273986529
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3395907629
Short name T890
Test name
Test status
Simulation time 4378073031 ps
CPU time 6.97 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201864 kb
Host smart-147b3ad6-3c16-42ee-9441-fffbb5208cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395907629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3395907629
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3219535647
Short name T78
Test name
Test status
Simulation time 917389555 ps
CPU time 1.1 seconds
Started Jul 14 07:00:25 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 201592 kb
Host smart-c3b5790a-5f5e-4c29-809c-e79ebcce9093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219535647 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3219535647
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.77185807
Short name T138
Test name
Test status
Simulation time 415807085 ps
CPU time 1.71 seconds
Started Jul 14 07:00:08 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 201480 kb
Host smart-1a4cbc84-a386-4377-8762-47512b6a2878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77185807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.77185807
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2043774305
Short name T908
Test name
Test status
Simulation time 379624482 ps
CPU time 0.86 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201432 kb
Host smart-df664ad2-74c5-48ad-adf1-614e30f93586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043774305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2043774305
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4162788280
Short name T889
Test name
Test status
Simulation time 2934968270 ps
CPU time 1.96 seconds
Started Jul 14 07:00:19 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 201508 kb
Host smart-b2d06933-9a1e-4ee0-b574-bfce76278363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162788280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4162788280
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1773524627
Short name T877
Test name
Test status
Simulation time 639278417 ps
CPU time 2.58 seconds
Started Jul 14 07:00:25 PM PDT 24
Finished Jul 14 07:00:33 PM PDT 24
Peak memory 209928 kb
Host smart-bb6db869-cead-4cbc-8899-2aa051e853b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773524627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1773524627
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.845823980
Short name T332
Test name
Test status
Simulation time 4323143843 ps
CPU time 11.84 seconds
Started Jul 14 07:00:21 PM PDT 24
Finished Jul 14 07:00:39 PM PDT 24
Peak memory 201792 kb
Host smart-e936dac6-ed38-45d2-9ba9-98bb8db678fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845823980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.845823980
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2291197061
Short name T855
Test name
Test status
Simulation time 600748259 ps
CPU time 1.15 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:17 PM PDT 24
Peak memory 201576 kb
Host smart-ffb4f97d-4a67-4c97-8b30-ba31bd8cea5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291197061 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2291197061
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.887766868
Short name T868
Test name
Test status
Simulation time 409321226 ps
CPU time 1.64 seconds
Started Jul 14 07:00:17 PM PDT 24
Finished Jul 14 07:00:23 PM PDT 24
Peak memory 201404 kb
Host smart-0f9937f8-0a3f-4f91-9bab-ba6dd3dadbf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887766868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.887766868
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1581690833
Short name T811
Test name
Test status
Simulation time 383715817 ps
CPU time 0.65 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:13 PM PDT 24
Peak memory 201412 kb
Host smart-c094c5a8-055d-49dd-85d3-9202239f38aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581690833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1581690833
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1488605253
Short name T61
Test name
Test status
Simulation time 2354329322 ps
CPU time 3.05 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:31 PM PDT 24
Peak memory 201528 kb
Host smart-993790e0-ee6d-4147-ab0e-348075581f21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488605253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1488605253
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1863842799
Short name T900
Test name
Test status
Simulation time 518307251 ps
CPU time 1.71 seconds
Started Jul 14 07:00:18 PM PDT 24
Finished Jul 14 07:00:25 PM PDT 24
Peak memory 201664 kb
Host smart-33af1bf5-49c6-4632-bfa3-74ae64283946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863842799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1863842799
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3227365969
Short name T330
Test name
Test status
Simulation time 8634291554 ps
CPU time 7.53 seconds
Started Jul 14 07:00:00 PM PDT 24
Finished Jul 14 07:00:16 PM PDT 24
Peak memory 201832 kb
Host smart-f72b81c5-23db-4aac-b556-4be5590923b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227365969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3227365969
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3955026872
Short name T898
Test name
Test status
Simulation time 628977749 ps
CPU time 1.32 seconds
Started Jul 14 07:00:06 PM PDT 24
Finished Jul 14 07:00:14 PM PDT 24
Peak memory 201532 kb
Host smart-45f5c9d2-f4cd-44c9-a700-1487329a0ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955026872 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3955026872
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1178090507
Short name T133
Test name
Test status
Simulation time 589989583 ps
CPU time 0.89 seconds
Started Jul 14 07:00:00 PM PDT 24
Finished Jul 14 07:00:09 PM PDT 24
Peak memory 201496 kb
Host smart-2e3f6c69-df63-4270-bca9-d3c42fe46a4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178090507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1178090507
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3370589017
Short name T828
Test name
Test status
Simulation time 478645270 ps
CPU time 0.83 seconds
Started Jul 14 07:00:24 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 201364 kb
Host smart-faea1b7d-c0d7-4965-a28f-79602b0f3dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370589017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3370589017
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2192287120
Short name T142
Test name
Test status
Simulation time 2044388102 ps
CPU time 5.42 seconds
Started Jul 14 07:00:04 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 201516 kb
Host smart-1ceab0df-6f04-4ae4-881a-9f3307edc374
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192287120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2192287120
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4161896611
Short name T73
Test name
Test status
Simulation time 367795348 ps
CPU time 2.34 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:13 PM PDT 24
Peak memory 201772 kb
Host smart-844e7d9e-2bdc-4028-b905-d60ce908ca67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161896611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4161896611
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1031301330
Short name T850
Test name
Test status
Simulation time 4522904806 ps
CPU time 4.29 seconds
Started Jul 14 07:00:02 PM PDT 24
Finished Jul 14 07:00:15 PM PDT 24
Peak memory 201680 kb
Host smart-bff4ddaf-d1e5-4773-a220-6afebdd3a240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031301330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1031301330
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2545309844
Short name T650
Test name
Test status
Simulation time 381736624 ps
CPU time 0.87 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:00:29 PM PDT 24
Peak memory 201668 kb
Host smart-c9d331ba-80df-4081-823b-2518cfdc9a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545309844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2545309844
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.504747043
Short name T753
Test name
Test status
Simulation time 161878130372 ps
CPU time 196.03 seconds
Started Jul 14 07:00:37 PM PDT 24
Finished Jul 14 07:03:55 PM PDT 24
Peak memory 201872 kb
Host smart-7cab3d17-5bc4-492b-89c3-3004c19c131f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504747043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.504747043
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3910315343
Short name T228
Test name
Test status
Simulation time 326763263588 ps
CPU time 672.99 seconds
Started Jul 14 07:00:39 PM PDT 24
Finished Jul 14 07:11:54 PM PDT 24
Peak memory 201904 kb
Host smart-e4bf3cd3-2955-4793-8f23-4f8f642bf8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910315343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3910315343
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4194505478
Short name T537
Test name
Test status
Simulation time 162616929307 ps
CPU time 85.24 seconds
Started Jul 14 07:00:29 PM PDT 24
Finished Jul 14 07:01:58 PM PDT 24
Peak memory 201936 kb
Host smart-b413b4c4-a4b3-4d44-a236-5564805f1958
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194505478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4194505478
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2813611439
Short name T404
Test name
Test status
Simulation time 324298998526 ps
CPU time 752.99 seconds
Started Jul 14 07:00:28 PM PDT 24
Finished Jul 14 07:13:05 PM PDT 24
Peak memory 201988 kb
Host smart-d3446183-aba5-4731-914c-31e6bb5cf7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813611439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2813611439
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.950819904
Short name T669
Test name
Test status
Simulation time 502537695947 ps
CPU time 1117.08 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:19:32 PM PDT 24
Peak memory 201892 kb
Host smart-f8a18de1-9552-45f8-90ca-d631b912ba16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=950819904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.950819904
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.436353599
Short name T637
Test name
Test status
Simulation time 168028058264 ps
CPU time 194.75 seconds
Started Jul 14 07:00:29 PM PDT 24
Finished Jul 14 07:03:48 PM PDT 24
Peak memory 201932 kb
Host smart-fd65b54e-8401-41f4-8cd7-f00a987eb9f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436353599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.436353599
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3568648090
Short name T630
Test name
Test status
Simulation time 195875226082 ps
CPU time 106.7 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:02:42 PM PDT 24
Peak memory 201884 kb
Host smart-e6833fc4-5275-4117-8f0c-89013013aa67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568648090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3568648090
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2781339627
Short name T726
Test name
Test status
Simulation time 31795173503 ps
CPU time 16.1 seconds
Started Jul 14 07:00:20 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 201728 kb
Host smart-4991e4c1-5c65-4545-9323-5a030718d3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781339627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2781339627
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4130461827
Short name T515
Test name
Test status
Simulation time 3097331025 ps
CPU time 4.22 seconds
Started Jul 14 07:00:40 PM PDT 24
Finished Jul 14 07:00:45 PM PDT 24
Peak memory 201692 kb
Host smart-508417c0-a0ad-4625-8545-186ae01b45f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130461827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4130461827
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1212564832
Short name T576
Test name
Test status
Simulation time 6074816686 ps
CPU time 4.57 seconds
Started Jul 14 07:00:23 PM PDT 24
Finished Jul 14 07:00:34 PM PDT 24
Peak memory 201608 kb
Host smart-d641ed47-13e0-470f-b278-743f86e5c089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212564832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1212564832
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.264911530
Short name T24
Test name
Test status
Simulation time 81876471260 ps
CPU time 89.29 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:02:20 PM PDT 24
Peak memory 210624 kb
Host smart-f30d861f-bfa9-4d55-9808-214713aaabce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264911530 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.264911530
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4155700019
Short name T479
Test name
Test status
Simulation time 548966166 ps
CPU time 0.95 seconds
Started Jul 14 07:00:33 PM PDT 24
Finished Jul 14 07:00:36 PM PDT 24
Peak memory 201604 kb
Host smart-7319115e-4b9f-43cf-ba20-11728a3220c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155700019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4155700019
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2663374725
Short name T284
Test name
Test status
Simulation time 166583718276 ps
CPU time 377.88 seconds
Started Jul 14 07:00:38 PM PDT 24
Finished Jul 14 07:06:57 PM PDT 24
Peak memory 201936 kb
Host smart-2460e0c4-930e-4082-9779-4379ab685849
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663374725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2663374725
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2450841988
Short name T683
Test name
Test status
Simulation time 328737771176 ps
CPU time 532.51 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:09:30 PM PDT 24
Peak memory 201900 kb
Host smart-e9a10782-4ce8-47e0-9b9c-7a312e2206b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450841988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2450841988
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3415043086
Short name T674
Test name
Test status
Simulation time 171515303392 ps
CPU time 418.98 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:07:27 PM PDT 24
Peak memory 201836 kb
Host smart-aeee9896-94de-4c6e-b30c-cf72399312eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415043086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3415043086
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.819479347
Short name T519
Test name
Test status
Simulation time 169767194773 ps
CPU time 111.12 seconds
Started Jul 14 07:00:33 PM PDT 24
Finished Jul 14 07:02:27 PM PDT 24
Peak memory 201972 kb
Host smart-fe7c789b-e0a2-4967-802f-655608785bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819479347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.819479347
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1157821620
Short name T561
Test name
Test status
Simulation time 328487290025 ps
CPU time 202.62 seconds
Started Jul 14 07:00:26 PM PDT 24
Finished Jul 14 07:03:54 PM PDT 24
Peak memory 201860 kb
Host smart-27a27271-0a8f-40c1-8110-3ca4b1cd2364
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157821620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1157821620
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3710695526
Short name T613
Test name
Test status
Simulation time 378204615243 ps
CPU time 162.05 seconds
Started Jul 14 07:00:23 PM PDT 24
Finished Jul 14 07:03:11 PM PDT 24
Peak memory 201964 kb
Host smart-a9ef988a-faf5-4b81-afa9-30dae9445418
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710695526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3710695526
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2038776123
Short name T379
Test name
Test status
Simulation time 407333747499 ps
CPU time 318.25 seconds
Started Jul 14 07:00:29 PM PDT 24
Finished Jul 14 07:05:51 PM PDT 24
Peak memory 201924 kb
Host smart-c9f2dc84-f7d2-48b0-88a7-e64858e91daf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038776123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2038776123
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3349953351
Short name T196
Test name
Test status
Simulation time 106563908185 ps
CPU time 387.56 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:07:14 PM PDT 24
Peak memory 202212 kb
Host smart-eeb0eebe-9699-43ae-8a27-762e91d0e4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349953351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3349953351
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4101432834
Short name T407
Test name
Test status
Simulation time 38092995412 ps
CPU time 87.9 seconds
Started Jul 14 07:00:39 PM PDT 24
Finished Jul 14 07:02:08 PM PDT 24
Peak memory 201656 kb
Host smart-2bdbccbe-9474-4d4d-be23-0a6023d2ac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101432834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4101432834
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1647708021
Short name T433
Test name
Test status
Simulation time 4227456695 ps
CPU time 10.55 seconds
Started Jul 14 07:00:25 PM PDT 24
Finished Jul 14 07:00:40 PM PDT 24
Peak memory 201684 kb
Host smart-ac7679e2-6d10-4524-a95a-9d95099b9c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647708021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1647708021
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3186385749
Short name T71
Test name
Test status
Simulation time 3749432546 ps
CPU time 2.76 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:00:36 PM PDT 24
Peak memory 217080 kb
Host smart-721ed4bc-b65c-446a-9015-732342d2a3e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186385749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3186385749
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1171268576
Short name T626
Test name
Test status
Simulation time 6141331820 ps
CPU time 13.96 seconds
Started Jul 14 07:00:36 PM PDT 24
Finished Jul 14 07:00:52 PM PDT 24
Peak memory 201684 kb
Host smart-85a97886-fbf4-4998-8d6f-b3098e76436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171268576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1171268576
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3217364205
Short name T163
Test name
Test status
Simulation time 293708173037 ps
CPU time 1040.09 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:18:14 PM PDT 24
Peak memory 202244 kb
Host smart-081b904e-2a7a-4d8d-a004-d945fd27ac27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217364205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3217364205
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.827682918
Short name T92
Test name
Test status
Simulation time 58648899324 ps
CPU time 38.14 seconds
Started Jul 14 07:00:26 PM PDT 24
Finished Jul 14 07:01:09 PM PDT 24
Peak memory 210236 kb
Host smart-28f5e505-72d4-4538-802b-2d3b9ce989a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827682918 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.827682918
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3345133457
Short name T377
Test name
Test status
Simulation time 379714229 ps
CPU time 0.81 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:00:47 PM PDT 24
Peak memory 201656 kb
Host smart-ab4afbf1-7604-4756-a051-443bfc417be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345133457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3345133457
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3908529190
Short name T6
Test name
Test status
Simulation time 184962340000 ps
CPU time 101.23 seconds
Started Jul 14 07:01:03 PM PDT 24
Finished Jul 14 07:02:48 PM PDT 24
Peak memory 201924 kb
Host smart-e892304a-2f95-452d-9044-65c0c608c804
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908529190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3908529190
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2742765951
Short name T781
Test name
Test status
Simulation time 342124962999 ps
CPU time 551.12 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:10:08 PM PDT 24
Peak memory 201924 kb
Host smart-18460b56-b267-4017-9659-a353b3941936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742765951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2742765951
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3165496017
Short name T110
Test name
Test status
Simulation time 166846316471 ps
CPU time 408.46 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 201952 kb
Host smart-517fc84b-2cdf-4249-b5d3-1dc4e6e5fa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165496017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3165496017
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3689492991
Short name T456
Test name
Test status
Simulation time 171545597419 ps
CPU time 210.23 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:04:31 PM PDT 24
Peak memory 201912 kb
Host smart-2b1a45d1-c6a2-4257-b336-9b5318a55e3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689492991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3689492991
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3093942224
Short name T172
Test name
Test status
Simulation time 489243102079 ps
CPU time 235.91 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:04:43 PM PDT 24
Peak memory 201984 kb
Host smart-653ad4d5-13aa-4d4a-ba27-19de59eaffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093942224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3093942224
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4009127010
Short name T348
Test name
Test status
Simulation time 329410158989 ps
CPU time 390.65 seconds
Started Jul 14 07:01:04 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 201912 kb
Host smart-473cf3c1-807e-4fc8-bcf2-a69f0913cf4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009127010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4009127010
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1990161022
Short name T271
Test name
Test status
Simulation time 171641174814 ps
CPU time 102.11 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:02:33 PM PDT 24
Peak memory 201912 kb
Host smart-860b9826-1b48-4c08-b0f6-fdf7b97d0d03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990161022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1990161022
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3119311642
Short name T366
Test name
Test status
Simulation time 402822178564 ps
CPU time 902.23 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:15:52 PM PDT 24
Peak memory 201832 kb
Host smart-f9377139-03c5-4c74-9dcf-935aad466fea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119311642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3119311642
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1013494662
Short name T780
Test name
Test status
Simulation time 122227753804 ps
CPU time 472.49 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:08:55 PM PDT 24
Peak memory 202184 kb
Host smart-9d0268e6-a91a-419c-938f-f8e197f89b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013494662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1013494662
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1508384965
Short name T444
Test name
Test status
Simulation time 39124860142 ps
CPU time 95.84 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:02:38 PM PDT 24
Peak memory 201704 kb
Host smart-36044e8a-3c2f-4c19-8bf7-1f169c7cc40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508384965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1508384965
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2185901404
Short name T685
Test name
Test status
Simulation time 3258313244 ps
CPU time 2.55 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:01:01 PM PDT 24
Peak memory 201728 kb
Host smart-3ed875c2-1b8a-41be-b234-fa1df7b3f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185901404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2185901404
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1285259060
Short name T631
Test name
Test status
Simulation time 5711471421 ps
CPU time 3.95 seconds
Started Jul 14 07:01:02 PM PDT 24
Finished Jul 14 07:01:10 PM PDT 24
Peak memory 201696 kb
Host smart-c1cb046d-543a-4e70-957b-262ffd7c720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285259060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1285259060
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2252276466
Short name T624
Test name
Test status
Simulation time 155806027142 ps
CPU time 577.59 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:10:28 PM PDT 24
Peak memory 202268 kb
Host smart-b9f46d9f-3772-4609-90ae-bfec22855948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252276466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2252276466
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3799057177
Short name T285
Test name
Test status
Simulation time 131006763935 ps
CPU time 63.63 seconds
Started Jul 14 07:01:04 PM PDT 24
Finished Jul 14 07:02:11 PM PDT 24
Peak memory 210548 kb
Host smart-0511499f-5028-4cec-bc3a-406ab1a2385c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799057177 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3799057177
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1111912254
Short name T659
Test name
Test status
Simulation time 307038359 ps
CPU time 0.79 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:00:38 PM PDT 24
Peak memory 201672 kb
Host smart-8707bacc-fe30-487e-8ed6-41c8d5c3b57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111912254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1111912254
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1808894089
Short name T518
Test name
Test status
Simulation time 349265122834 ps
CPU time 773.4 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:14:02 PM PDT 24
Peak memory 201908 kb
Host smart-41b449b5-4c7b-44fd-89dc-56918b695377
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808894089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1808894089
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1069812475
Short name T587
Test name
Test status
Simulation time 167466966255 ps
CPU time 101.82 seconds
Started Jul 14 07:00:55 PM PDT 24
Finished Jul 14 07:02:42 PM PDT 24
Peak memory 201920 kb
Host smart-61f15e36-0b36-40dc-b20d-dc8cb83326d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069812475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1069812475
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1556918909
Short name T625
Test name
Test status
Simulation time 164201733727 ps
CPU time 48.43 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:01:37 PM PDT 24
Peak memory 201916 kb
Host smart-e0eb2c92-5649-4ed7-b06e-35c1be8caffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556918909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1556918909
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2363014457
Short name T365
Test name
Test status
Simulation time 163372263922 ps
CPU time 103.01 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:02:41 PM PDT 24
Peak memory 201952 kb
Host smart-4a854737-b254-4075-ae59-6447ad77ef5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363014457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2363014457
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.806406310
Short name T502
Test name
Test status
Simulation time 172249078174 ps
CPU time 407.78 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:08:04 PM PDT 24
Peak memory 201984 kb
Host smart-9f4e1772-aeb7-41c9-a0ff-1ff37b0016bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806406310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.806406310
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3481754369
Short name T478
Test name
Test status
Simulation time 598563188878 ps
CPU time 209.76 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:04:19 PM PDT 24
Peak memory 201904 kb
Host smart-fe9a846c-3fbe-40f4-9c62-87333420ff79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481754369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3481754369
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2401656929
Short name T454
Test name
Test status
Simulation time 113254262068 ps
CPU time 586.06 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:10:48 PM PDT 24
Peak memory 202236 kb
Host smart-4be95004-a57d-4f1d-8ffe-0942f2c76fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401656929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2401656929
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2076480270
Short name T484
Test name
Test status
Simulation time 29616457348 ps
CPU time 61.42 seconds
Started Jul 14 07:01:03 PM PDT 24
Finished Jul 14 07:02:08 PM PDT 24
Peak memory 201708 kb
Host smart-7c6f57cb-fe41-448e-82f1-c721464dc23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076480270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2076480270
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4277007266
Short name T595
Test name
Test status
Simulation time 2546711837 ps
CPU time 6.91 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:01:01 PM PDT 24
Peak memory 201660 kb
Host smart-7855cc33-03c5-437a-820a-5a424e1a5e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277007266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4277007266
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1876119416
Short name T434
Test name
Test status
Simulation time 5983621770 ps
CPU time 14.59 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:01:11 PM PDT 24
Peak memory 201704 kb
Host smart-d64b495c-b186-4f64-a6bd-cdf00ded6944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876119416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1876119416
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1580121923
Short name T564
Test name
Test status
Simulation time 213533900243 ps
CPU time 179.65 seconds
Started Jul 14 07:01:02 PM PDT 24
Finished Jul 14 07:04:06 PM PDT 24
Peak memory 217756 kb
Host smart-a729139a-148c-49ba-95c5-4a043df15a9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580121923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1580121923
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1446751225
Short name T296
Test name
Test status
Simulation time 332432355874 ps
CPU time 749.92 seconds
Started Jul 14 07:01:01 PM PDT 24
Finished Jul 14 07:13:35 PM PDT 24
Peak memory 201944 kb
Host smart-89817a19-cf15-4415-a391-f579387ab441
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446751225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1446751225
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3591687354
Short name T148
Test name
Test status
Simulation time 484616841599 ps
CPU time 573.42 seconds
Started Jul 14 07:01:02 PM PDT 24
Finished Jul 14 07:10:39 PM PDT 24
Peak memory 201996 kb
Host smart-2de991e7-a257-448c-9439-99bc5a75e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591687354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3591687354
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3170745266
Short name T693
Test name
Test status
Simulation time 165775599630 ps
CPU time 347.09 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:06:36 PM PDT 24
Peak memory 201776 kb
Host smart-db56c75e-0839-4b3d-893e-450b305c3ed9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170745266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3170745266
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3218793217
Short name T664
Test name
Test status
Simulation time 498139896727 ps
CPU time 281.16 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:05:57 PM PDT 24
Peak memory 201880 kb
Host smart-f69507b3-0709-447f-b392-6a89ea863e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218793217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3218793217
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1817951529
Short name T580
Test name
Test status
Simulation time 161944001658 ps
CPU time 358.05 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:06:49 PM PDT 24
Peak memory 201876 kb
Host smart-ed00b26e-445e-42ef-a288-0c24080cdf96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817951529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1817951529
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1785366379
Short name T360
Test name
Test status
Simulation time 196408984914 ps
CPU time 452.92 seconds
Started Jul 14 07:01:05 PM PDT 24
Finished Jul 14 07:08:41 PM PDT 24
Peak memory 201880 kb
Host smart-c31d28ae-ae32-471d-987d-ca2417b67490
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785366379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1785366379
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3536866489
Short name T198
Test name
Test status
Simulation time 93235669409 ps
CPU time 440.06 seconds
Started Jul 14 07:00:55 PM PDT 24
Finished Jul 14 07:08:21 PM PDT 24
Peak memory 202292 kb
Host smart-3febc851-e9fe-4eac-b9d8-bec9c8c61887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536866489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3536866489
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2806396356
Short name T97
Test name
Test status
Simulation time 32522691617 ps
CPU time 35.92 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:01:34 PM PDT 24
Peak memory 201712 kb
Host smart-59621e43-1078-47d0-a769-5fa5cbe09163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806396356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2806396356
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.445098498
Short name T385
Test name
Test status
Simulation time 3578355168 ps
CPU time 5.55 seconds
Started Jul 14 07:01:04 PM PDT 24
Finished Jul 14 07:01:13 PM PDT 24
Peak memory 201680 kb
Host smart-06fcf110-6e2c-4b49-811c-08bad0ffd695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445098498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.445098498
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3526851522
Short name T665
Test name
Test status
Simulation time 6016922829 ps
CPU time 7.67 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:01:19 PM PDT 24
Peak memory 201724 kb
Host smart-e3e5d1bb-27da-4324-996e-0ef7260be434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526851522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3526851522
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1043645773
Short name T731
Test name
Test status
Simulation time 83196026743 ps
CPU time 114.81 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:03:08 PM PDT 24
Peak memory 210540 kb
Host smart-0e1cb0dc-d58a-4919-aeda-ce3765c65573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043645773 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1043645773
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3148430623
Short name T411
Test name
Test status
Simulation time 380852045 ps
CPU time 0.69 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:01:00 PM PDT 24
Peak memory 201596 kb
Host smart-de2ef793-7f87-4816-8275-8f642ef46fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148430623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3148430623
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3201843909
Short name T213
Test name
Test status
Simulation time 202082816941 ps
CPU time 436.55 seconds
Started Jul 14 07:01:00 PM PDT 24
Finished Jul 14 07:08:22 PM PDT 24
Peak memory 201896 kb
Host smart-6a6cf3a3-a573-4ebf-b663-f5b4277d1c83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201843909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3201843909
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1936146057
Short name T219
Test name
Test status
Simulation time 342554990702 ps
CPU time 811.8 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:14:24 PM PDT 24
Peak memory 201904 kb
Host smart-27dfcddc-8734-4614-8d83-214a48bf5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936146057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1936146057
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2157183200
Short name T427
Test name
Test status
Simulation time 162450219014 ps
CPU time 352.38 seconds
Started Jul 14 07:01:09 PM PDT 24
Finished Jul 14 07:07:03 PM PDT 24
Peak memory 201960 kb
Host smart-9f18d522-55f2-41e8-9424-d74299f0c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157183200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2157183200
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3880448647
Short name T350
Test name
Test status
Simulation time 482904767641 ps
CPU time 881.88 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:15:33 PM PDT 24
Peak memory 201860 kb
Host smart-dea67750-9fce-428b-a9ef-b55beedec452
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880448647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3880448647
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1749703405
Short name T498
Test name
Test status
Simulation time 327352179296 ps
CPU time 180.66 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:04:03 PM PDT 24
Peak memory 201932 kb
Host smart-1025736c-4770-42e2-8ccf-026c65ff4da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749703405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1749703405
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.78366956
Short name T416
Test name
Test status
Simulation time 485470562199 ps
CPU time 1087.06 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 201880 kb
Host smart-437d2f0c-3a36-457e-91a3-83542b38094c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=78366956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed
.78366956
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.719736551
Short name T297
Test name
Test status
Simulation time 286989719884 ps
CPU time 668.85 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:12:10 PM PDT 24
Peak memory 202096 kb
Host smart-4648ccd3-3b3d-422c-ade4-5f1737735531
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719736551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.719736551
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1648296464
Short name T174
Test name
Test status
Simulation time 202187618006 ps
CPU time 469.26 seconds
Started Jul 14 07:01:00 PM PDT 24
Finished Jul 14 07:08:54 PM PDT 24
Peak memory 201892 kb
Host smart-d4f151ea-9438-4d6d-a003-84a831581f17
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648296464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1648296464
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2293654589
Short name T527
Test name
Test status
Simulation time 108428063640 ps
CPU time 552.97 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:10:01 PM PDT 24
Peak memory 202276 kb
Host smart-c72b9209-d924-475a-8f72-dcb5edcac32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293654589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2293654589
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2100211666
Short name T370
Test name
Test status
Simulation time 40151885840 ps
CPU time 89.56 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:02:31 PM PDT 24
Peak memory 201728 kb
Host smart-0d628e20-67ad-4cef-b2d5-12352635bca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100211666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2100211666
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2046675139
Short name T682
Test name
Test status
Simulation time 4650185528 ps
CPU time 3.84 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:00:57 PM PDT 24
Peak memory 201616 kb
Host smart-b34b8314-5098-4c50-a69f-fb6698c84960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046675139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2046675139
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3941117752
Short name T791
Test name
Test status
Simulation time 5896375314 ps
CPU time 2.81 seconds
Started Jul 14 07:01:04 PM PDT 24
Finished Jul 14 07:01:10 PM PDT 24
Peak memory 201716 kb
Host smart-c772e344-b600-4d23-be2f-8cd77427b9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941117752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3941117752
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4219326412
Short name T206
Test name
Test status
Simulation time 429390655659 ps
CPU time 253.55 seconds
Started Jul 14 07:01:01 PM PDT 24
Finished Jul 14 07:05:19 PM PDT 24
Peak memory 201872 kb
Host smart-597b6eb5-7191-44a4-be88-3546359fe326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219326412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4219326412
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1701633970
Short name T23
Test name
Test status
Simulation time 67688579012 ps
CPU time 168.06 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:03:37 PM PDT 24
Peak memory 210516 kb
Host smart-afb16256-d9bb-4fbc-b8bd-f90152079720
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701633970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1701633970
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1056144194
Short name T376
Test name
Test status
Simulation time 400034778 ps
CPU time 1.12 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:00:57 PM PDT 24
Peak memory 201668 kb
Host smart-6e425600-6e6e-4159-9bbb-80fd6b90da9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056144194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1056144194
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1380630456
Short name T275
Test name
Test status
Simulation time 500640653796 ps
CPU time 195.82 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:04:11 PM PDT 24
Peak memory 201776 kb
Host smart-ac1a55ce-452c-49a1-b731-6ee18254329b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380630456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1380630456
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2027420080
Short name T313
Test name
Test status
Simulation time 331806308881 ps
CPU time 762.17 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:13:37 PM PDT 24
Peak memory 201916 kb
Host smart-351cd591-be3d-4f02-a756-a981a2f0cc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027420080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2027420080
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3325880862
Short name T721
Test name
Test status
Simulation time 323685904867 ps
CPU time 192 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:04:09 PM PDT 24
Peak memory 201816 kb
Host smart-b0ceabe8-5959-4580-a086-1f2d41559335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325880862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3325880862
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2677925990
Short name T93
Test name
Test status
Simulation time 501312400427 ps
CPU time 594.61 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:11:03 PM PDT 24
Peak memory 201888 kb
Host smart-c5fdb544-8d15-4c58-bcc2-de4050c4d677
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677925990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2677925990
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3559500487
Short name T482
Test name
Test status
Simulation time 159705529197 ps
CPU time 173.83 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:03:54 PM PDT 24
Peak memory 201860 kb
Host smart-990650cd-04d1-4527-b834-ee49fdaab113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559500487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3559500487
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2345457138
Short name T358
Test name
Test status
Simulation time 498849629271 ps
CPU time 317.31 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:06:11 PM PDT 24
Peak memory 201808 kb
Host smart-9860a8f3-f508-4ea6-9904-42e21c21bf4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345457138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2345457138
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.4185655831
Short name T259
Test name
Test status
Simulation time 360157219484 ps
CPU time 190.82 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:04:02 PM PDT 24
Peak memory 201952 kb
Host smart-45bb3600-a64c-4f42-bfbc-6a03333eb41d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185655831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.4185655831
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1869816545
Short name T392
Test name
Test status
Simulation time 106240204215 ps
CPU time 422.63 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:08:04 PM PDT 24
Peak memory 202200 kb
Host smart-d2412cdd-3a4d-490c-b317-8c9310b793ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869816545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1869816545
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1536561134
Short name T378
Test name
Test status
Simulation time 47097430923 ps
CPU time 12.2 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:01:15 PM PDT 24
Peak memory 201716 kb
Host smart-e4041315-3e18-4c20-b035-0272fc4d5f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536561134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1536561134
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2477328956
Short name T714
Test name
Test status
Simulation time 3677166315 ps
CPU time 8.89 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:01:02 PM PDT 24
Peak memory 201648 kb
Host smart-f8fecfb3-1d32-4fd7-8cc1-2c5b617c9980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477328956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2477328956
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.547183171
Short name T715
Test name
Test status
Simulation time 5828950216 ps
CPU time 7.56 seconds
Started Jul 14 07:01:08 PM PDT 24
Finished Jul 14 07:01:17 PM PDT 24
Peak memory 201708 kb
Host smart-d2cfb106-dd89-4a46-b230-62fa52b82126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547183171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.547183171
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2382240594
Short name T316
Test name
Test status
Simulation time 337005264083 ps
CPU time 692.98 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:12:30 PM PDT 24
Peak memory 201800 kb
Host smart-79d36a27-be97-454d-9833-dab9a5d1eb54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382240594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2382240594
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.735958110
Short name T745
Test name
Test status
Simulation time 25344814093 ps
CPU time 30.85 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:01:24 PM PDT 24
Peak memory 202004 kb
Host smart-b7c4d84f-eb5c-4e96-b7aa-a1225ade1d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735958110 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.735958110
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3195807174
Short name T609
Test name
Test status
Simulation time 319827692 ps
CPU time 1.29 seconds
Started Jul 14 07:01:05 PM PDT 24
Finished Jul 14 07:01:09 PM PDT 24
Peak memory 201568 kb
Host smart-dba4e149-1d8b-4348-baab-92d8ec9acf5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195807174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3195807174
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1814740953
Short name T265
Test name
Test status
Simulation time 365934303395 ps
CPU time 198.73 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:04:17 PM PDT 24
Peak memory 201844 kb
Host smart-ffabb848-dc08-429a-9ef2-28ff6fe5f799
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814740953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1814740953
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.407251811
Short name T231
Test name
Test status
Simulation time 541289868272 ps
CPU time 315.54 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:06:13 PM PDT 24
Peak memory 201868 kb
Host smart-af915091-37e8-482f-b6a3-abb04104f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407251811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.407251811
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2223511601
Short name T160
Test name
Test status
Simulation time 496052259856 ps
CPU time 78.46 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:02:10 PM PDT 24
Peak memory 201872 kb
Host smart-9cafbc42-2955-4979-9193-4d36204bcaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223511601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2223511601
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1519339596
Short name T344
Test name
Test status
Simulation time 493547310726 ps
CPU time 583.04 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:11:01 PM PDT 24
Peak memory 201824 kb
Host smart-a4574026-20b8-421f-9670-5ec89b44bd34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519339596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1519339596
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3185376960
Short name T281
Test name
Test status
Simulation time 172011548440 ps
CPU time 97.27 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:02:46 PM PDT 24
Peak memory 201960 kb
Host smart-6f5b587e-c3ec-43f2-a657-c4feefab498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185376960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3185376960
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.4235181118
Short name T120
Test name
Test status
Simulation time 477451175909 ps
CPU time 91.36 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:02:36 PM PDT 24
Peak memory 201856 kb
Host smart-a7a072f2-8e98-4331-8408-1a3f3f9c5f9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235181118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.4235181118
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3354666287
Short name T646
Test name
Test status
Simulation time 597540805196 ps
CPU time 333.43 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:06:50 PM PDT 24
Peak memory 201892 kb
Host smart-12390d99-e3e0-40ab-9bf1-71f362099602
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354666287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3354666287
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3338629328
Short name T658
Test name
Test status
Simulation time 103508849516 ps
CPU time 315.65 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:06:34 PM PDT 24
Peak memory 202192 kb
Host smart-dcc0e750-fdb1-44e7-aa1e-05af9522d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338629328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3338629328
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.4249537163
Short name T395
Test name
Test status
Simulation time 35079760111 ps
CPU time 19.48 seconds
Started Jul 14 07:01:02 PM PDT 24
Finished Jul 14 07:01:25 PM PDT 24
Peak memory 201704 kb
Host smart-740def59-81e3-4d52-939c-1cf3c38b2584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249537163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.4249537163
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4258998455
Short name T524
Test name
Test status
Simulation time 5332743676 ps
CPU time 12.92 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:01:01 PM PDT 24
Peak memory 201688 kb
Host smart-f4b85084-0f6b-4a83-8186-c819a7661496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258998455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4258998455
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1943468007
Short name T586
Test name
Test status
Simulation time 5751090860 ps
CPU time 13.14 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:01:14 PM PDT 24
Peak memory 201708 kb
Host smart-0e79cea2-ea81-4989-ac06-0169bf95093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943468007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1943468007
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.332021800
Short name T50
Test name
Test status
Simulation time 251155343665 ps
CPU time 226.91 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:04:42 PM PDT 24
Peak memory 210576 kb
Host smart-b77b4c41-9685-4b1d-b542-0f86f405a46f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332021800 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.332021800
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4144320826
Short name T28
Test name
Test status
Simulation time 418709574 ps
CPU time 1.5 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:01:12 PM PDT 24
Peak memory 201652 kb
Host smart-892825a8-ae70-42c5-a099-d0372efca5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144320826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4144320826
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.127595180
Short name T248
Test name
Test status
Simulation time 331123565055 ps
CPU time 641.19 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:11:44 PM PDT 24
Peak memory 201980 kb
Host smart-f481f557-d15f-44e6-accf-1f03d61a0aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127595180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.127595180
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.4134554636
Short name T443
Test name
Test status
Simulation time 327308510580 ps
CPU time 794.23 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:14:28 PM PDT 24
Peak memory 201816 kb
Host smart-b6ae42c8-3a66-46f2-abd1-053e7e4cb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134554636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4134554636
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2680690380
Short name T663
Test name
Test status
Simulation time 323445954446 ps
CPU time 402.86 seconds
Started Jul 14 07:01:01 PM PDT 24
Finished Jul 14 07:07:48 PM PDT 24
Peak memory 201856 kb
Host smart-0e08fd03-d0b1-40d6-8bb9-4c81f641091b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680690380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2680690380
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2724171253
Short name T642
Test name
Test status
Simulation time 495315938357 ps
CPU time 1119.63 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:19:39 PM PDT 24
Peak memory 201972 kb
Host smart-0be8033c-6cfd-40e2-b893-b928c214e255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724171253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2724171253
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.292350982
Short name T544
Test name
Test status
Simulation time 325603316497 ps
CPU time 165.24 seconds
Started Jul 14 07:01:09 PM PDT 24
Finished Jul 14 07:03:55 PM PDT 24
Peak memory 201892 kb
Host smart-cd91a5da-4b21-43d3-bb00-7dad02b38adb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=292350982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.292350982
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2892204561
Short name T46
Test name
Test status
Simulation time 373468841635 ps
CPU time 530.88 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:09:55 PM PDT 24
Peak memory 201908 kb
Host smart-4007c43c-46eb-4bf5-aaca-92478b3a93b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892204561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2892204561
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1460739471
Short name T460
Test name
Test status
Simulation time 204307179475 ps
CPU time 112.51 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:03:05 PM PDT 24
Peak memory 201864 kb
Host smart-da8dd344-24a2-4d81-973c-e0417559353a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460739471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1460739471
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2682172480
Short name T679
Test name
Test status
Simulation time 75135092991 ps
CPU time 236.16 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:04:53 PM PDT 24
Peak memory 202128 kb
Host smart-d2879989-3c98-4b3c-a68a-59d320a6e0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682172480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2682172480
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2691699811
Short name T389
Test name
Test status
Simulation time 30747339389 ps
CPU time 69.31 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:02:26 PM PDT 24
Peak memory 201724 kb
Host smart-f154e774-a6d0-4187-83cc-9952e64272a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691699811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2691699811
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.979466216
Short name T402
Test name
Test status
Simulation time 3723417165 ps
CPU time 5.05 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:01:21 PM PDT 24
Peak memory 201584 kb
Host smart-920ea2a8-0a98-4af2-bb3e-81402bcfd001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979466216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.979466216
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.6895552
Short name T666
Test name
Test status
Simulation time 6005240234 ps
CPU time 6.9 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:01:26 PM PDT 24
Peak memory 201692 kb
Host smart-59977c43-d617-403e-9ec7-bbdba97fd9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6895552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.6895552
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.564665082
Short name T308
Test name
Test status
Simulation time 673669976079 ps
CPU time 1591.25 seconds
Started Jul 14 07:00:55 PM PDT 24
Finished Jul 14 07:27:32 PM PDT 24
Peak memory 201912 kb
Host smart-fd38ea61-00d3-4d1c-a5e7-61fce7667ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564665082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
564665082
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2205273283
Short name T372
Test name
Test status
Simulation time 389349645 ps
CPU time 0.85 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:00:52 PM PDT 24
Peak memory 201640 kb
Host smart-2fce51b1-8053-43c4-8a65-5a6543861830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205273283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2205273283
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1775323594
Short name T269
Test name
Test status
Simulation time 520882398070 ps
CPU time 898.51 seconds
Started Jul 14 07:01:08 PM PDT 24
Finished Jul 14 07:16:08 PM PDT 24
Peak memory 201908 kb
Host smart-534e6aa1-bd0b-4a2e-a5a1-142cab7c86d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775323594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1775323594
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.273433374
Short name T764
Test name
Test status
Simulation time 160646863883 ps
CPU time 87.6 seconds
Started Jul 14 07:00:58 PM PDT 24
Finished Jul 14 07:02:31 PM PDT 24
Peak memory 202124 kb
Host smart-99a2567d-72f4-4d2a-8abd-14873719809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273433374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.273433374
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.238720678
Short name T536
Test name
Test status
Simulation time 327867267165 ps
CPU time 206.4 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:04:44 PM PDT 24
Peak memory 201968 kb
Host smart-8a22e10d-0a37-4a8a-be5a-275319f0ff83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=238720678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.238720678
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1587285908
Short name T150
Test name
Test status
Simulation time 494926367308 ps
CPU time 272.87 seconds
Started Jul 14 07:01:20 PM PDT 24
Finished Jul 14 07:05:56 PM PDT 24
Peak memory 201772 kb
Host smart-3a38a030-d8db-4fd1-b2ca-846ae343ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587285908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1587285908
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.62382265
Short name T681
Test name
Test status
Simulation time 322340405860 ps
CPU time 740.66 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 201672 kb
Host smart-e81533be-3f46-4536-b3c6-6efc78901cd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=62382265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed
.62382265
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1633467786
Short name T729
Test name
Test status
Simulation time 192033649176 ps
CPU time 222.28 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:04:41 PM PDT 24
Peak memory 201956 kb
Host smart-4458cc4c-9e76-4f4e-985b-302df56e7b63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633467786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1633467786
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3902578127
Short name T355
Test name
Test status
Simulation time 205713680032 ps
CPU time 129.8 seconds
Started Jul 14 07:01:03 PM PDT 24
Finished Jul 14 07:03:16 PM PDT 24
Peak memory 201880 kb
Host smart-0b0b2f27-f70f-42f7-8b35-7f151ba7a3b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902578127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3902578127
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3536851385
Short name T605
Test name
Test status
Simulation time 22677764791 ps
CPU time 50.77 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:02:02 PM PDT 24
Peak memory 201736 kb
Host smart-add9f6b4-142e-43b1-9b37-13557bb374ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536851385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3536851385
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.773402264
Short name T9
Test name
Test status
Simulation time 5069975234 ps
CPU time 11.97 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:01:31 PM PDT 24
Peak memory 201704 kb
Host smart-cbcf34d2-4dc3-44bb-a4d9-fe956826e070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773402264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.773402264
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.80451331
Short name T364
Test name
Test status
Simulation time 5781538550 ps
CPU time 13.09 seconds
Started Jul 14 07:00:55 PM PDT 24
Finished Jul 14 07:01:13 PM PDT 24
Peak memory 201716 kb
Host smart-fb107ff4-d81d-4871-bfeb-b01c505813b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80451331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.80451331
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.37249113
Short name T202
Test name
Test status
Simulation time 559483148507 ps
CPU time 1726.5 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:30:00 PM PDT 24
Peak memory 210456 kb
Host smart-23965ea8-555f-4673-aa30-ea3d90aea9fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37249113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.37249113
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1262838537
Short name T318
Test name
Test status
Simulation time 52882335634 ps
CPU time 68.09 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:02:12 PM PDT 24
Peak memory 210296 kb
Host smart-31b0779d-2649-4f75-847e-c6d01e3db347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262838537 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1262838537
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1101281850
Short name T35
Test name
Test status
Simulation time 343033129 ps
CPU time 0.81 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:01:14 PM PDT 24
Peak memory 201520 kb
Host smart-d43fba92-bd73-475a-874f-a234084eed13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101281850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1101281850
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2123046852
Short name T328
Test name
Test status
Simulation time 493403216863 ps
CPU time 520.93 seconds
Started Jul 14 07:01:01 PM PDT 24
Finished Jul 14 07:09:47 PM PDT 24
Peak memory 201800 kb
Host smart-e7b70fb0-a0db-4ba1-9f7d-0c4739b4e69d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123046852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2123046852
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2119429527
Short name T787
Test name
Test status
Simulation time 483074524602 ps
CPU time 118.09 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:02:56 PM PDT 24
Peak memory 201816 kb
Host smart-53bcf5ac-9efc-451d-9b30-15c00567901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119429527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2119429527
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3019662252
Short name T388
Test name
Test status
Simulation time 167420347633 ps
CPU time 198.55 seconds
Started Jul 14 07:01:03 PM PDT 24
Finished Jul 14 07:04:25 PM PDT 24
Peak memory 201828 kb
Host smart-e2b0797f-8a9d-49b2-9c33-97eb30f4df94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019662252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3019662252
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3740279158
Short name T152
Test name
Test status
Simulation time 490454052518 ps
CPU time 590.56 seconds
Started Jul 14 07:00:58 PM PDT 24
Finished Jul 14 07:10:54 PM PDT 24
Peak memory 201984 kb
Host smart-bc93a452-a4c3-4b31-8c16-7270356fb9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740279158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3740279158
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3225895287
Short name T408
Test name
Test status
Simulation time 331376994111 ps
CPU time 759.1 seconds
Started Jul 14 07:01:01 PM PDT 24
Finished Jul 14 07:13:45 PM PDT 24
Peak memory 201856 kb
Host smart-70268aab-6805-4ad4-b8d4-4b189b9c2807
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225895287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3225895287
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4224093317
Short name T529
Test name
Test status
Simulation time 195626174459 ps
CPU time 226.86 seconds
Started Jul 14 07:01:05 PM PDT 24
Finished Jul 14 07:04:55 PM PDT 24
Peak memory 201868 kb
Host smart-4f364a89-2127-4bdf-b320-ab435e76bce6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224093317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4224093317
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3037925177
Short name T485
Test name
Test status
Simulation time 31174467599 ps
CPU time 64.53 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:02:18 PM PDT 24
Peak memory 201616 kb
Host smart-229a521b-b70c-43d4-8938-d20a3a1a9266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037925177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3037925177
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1203903966
Short name T523
Test name
Test status
Simulation time 3020775060 ps
CPU time 7.7 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:01:10 PM PDT 24
Peak memory 201672 kb
Host smart-22143b03-a5ce-489e-8592-d13aa2ba6955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203903966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1203903966
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2390053037
Short name T511
Test name
Test status
Simulation time 5713491179 ps
CPU time 2.05 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:01:13 PM PDT 24
Peak memory 201648 kb
Host smart-3adb721d-53fd-4a05-9ab7-75abd2734bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390053037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2390053037
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2391393413
Short name T784
Test name
Test status
Simulation time 19960607040 ps
CPU time 50.01 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:02:08 PM PDT 24
Peak memory 210192 kb
Host smart-527347a0-c919-43d2-9e88-c30f61c195e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391393413 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2391393413
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.4115259601
Short name T651
Test name
Test status
Simulation time 342796149 ps
CPU time 0.98 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:01:22 PM PDT 24
Peak memory 201648 kb
Host smart-5ee88e59-425e-4a85-8c6c-78b6a4a21bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115259601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.4115259601
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1100577
Short name T327
Test name
Test status
Simulation time 337770903514 ps
CPU time 217.68 seconds
Started Jul 14 07:01:03 PM PDT 24
Finished Jul 14 07:04:45 PM PDT 24
Peak memory 201880 kb
Host smart-769af046-db05-4c1e-9861-f4179f536c1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.1100577
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3294806571
Short name T770
Test name
Test status
Simulation time 330242496519 ps
CPU time 714.3 seconds
Started Jul 14 07:01:02 PM PDT 24
Finished Jul 14 07:13:01 PM PDT 24
Peak memory 201904 kb
Host smart-eee96091-2fe0-4ee4-94a4-e7098b57e312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294806571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3294806571
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.876292287
Short name T762
Test name
Test status
Simulation time 163442282085 ps
CPU time 336.7 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:06:57 PM PDT 24
Peak memory 201808 kb
Host smart-36beb219-b414-49f3-afaf-1b8928cc191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876292287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.876292287
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1054202917
Short name T521
Test name
Test status
Simulation time 165885164866 ps
CPU time 101.4 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:03:04 PM PDT 24
Peak memory 201728 kb
Host smart-01ba661d-2509-42b7-a80a-804d2cea2a43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054202917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1054202917
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1336439679
Short name T205
Test name
Test status
Simulation time 489884220423 ps
CPU time 505.39 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:09:41 PM PDT 24
Peak memory 201876 kb
Host smart-ec3d96db-34f7-4be5-8b03-b022569156b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336439679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1336439679
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2345583903
Short name T767
Test name
Test status
Simulation time 163287841475 ps
CPU time 90.28 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:02:48 PM PDT 24
Peak memory 201884 kb
Host smart-70e7d105-9bde-4c52-8e13-e64c8f373728
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345583903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2345583903
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2834554599
Short name T111
Test name
Test status
Simulation time 182710386203 ps
CPU time 200.55 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 201900 kb
Host smart-381731ef-1a6e-4230-8c89-e871b53bf446
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834554599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2834554599
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.363933746
Short name T373
Test name
Test status
Simulation time 212057310949 ps
CPU time 421.14 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:08:01 PM PDT 24
Peak memory 201896 kb
Host smart-d481b7da-f3c5-4bd4-ad76-6678707612c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363933746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.363933746
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4014982649
Short name T720
Test name
Test status
Simulation time 109638258864 ps
CPU time 602.9 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:11:20 PM PDT 24
Peak memory 202192 kb
Host smart-582c828e-ceb2-4b5b-9c7a-9b2736117317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014982649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4014982649
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1890418837
Short name T394
Test name
Test status
Simulation time 30792161425 ps
CPU time 66.17 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:02:13 PM PDT 24
Peak memory 201660 kb
Host smart-5578111f-bce2-43ff-96e7-a39bc90566cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890418837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1890418837
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1124295956
Short name T414
Test name
Test status
Simulation time 4516637427 ps
CPU time 1.53 seconds
Started Jul 14 07:01:09 PM PDT 24
Finished Jul 14 07:01:12 PM PDT 24
Peak memory 201676 kb
Host smart-2bbfbd85-2403-4e62-8a1b-855a3b9cc2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124295956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1124295956
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.815053801
Short name T645
Test name
Test status
Simulation time 5606318060 ps
CPU time 12.43 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:01:14 PM PDT 24
Peak memory 201728 kb
Host smart-a4f66e33-c25b-4b34-922e-8af8c7a1230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815053801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.815053801
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3718070990
Short name T154
Test name
Test status
Simulation time 522163313592 ps
CPU time 167.23 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:03:49 PM PDT 24
Peak memory 201880 kb
Host smart-ff9e5683-1762-4bb7-b4a3-adbf830e9fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718070990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3718070990
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.696369742
Short name T419
Test name
Test status
Simulation time 508522785 ps
CPU time 1.73 seconds
Started Jul 14 07:01:02 PM PDT 24
Finished Jul 14 07:01:08 PM PDT 24
Peak memory 201628 kb
Host smart-b47870fb-f0fb-48ae-842f-03641f791de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696369742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.696369742
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3465245591
Short name T324
Test name
Test status
Simulation time 360630870946 ps
CPU time 751.27 seconds
Started Jul 14 07:00:41 PM PDT 24
Finished Jul 14 07:13:13 PM PDT 24
Peak memory 201872 kb
Host smart-144b6abd-6c83-465c-9318-875c7f03e5d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465245591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3465245591
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3918109292
Short name T596
Test name
Test status
Simulation time 562883418012 ps
CPU time 317.29 seconds
Started Jul 14 07:00:34 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 201944 kb
Host smart-b0be578f-73d5-4652-a51f-29b04ea171b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918109292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3918109292
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.392839177
Short name T41
Test name
Test status
Simulation time 322577278513 ps
CPU time 158.04 seconds
Started Jul 14 07:00:22 PM PDT 24
Finished Jul 14 07:03:07 PM PDT 24
Peak memory 201884 kb
Host smart-653a7d80-48f5-4de9-9a48-55a600274496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392839177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.392839177
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3850604408
Short name T501
Test name
Test status
Simulation time 494178351513 ps
CPU time 1057.93 seconds
Started Jul 14 07:00:39 PM PDT 24
Finished Jul 14 07:18:18 PM PDT 24
Peak memory 201824 kb
Host smart-d4443c17-c524-45ea-af1b-689e7d56b1b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850604408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3850604408
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.893922277
Short name T251
Test name
Test status
Simulation time 166765358848 ps
CPU time 191.89 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:04:10 PM PDT 24
Peak memory 201988 kb
Host smart-38bb0a72-89f0-4bcd-b0ab-18bc3be6710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893922277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.893922277
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.863158670
Short name T627
Test name
Test status
Simulation time 168222269266 ps
CPU time 206.82 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:04:04 PM PDT 24
Peak memory 201828 kb
Host smart-f2c8eebd-bbad-4c17-bda1-139114f2f303
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=863158670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.863158670
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1646153669
Short name T272
Test name
Test status
Simulation time 177846080971 ps
CPU time 396.06 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:07:10 PM PDT 24
Peak memory 201920 kb
Host smart-b732304e-57d1-44f5-965e-ed8104410a2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646153669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1646153669
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2226387604
Short name T342
Test name
Test status
Simulation time 600608057221 ps
CPU time 458.23 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:08:27 PM PDT 24
Peak memory 201840 kb
Host smart-66dcbf49-4225-42e3-a47c-4daf5afcf1c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226387604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2226387604
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1534831909
Short name T676
Test name
Test status
Simulation time 143631339258 ps
CPU time 529.94 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:09:42 PM PDT 24
Peak memory 201964 kb
Host smart-20f58dc3-9e49-48e4-aa1f-117521c691bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534831909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1534831909
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3910262679
Short name T418
Test name
Test status
Simulation time 47241899158 ps
CPU time 31.18 seconds
Started Jul 14 07:00:32 PM PDT 24
Finished Jul 14 07:01:07 PM PDT 24
Peak memory 201704 kb
Host smart-9468a2ac-4081-4ae4-9a05-d888ef99ec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910262679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3910262679
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3088570576
Short name T496
Test name
Test status
Simulation time 3458299316 ps
CPU time 1.46 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:00:35 PM PDT 24
Peak memory 201704 kb
Host smart-73e54624-9325-4ae5-90e1-60c24a37a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088570576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3088570576
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2986607527
Short name T81
Test name
Test status
Simulation time 8240145570 ps
CPU time 15.38 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:01:12 PM PDT 24
Peak memory 218208 kb
Host smart-040365b9-4aa0-489c-9be6-89b46501b4ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986607527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2986607527
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1966742320
Short name T513
Test name
Test status
Simulation time 5858139033 ps
CPU time 14.54 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:00:58 PM PDT 24
Peak memory 201652 kb
Host smart-99a56053-6144-43ac-af61-0e1ed38c46eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966742320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1966742320
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1673436681
Short name T698
Test name
Test status
Simulation time 235864033052 ps
CPU time 256.79 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:05:21 PM PDT 24
Peak memory 201876 kb
Host smart-4ca12da6-71b6-45bf-8a2d-7b40e265fe74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673436681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1673436681
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3673728178
Short name T12
Test name
Test status
Simulation time 181603215267 ps
CPU time 105.28 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:02:34 PM PDT 24
Peak memory 210608 kb
Host smart-7bdffa4f-d3fb-4f74-b2b7-bc81a01b7f65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673728178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3673728178
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1022166725
Short name T603
Test name
Test status
Simulation time 520276416 ps
CPU time 1.2 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:01:15 PM PDT 24
Peak memory 201520 kb
Host smart-0a1f890b-072e-4f96-9aa0-09d8cd507c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022166725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1022166725
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2307978009
Short name T600
Test name
Test status
Simulation time 501174970200 ps
CPU time 1086.01 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:19:08 PM PDT 24
Peak memory 201988 kb
Host smart-01dd4531-5e71-4b56-9ffa-2c4b6590fe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307978009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2307978009
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1620524547
Short name T589
Test name
Test status
Simulation time 164368967494 ps
CPU time 28.97 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:01:30 PM PDT 24
Peak memory 201852 kb
Host smart-cf842a5c-563e-421d-a53a-43aa69bc2b5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620524547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1620524547
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2533090466
Short name T657
Test name
Test status
Simulation time 491923162566 ps
CPU time 66.66 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:02:08 PM PDT 24
Peak memory 201912 kb
Host smart-3807f32c-3842-4f2f-b2a7-1fc96f9ab6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533090466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2533090466
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1338140502
Short name T504
Test name
Test status
Simulation time 163716690600 ps
CPU time 357.63 seconds
Started Jul 14 07:00:58 PM PDT 24
Finished Jul 14 07:07:01 PM PDT 24
Peak memory 202056 kb
Host smart-7014ee72-4379-4761-ba40-8c3a343d9941
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338140502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1338140502
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2633465299
Short name T713
Test name
Test status
Simulation time 364430701828 ps
CPU time 811.8 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:14:58 PM PDT 24
Peak memory 201772 kb
Host smart-d7873495-3f7a-43b1-9bc5-f3c785424262
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633465299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2633465299
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1300363117
Short name T476
Test name
Test status
Simulation time 394601337461 ps
CPU time 235.35 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:05:08 PM PDT 24
Peak memory 201900 kb
Host smart-b4f57e5c-250a-4dc9-ad7c-d85929d9191c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300363117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1300363117
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2339673845
Short name T539
Test name
Test status
Simulation time 122543350735 ps
CPU time 496.82 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:09:34 PM PDT 24
Peak memory 202272 kb
Host smart-2562074d-3820-41e2-85e1-b18cdf730c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339673845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2339673845
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2539324827
Short name T737
Test name
Test status
Simulation time 34705535087 ps
CPU time 73.22 seconds
Started Jul 14 07:01:26 PM PDT 24
Finished Jul 14 07:02:40 PM PDT 24
Peak memory 201560 kb
Host smart-90cecb5f-28cb-4bbe-8d3f-73323ba47fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539324827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2539324827
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2418117335
Short name T397
Test name
Test status
Simulation time 4626850645 ps
CPU time 10.62 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:01:26 PM PDT 24
Peak memory 201716 kb
Host smart-aac7aa4f-ce56-4337-b9af-380b4136402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418117335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2418117335
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1678038495
Short name T390
Test name
Test status
Simulation time 5667610710 ps
CPU time 14.02 seconds
Started Jul 14 07:00:55 PM PDT 24
Finished Jul 14 07:01:14 PM PDT 24
Peak memory 201712 kb
Host smart-fe9310d4-017b-4818-8247-d924bcb36ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678038495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1678038495
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2985465559
Short name T400
Test name
Test status
Simulation time 146653004674 ps
CPU time 736.1 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:13:19 PM PDT 24
Peak memory 202232 kb
Host smart-ee7998b9-f800-4808-91fe-2b147cc8b294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985465559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2985465559
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1221648007
Short name T505
Test name
Test status
Simulation time 24375350413 ps
CPU time 57.19 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:02:13 PM PDT 24
Peak memory 202036 kb
Host smart-21a61b32-8296-4664-889f-bab2740da5d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221648007 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1221648007
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1837879343
Short name T738
Test name
Test status
Simulation time 355814960 ps
CPU time 0.98 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:01:23 PM PDT 24
Peak memory 201592 kb
Host smart-74848a2c-a883-4839-8e9c-b7115d28a8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837879343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1837879343
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.417373171
Short name T717
Test name
Test status
Simulation time 329723011343 ps
CPU time 770.42 seconds
Started Jul 14 07:01:26 PM PDT 24
Finished Jul 14 07:14:18 PM PDT 24
Peak memory 201940 kb
Host smart-2172971d-b88b-4863-8bfd-914d60e25d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417373171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.417373171
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4121690906
Short name T641
Test name
Test status
Simulation time 333862527540 ps
CPU time 169.59 seconds
Started Jul 14 07:01:22 PM PDT 24
Finished Jul 14 07:04:14 PM PDT 24
Peak memory 201748 kb
Host smart-c72d2492-1bd4-4322-85f0-ee9b269902f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121690906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4121690906
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3596300309
Short name T727
Test name
Test status
Simulation time 159518622657 ps
CPU time 358.32 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:07:12 PM PDT 24
Peak memory 201908 kb
Host smart-d2a68cbe-9223-4605-9982-976ffe014851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596300309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3596300309
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2231810172
Short name T619
Test name
Test status
Simulation time 330802027264 ps
CPU time 685.79 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:12:45 PM PDT 24
Peak memory 201884 kb
Host smart-76ae0dc8-daba-41c1-8e51-5856f5096ea3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231810172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2231810172
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3243386791
Short name T310
Test name
Test status
Simulation time 516837540562 ps
CPU time 276.53 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:06:03 PM PDT 24
Peak memory 201772 kb
Host smart-e2d4ee22-494d-4f3a-a4d7-8fb346063e17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243386791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3243386791
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3410260294
Short name T361
Test name
Test status
Simulation time 208620047472 ps
CPU time 113.33 seconds
Started Jul 14 07:01:01 PM PDT 24
Finished Jul 14 07:02:59 PM PDT 24
Peak memory 201868 kb
Host smart-be35cc58-d4cd-4b29-bfcf-3835f1773634
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410260294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3410260294
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3255255398
Short name T31
Test name
Test status
Simulation time 95680755629 ps
CPU time 437.02 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:08:35 PM PDT 24
Peak memory 202224 kb
Host smart-58e994f5-b003-47d0-8ac7-b5945c5552bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255255398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3255255398
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2581820893
Short name T429
Test name
Test status
Simulation time 25969943679 ps
CPU time 29.2 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:01:47 PM PDT 24
Peak memory 201684 kb
Host smart-20170e19-e691-4a0c-9209-2a387d946540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581820893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2581820893
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.358165620
Short name T573
Test name
Test status
Simulation time 2816341841 ps
CPU time 2.12 seconds
Started Jul 14 07:01:02 PM PDT 24
Finished Jul 14 07:01:08 PM PDT 24
Peak memory 201716 kb
Host smart-6db551c4-b3e8-4241-ae68-325c9c092f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358165620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.358165620
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2175623875
Short name T635
Test name
Test status
Simulation time 5975120004 ps
CPU time 4.06 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:01:21 PM PDT 24
Peak memory 201720 kb
Host smart-cd313beb-e511-4ecc-959b-047800265839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175623875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2175623875
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.4078400957
Short name T334
Test name
Test status
Simulation time 194207636756 ps
CPU time 658.82 seconds
Started Jul 14 07:01:00 PM PDT 24
Finished Jul 14 07:12:04 PM PDT 24
Peak memory 210416 kb
Host smart-3f579bff-14ae-4aa1-a435-39b2fbc24575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078400957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.4078400957
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1223070673
Short name T91
Test name
Test status
Simulation time 77910385281 ps
CPU time 154.52 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:03:53 PM PDT 24
Peak memory 210448 kb
Host smart-7a96a4d8-ee2f-46f1-b39a-c6ab32c1765b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223070673 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1223070673
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2976524459
Short name T503
Test name
Test status
Simulation time 425504427 ps
CPU time 1.52 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:01:18 PM PDT 24
Peak memory 201520 kb
Host smart-b8880d4c-be44-4c13-a285-6bd2060dd513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976524459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2976524459
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.542675762
Short name T690
Test name
Test status
Simulation time 355200267653 ps
CPU time 199.23 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:04:39 PM PDT 24
Peak memory 201880 kb
Host smart-132735de-76cb-403c-867b-a81083be967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542675762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.542675762
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2735196011
Short name T542
Test name
Test status
Simulation time 329131514569 ps
CPU time 338.54 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:06:41 PM PDT 24
Peak memory 201828 kb
Host smart-e52e0c58-1e86-4c8b-b278-ee900f6a67d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735196011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2735196011
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3193910004
Short name T149
Test name
Test status
Simulation time 501024559236 ps
CPU time 1061.04 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:18:58 PM PDT 24
Peak memory 201812 kb
Host smart-3b6c249d-57bf-4519-9560-62154342d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193910004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3193910004
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2258198840
Short name T446
Test name
Test status
Simulation time 498304589154 ps
CPU time 1105.52 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:19:37 PM PDT 24
Peak memory 201960 kb
Host smart-0ab75719-6ff2-44bd-bf45-83a17f5d6d44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258198840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2258198840
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3826158509
Short name T740
Test name
Test status
Simulation time 587104951138 ps
CPU time 328.45 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:06:40 PM PDT 24
Peak memory 201912 kb
Host smart-30fd3c1a-c0ad-42e8-b19f-67d952c21d81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826158509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3826158509
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.15445952
Short name T368
Test name
Test status
Simulation time 620391573085 ps
CPU time 356.61 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:07:00 PM PDT 24
Peak memory 201896 kb
Host smart-4a3cdb1d-1b3e-46fe-916b-bd62ce6eab2c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15445952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
dc_ctrl_filters_wakeup_fixed.15445952
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2522936028
Short name T560
Test name
Test status
Simulation time 67625818467 ps
CPU time 343.1 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:07:04 PM PDT 24
Peak memory 202204 kb
Host smart-42abe458-d42a-4a4e-8392-c84543f1bb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522936028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2522936028
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3632005420
Short name T432
Test name
Test status
Simulation time 42976217565 ps
CPU time 103.88 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:02:47 PM PDT 24
Peak memory 201696 kb
Host smart-bc38798d-0820-4103-8081-bab3cb809a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632005420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3632005420
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2557951532
Short name T678
Test name
Test status
Simulation time 3661232204 ps
CPU time 5.31 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:01:28 PM PDT 24
Peak memory 201700 kb
Host smart-c76836ad-decc-4501-9963-e4ad0a192525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557951532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2557951532
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3126013984
Short name T146
Test name
Test status
Simulation time 5758389646 ps
CPU time 12.33 seconds
Started Jul 14 07:00:55 PM PDT 24
Finished Jul 14 07:01:13 PM PDT 24
Peak memory 201700 kb
Host smart-03925c75-9235-4977-8959-75dffaa32843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126013984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3126013984
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.4037175709
Short name T306
Test name
Test status
Simulation time 334222206861 ps
CPU time 708.27 seconds
Started Jul 14 07:01:08 PM PDT 24
Finished Jul 14 07:12:58 PM PDT 24
Peak memory 201968 kb
Host smart-08828678-8f12-4b69-aaa0-d5f461c2c705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037175709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.4037175709
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1794109297
Short name T486
Test name
Test status
Simulation time 525502359 ps
CPU time 0.77 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:01:23 PM PDT 24
Peak memory 201664 kb
Host smart-ea6d6cf4-7407-4b2d-9134-3144a79b8842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794109297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1794109297
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4099786086
Short name T555
Test name
Test status
Simulation time 168810625948 ps
CPU time 72.68 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:02:27 PM PDT 24
Peak memory 201880 kb
Host smart-8480dc5d-5472-4ed5-bff8-f8445520fdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099786086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4099786086
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.161833271
Short name T305
Test name
Test status
Simulation time 163076367303 ps
CPU time 192.48 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:04:30 PM PDT 24
Peak memory 201912 kb
Host smart-a975494d-74fb-488d-997d-9b303eb797cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161833271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.161833271
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2522142393
Short name T757
Test name
Test status
Simulation time 326623254848 ps
CPU time 742.31 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:13:40 PM PDT 24
Peak memory 201796 kb
Host smart-faa96073-524d-47e2-b1f2-7c5dc3cfdd07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522142393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2522142393
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2806348803
Short name T744
Test name
Test status
Simulation time 500370091953 ps
CPU time 1023.88 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:18:30 PM PDT 24
Peak memory 201964 kb
Host smart-39a80475-8dd7-4954-a699-5043665b0039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806348803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2806348803
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2705793365
Short name T166
Test name
Test status
Simulation time 494053878863 ps
CPU time 285.63 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:06:06 PM PDT 24
Peak memory 201824 kb
Host smart-acdeea2e-4ece-4f34-a7fb-b8c85eaccafa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705793365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2705793365
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3714675966
Short name T772
Test name
Test status
Simulation time 558204558475 ps
CPU time 875.25 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:15:54 PM PDT 24
Peak memory 201972 kb
Host smart-85efdf63-3106-4839-9bb8-abed9c49998f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714675966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3714675966
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3528298789
Short name T351
Test name
Test status
Simulation time 195642091993 ps
CPU time 392.14 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 201864 kb
Host smart-8b61a920-a58f-432e-b191-f7b225726470
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528298789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3528298789
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1781323793
Short name T724
Test name
Test status
Simulation time 41722735954 ps
CPU time 7.25 seconds
Started Jul 14 07:01:09 PM PDT 24
Finished Jul 14 07:01:17 PM PDT 24
Peak memory 201912 kb
Host smart-7b9366f5-7db8-4795-9fcd-2ccaf8349445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781323793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1781323793
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.600955072
Short name T88
Test name
Test status
Simulation time 3133168391 ps
CPU time 7.52 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:01:26 PM PDT 24
Peak memory 201684 kb
Host smart-3e2d93a3-c7e9-4400-ba8d-2ebbbc0edda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600955072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.600955072
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.261153401
Short name T607
Test name
Test status
Simulation time 6057505900 ps
CPU time 14.87 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:01:34 PM PDT 24
Peak memory 201524 kb
Host smart-79da7919-d301-44d6-8696-06929344abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261153401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.261153401
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3106596553
Short name T207
Test name
Test status
Simulation time 234879173748 ps
CPU time 49.27 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:02:11 PM PDT 24
Peak memory 201952 kb
Host smart-c19d6d94-fb72-4846-b76e-dacc933553d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106596553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3106596553
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2595038762
Short name T253
Test name
Test status
Simulation time 177667689852 ps
CPU time 108.8 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:03:08 PM PDT 24
Peak memory 210544 kb
Host smart-7ad97171-ad04-42e1-ba2a-dee43a0467cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595038762 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2595038762
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4012221709
Short name T440
Test name
Test status
Simulation time 389710429 ps
CPU time 1.06 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:01:13 PM PDT 24
Peak memory 201620 kb
Host smart-aeff6488-9ae3-4ebd-a997-441f2472c9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012221709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4012221709
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.496928333
Short name T188
Test name
Test status
Simulation time 641052198984 ps
CPU time 124.91 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:03:16 PM PDT 24
Peak memory 201884 kb
Host smart-3c3c8fce-0cb9-42e8-9f7b-b0261bad3f24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496928333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.496928333
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.264785172
Short name T276
Test name
Test status
Simulation time 331056535686 ps
CPU time 401.87 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:08:03 PM PDT 24
Peak memory 201812 kb
Host smart-5276d26e-e06a-48e7-848c-06848d190d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264785172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.264785172
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3152470513
Short name T535
Test name
Test status
Simulation time 330752727573 ps
CPU time 732.76 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:13:32 PM PDT 24
Peak memory 201900 kb
Host smart-7eab3ba9-6746-4e19-add7-2c98963ffd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152470513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3152470513
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3309003856
Short name T688
Test name
Test status
Simulation time 496097571494 ps
CPU time 1117.48 seconds
Started Jul 14 07:01:26 PM PDT 24
Finished Jul 14 07:20:05 PM PDT 24
Peak memory 201880 kb
Host smart-b4e1d3e3-dde9-4867-97d8-04c7ce5618d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309003856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3309003856
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1195263948
Short name T147
Test name
Test status
Simulation time 161443347747 ps
CPU time 169.83 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:04:15 PM PDT 24
Peak memory 201876 kb
Host smart-81b5c232-e582-4e43-b7b0-1fc19175159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195263948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1195263948
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1697078980
Short name T176
Test name
Test status
Simulation time 166790997102 ps
CPU time 376.35 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 201928 kb
Host smart-c097a20a-e745-4dd0-bffb-e333dc2c4147
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697078980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1697078980
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1724656510
Short name T87
Test name
Test status
Simulation time 340483046913 ps
CPU time 732.22 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 201888 kb
Host smart-3aa6aa67-67db-474d-a9a7-d8a15148c3f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724656510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1724656510
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.707454229
Short name T565
Test name
Test status
Simulation time 583258175387 ps
CPU time 654.68 seconds
Started Jul 14 07:01:17 PM PDT 24
Finished Jul 14 07:12:16 PM PDT 24
Peak memory 201868 kb
Host smart-b13c3e6e-51a7-46f9-a883-6e106459926f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707454229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.707454229
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3531322905
Short name T55
Test name
Test status
Simulation time 86807825888 ps
CPU time 257.52 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:05:32 PM PDT 24
Peak memory 202192 kb
Host smart-5b5f3c2b-3a42-4eb9-87be-d711232093a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531322905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3531322905
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2384029431
Short name T749
Test name
Test status
Simulation time 41489474772 ps
CPU time 85.72 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:02:50 PM PDT 24
Peak memory 201732 kb
Host smart-e580e973-0691-4b87-b0a5-24d3b6136b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384029431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2384029431
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3094673839
Short name T83
Test name
Test status
Simulation time 3545791588 ps
CPU time 5.23 seconds
Started Jul 14 07:01:05 PM PDT 24
Finished Jul 14 07:01:13 PM PDT 24
Peak memory 201720 kb
Host smart-6fe10563-e7f9-4d37-bebc-a4ee954f170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094673839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3094673839
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2548474504
Short name T677
Test name
Test status
Simulation time 5857092951 ps
CPU time 12.47 seconds
Started Jul 14 07:01:29 PM PDT 24
Finished Jul 14 07:01:42 PM PDT 24
Peak memory 201584 kb
Host smart-717c4079-8f29-4fa9-8577-c2e819b89a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548474504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2548474504
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.447334775
Short name T431
Test name
Test status
Simulation time 7006522464 ps
CPU time 9.1 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:01:38 PM PDT 24
Peak memory 201616 kb
Host smart-41f29635-4d33-44df-b793-f15acab2fac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447334775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
447334775
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2780019524
Short name T387
Test name
Test status
Simulation time 407395138 ps
CPU time 1.57 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:01:19 PM PDT 24
Peak memory 201652 kb
Host smart-fde001f4-22a8-44c1-ab3b-94f72534e7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780019524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2780019524
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1294624769
Short name T177
Test name
Test status
Simulation time 324263913328 ps
CPU time 91.31 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:02:43 PM PDT 24
Peak memory 201776 kb
Host smart-52a7dbe8-b356-40d3-a746-663222495fe8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294624769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1294624769
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.791679063
Short name T235
Test name
Test status
Simulation time 167206745244 ps
CPU time 198.89 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:04:27 PM PDT 24
Peak memory 201916 kb
Host smart-5d39c89f-9650-4c79-b5b1-fa9b6b9eb67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791679063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.791679063
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1054783763
Short name T254
Test name
Test status
Simulation time 166927439977 ps
CPU time 104.23 seconds
Started Jul 14 07:01:21 PM PDT 24
Finished Jul 14 07:03:08 PM PDT 24
Peak memory 201884 kb
Host smart-88cf8e4a-7f9b-4dcd-8339-a6c771f64d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054783763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1054783763
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3337214354
Short name T241
Test name
Test status
Simulation time 334465216815 ps
CPU time 742.01 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 201932 kb
Host smart-1b9eb630-9fd3-4fbc-97e3-82aacf55cc51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337214354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3337214354
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3175480977
Short name T209
Test name
Test status
Simulation time 327426919187 ps
CPU time 655.27 seconds
Started Jul 14 07:01:17 PM PDT 24
Finished Jul 14 07:12:16 PM PDT 24
Peak memory 201784 kb
Host smart-7ab90d66-cb38-4ce9-b0d8-b3cb718cf2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175480977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3175480977
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3568369965
Short name T725
Test name
Test status
Simulation time 334369839249 ps
CPU time 775.37 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:14:10 PM PDT 24
Peak memory 201776 kb
Host smart-ede3fa17-8c36-47f2-a34e-9982d6d5bebb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568369965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3568369965
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.631845
Short name T260
Test name
Test status
Simulation time 194385185988 ps
CPU time 104.34 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:03:04 PM PDT 24
Peak memory 201756 kb
Host smart-929f1d24-f4cc-42d0-9769-4828373c36c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wa
keup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wak
eup.631845
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2737656943
Short name T610
Test name
Test status
Simulation time 196778444909 ps
CPU time 247.87 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:05:53 PM PDT 24
Peak memory 201864 kb
Host smart-8a12b1ef-3cd1-42dc-bfdb-2259aa52675c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737656943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2737656943
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2218263247
Short name T199
Test name
Test status
Simulation time 130498235699 ps
CPU time 483.45 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:09:16 PM PDT 24
Peak memory 202140 kb
Host smart-b2519125-42ea-46dc-bab3-b51dd787b3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218263247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2218263247
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.4068983726
Short name T386
Test name
Test status
Simulation time 37457390658 ps
CPU time 91.48 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:02:47 PM PDT 24
Peak memory 201688 kb
Host smart-9c279191-5542-45d8-86e6-a4fd06133e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068983726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.4068983726
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2933975202
Short name T526
Test name
Test status
Simulation time 4239895521 ps
CPU time 10.73 seconds
Started Jul 14 07:01:20 PM PDT 24
Finished Jul 14 07:01:34 PM PDT 24
Peak memory 201676 kb
Host smart-13ad8cd3-2c43-4c3d-95d3-8c160bc98b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933975202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2933975202
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3900903662
Short name T471
Test name
Test status
Simulation time 6028512736 ps
CPU time 8.3 seconds
Started Jul 14 07:01:10 PM PDT 24
Finished Jul 14 07:01:20 PM PDT 24
Peak memory 201716 kb
Host smart-a5683609-c5d5-4f7b-95d0-1cef6bc76e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900903662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3900903662
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3786444025
Short name T309
Test name
Test status
Simulation time 390494386943 ps
CPU time 553.56 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:10:36 PM PDT 24
Peak memory 201904 kb
Host smart-47054142-517e-494e-b8ac-0faf2f1b830d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786444025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3786444025
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1126655180
Short name T95
Test name
Test status
Simulation time 234278068240 ps
CPU time 640.08 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:12:01 PM PDT 24
Peak memory 210576 kb
Host smart-1917501b-a4ce-4092-bbbd-400207d7b429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126655180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1126655180
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2887287630
Short name T464
Test name
Test status
Simulation time 362597497 ps
CPU time 1.66 seconds
Started Jul 14 07:01:11 PM PDT 24
Finished Jul 14 07:01:14 PM PDT 24
Peak memory 201708 kb
Host smart-5ebec8f8-2845-4bf2-a67d-14cd47e0929f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887287630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2887287630
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2471478946
Short name T689
Test name
Test status
Simulation time 160640434848 ps
CPU time 260.21 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:05:36 PM PDT 24
Peak memory 201932 kb
Host smart-6679986c-9f9d-4c6e-814e-891f017ea25e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471478946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2471478946
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.11800060
Short name T639
Test name
Test status
Simulation time 535179682039 ps
CPU time 570.97 seconds
Started Jul 14 07:01:18 PM PDT 24
Finished Jul 14 07:10:53 PM PDT 24
Peak memory 201880 kb
Host smart-6f6d27a9-71b1-4c07-8618-11c6a37a8c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11800060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.11800060
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2183473228
Short name T469
Test name
Test status
Simulation time 162626351480 ps
CPU time 353.44 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:07:13 PM PDT 24
Peak memory 201824 kb
Host smart-75a1af8b-dfe6-4a30-8101-49cdd5344797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183473228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2183473228
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2176680800
Short name T216
Test name
Test status
Simulation time 494388500168 ps
CPU time 1176.06 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:21:01 PM PDT 24
Peak memory 202084 kb
Host smart-d3cc16da-ead6-4ebb-a6a4-1826247b1561
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176680800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2176680800
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3313714523
Short name T622
Test name
Test status
Simulation time 331890963432 ps
CPU time 201.67 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:04:41 PM PDT 24
Peak memory 201904 kb
Host smart-9924b7bb-78e8-49f0-a2a0-8d00378181a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313714523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3313714523
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4057926264
Short name T547
Test name
Test status
Simulation time 170738844028 ps
CPU time 226.49 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:05:13 PM PDT 24
Peak memory 201892 kb
Host smart-dd3264f5-cfb1-4390-907d-a3424e589300
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057926264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4057926264
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4207508160
Short name T723
Test name
Test status
Simulation time 616848731647 ps
CPU time 1135.43 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:20:16 PM PDT 24
Peak memory 201800 kb
Host smart-dddf77e6-f193-4aac-be58-eb104773ebe2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207508160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4207508160
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.393003177
Short name T175
Test name
Test status
Simulation time 621796145950 ps
CPU time 362.2 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 201884 kb
Host smart-229b6400-024c-4c6b-894c-079a614b8539
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393003177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.393003177
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2484822457
Short name T474
Test name
Test status
Simulation time 96431491769 ps
CPU time 513.58 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:09:51 PM PDT 24
Peak memory 202204 kb
Host smart-b9ac0e53-76db-4e1a-8a18-ff0fdc76b433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484822457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2484822457
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3343092997
Short name T660
Test name
Test status
Simulation time 33104478718 ps
CPU time 5.23 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:01:31 PM PDT 24
Peak memory 201568 kb
Host smart-104c79e3-e4f4-4cdd-931d-e587d5c92e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343092997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3343092997
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.373306505
Short name T710
Test name
Test status
Simulation time 5207657676 ps
CPU time 6.98 seconds
Started Jul 14 07:01:07 PM PDT 24
Finished Jul 14 07:01:15 PM PDT 24
Peak memory 201732 kb
Host smart-5ac771cd-f61d-4407-9907-35492c9d2887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373306505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.373306505
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3052947723
Short name T773
Test name
Test status
Simulation time 5812052355 ps
CPU time 14.09 seconds
Started Jul 14 07:01:17 PM PDT 24
Finished Jul 14 07:01:36 PM PDT 24
Peak memory 201680 kb
Host smart-6bd6bc14-bc43-456b-a93f-796a42db3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052947723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3052947723
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1589538373
Short name T37
Test name
Test status
Simulation time 168033307572 ps
CPU time 208.36 seconds
Started Jul 14 07:01:30 PM PDT 24
Finished Jul 14 07:04:59 PM PDT 24
Peak memory 201932 kb
Host smart-15722ebb-1307-47d3-8598-baa479598d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589538373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1589538373
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2542322194
Short name T777
Test name
Test status
Simulation time 18948568818 ps
CPU time 62.24 seconds
Started Jul 14 07:01:18 PM PDT 24
Finished Jul 14 07:02:24 PM PDT 24
Peak memory 210548 kb
Host smart-b3e94af4-fc7f-49ad-8163-05a269e51b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542322194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2542322194
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3926393123
Short name T4
Test name
Test status
Simulation time 375337052 ps
CPU time 1.04 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:01:26 PM PDT 24
Peak memory 201604 kb
Host smart-4f2f5921-0f33-4311-a2e2-c7d8a92233c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926393123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3926393123
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2919440575
Short name T107
Test name
Test status
Simulation time 362352628161 ps
CPU time 116.12 seconds
Started Jul 14 07:01:21 PM PDT 24
Finished Jul 14 07:03:19 PM PDT 24
Peak memory 201872 kb
Host smart-2b8b0f75-3ec1-40e7-bce6-ddbbfb9d9ef8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919440575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2919440575
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3366011566
Short name T581
Test name
Test status
Simulation time 199652734001 ps
CPU time 244.18 seconds
Started Jul 14 07:01:31 PM PDT 24
Finished Jul 14 07:05:36 PM PDT 24
Peak memory 201916 kb
Host smart-e0064987-343d-4a5b-9eb8-591f55ab8533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366011566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3366011566
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3241024095
Short name T722
Test name
Test status
Simulation time 328451467909 ps
CPU time 686.04 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:12:47 PM PDT 24
Peak memory 201904 kb
Host smart-a9a0151f-14d3-4993-85a4-44e7e317463e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241024095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3241024095
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3713731687
Short name T178
Test name
Test status
Simulation time 494465708626 ps
CPU time 273.89 seconds
Started Jul 14 07:01:22 PM PDT 24
Finished Jul 14 07:05:58 PM PDT 24
Peak memory 201920 kb
Host smart-7e9f675c-2f72-439b-972a-a118b4d03986
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713731687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3713731687
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.515093235
Short name T707
Test name
Test status
Simulation time 180165885195 ps
CPU time 418.18 seconds
Started Jul 14 07:01:13 PM PDT 24
Finished Jul 14 07:08:15 PM PDT 24
Peak memory 201976 kb
Host smart-faf84477-4998-4b15-b293-ab5d1623a768
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515093235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.515093235
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2716565275
Short name T99
Test name
Test status
Simulation time 608671042317 ps
CPU time 704.29 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:13:09 PM PDT 24
Peak memory 201876 kb
Host smart-73e8ed38-7c5c-4708-8be1-9eaca1808533
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716565275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2716565275
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3506494089
Short name T680
Test name
Test status
Simulation time 93782025272 ps
CPU time 332.45 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 202272 kb
Host smart-c69aa1ca-1e56-47fd-8052-f80effc41bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506494089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3506494089
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.343369309
Short name T7
Test name
Test status
Simulation time 24254744360 ps
CPU time 31.41 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:01:50 PM PDT 24
Peak memory 201708 kb
Host smart-a3e627f1-a3b1-49a2-9357-25b8ca861efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343369309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.343369309
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.389279840
Short name T425
Test name
Test status
Simulation time 3939371723 ps
CPU time 9.08 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:01:30 PM PDT 24
Peak memory 201732 kb
Host smart-8b6c19c4-2db3-466c-bb19-70970717d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389279840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.389279840
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3939898360
Short name T509
Test name
Test status
Simulation time 5699837081 ps
CPU time 4.62 seconds
Started Jul 14 07:01:30 PM PDT 24
Finished Jul 14 07:01:35 PM PDT 24
Peak memory 201700 kb
Host smart-6e28ebd8-b739-4456-9dc2-a7c8fb89aa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939898360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3939898360
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3294433114
Short name T282
Test name
Test status
Simulation time 328569923028 ps
CPU time 209.7 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:04:55 PM PDT 24
Peak memory 202100 kb
Host smart-415675ba-3665-46fe-8d21-20e492ed4a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294433114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3294433114
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.4088906342
Short name T752
Test name
Test status
Simulation time 212841834173 ps
CPU time 116.71 seconds
Started Jul 14 07:01:24 PM PDT 24
Finished Jul 14 07:03:22 PM PDT 24
Peak memory 210196 kb
Host smart-da444c79-c1b6-4acc-9c30-3bc9fd8a79e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088906342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.4088906342
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1515962207
Short name T618
Test name
Test status
Simulation time 491616866 ps
CPU time 0.89 seconds
Started Jul 14 07:01:30 PM PDT 24
Finished Jul 14 07:01:31 PM PDT 24
Peak memory 201604 kb
Host smart-b0915cd5-7bda-42be-8e37-a6fdb20d5869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515962207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1515962207
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3216120325
Short name T706
Test name
Test status
Simulation time 521246043481 ps
CPU time 399.72 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:08:15 PM PDT 24
Peak memory 201964 kb
Host smart-5daf07a9-9ad5-4450-bceb-1f4825fceb32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216120325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3216120325
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2141051696
Short name T672
Test name
Test status
Simulation time 159051798995 ps
CPU time 189.84 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:04:35 PM PDT 24
Peak memory 201916 kb
Host smart-8bfb57c1-5c9c-4e75-abd4-d03e313f8c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141051696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2141051696
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1678038989
Short name T491
Test name
Test status
Simulation time 490472871960 ps
CPU time 298.81 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:06:24 PM PDT 24
Peak memory 201884 kb
Host smart-7c8c0db3-20b3-42d5-8a5d-c1df27e8165a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678038989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1678038989
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1294778188
Short name T468
Test name
Test status
Simulation time 495631162681 ps
CPU time 95.64 seconds
Started Jul 14 07:01:21 PM PDT 24
Finished Jul 14 07:02:59 PM PDT 24
Peak memory 201900 kb
Host smart-b66f2d9d-081d-4e59-afdc-f8cab015e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294778188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1294778188
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1704347572
Short name T584
Test name
Test status
Simulation time 167030507112 ps
CPU time 171.82 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:04:28 PM PDT 24
Peak memory 201880 kb
Host smart-b8b9103c-59e9-44a4-ae78-d0dc73d6f255
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704347572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1704347572
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2788560739
Short name T553
Test name
Test status
Simulation time 409637702855 ps
CPU time 158.49 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:04:07 PM PDT 24
Peak memory 202092 kb
Host smart-25596cb1-9340-436d-b664-b7b9de5974d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788560739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2788560739
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2098857925
Short name T197
Test name
Test status
Simulation time 113617419636 ps
CPU time 328.23 seconds
Started Jul 14 07:01:22 PM PDT 24
Finished Jul 14 07:06:53 PM PDT 24
Peak memory 202156 kb
Host smart-571fb1d8-bd51-4192-9d27-350f5cc582e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098857925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2098857925
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1406022430
Short name T608
Test name
Test status
Simulation time 24872374770 ps
CPU time 14.29 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:01:41 PM PDT 24
Peak memory 201720 kb
Host smart-1bc90efa-a9e3-4751-9a7f-3b02fe1f7033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406022430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1406022430
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3399147246
Short name T495
Test name
Test status
Simulation time 4019014582 ps
CPU time 9.79 seconds
Started Jul 14 07:01:24 PM PDT 24
Finished Jul 14 07:01:35 PM PDT 24
Peak memory 201708 kb
Host smart-e7406c8e-27ac-460e-b39b-d122189a4fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399147246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3399147246
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2337019489
Short name T769
Test name
Test status
Simulation time 5713784497 ps
CPU time 1.65 seconds
Started Jul 14 07:01:18 PM PDT 24
Finished Jul 14 07:01:24 PM PDT 24
Peak memory 201716 kb
Host smart-b7d6999f-d304-43df-a5b4-d93f9205e79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337019489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2337019489
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2548032074
Short name T262
Test name
Test status
Simulation time 407342643436 ps
CPU time 460.09 seconds
Started Jul 14 07:01:22 PM PDT 24
Finished Jul 14 07:09:04 PM PDT 24
Peak memory 202284 kb
Host smart-b8f899f2-1b96-424c-8dde-25d76fa64491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548032074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2548032074
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4076287499
Short name T487
Test name
Test status
Simulation time 534131227 ps
CPU time 0.71 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:01:30 PM PDT 24
Peak memory 201636 kb
Host smart-25d27929-3669-4c15-8c24-5552edd0bf24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076287499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4076287499
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1783046001
Short name T598
Test name
Test status
Simulation time 158593518828 ps
CPU time 336.87 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:06:59 PM PDT 24
Peak memory 201908 kb
Host smart-40a1ab46-5066-4cc7-90d4-a2ed5fbf3413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783046001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1783046001
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4233254929
Short name T181
Test name
Test status
Simulation time 336516107890 ps
CPU time 133.93 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:03:39 PM PDT 24
Peak memory 201980 kb
Host smart-2dbbe524-71b8-4b20-8bdb-6a8fa8e32a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233254929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4233254929
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3514080072
Short name T629
Test name
Test status
Simulation time 494294864272 ps
CPU time 89.26 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:03:05 PM PDT 24
Peak memory 201808 kb
Host smart-496a1552-d1b7-4659-b0c3-038aac53818a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514080072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3514080072
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1524791949
Short name T191
Test name
Test status
Simulation time 324386589787 ps
CPU time 729.7 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:13:31 PM PDT 24
Peak memory 201904 kb
Host smart-aef73759-b246-4ed4-8e95-9e36d7ae235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524791949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1524791949
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.32884045
Short name T192
Test name
Test status
Simulation time 162780320240 ps
CPU time 92.38 seconds
Started Jul 14 07:01:24 PM PDT 24
Finished Jul 14 07:02:58 PM PDT 24
Peak memory 201904 kb
Host smart-75a83c7d-ba81-4fa2-bc5f-70276f175a9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=32884045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed
.32884045
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.518824011
Short name T628
Test name
Test status
Simulation time 603715940675 ps
CPU time 362.4 seconds
Started Jul 14 07:01:26 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 201844 kb
Host smart-166c8068-fa04-4a89-8b35-473f5b632e38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518824011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.518824011
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2029310810
Short name T417
Test name
Test status
Simulation time 116163731751 ps
CPU time 625.54 seconds
Started Jul 14 07:01:18 PM PDT 24
Finished Jul 14 07:11:48 PM PDT 24
Peak memory 202208 kb
Host smart-84d62967-9f7b-4963-9bcc-2b9f66762195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029310810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2029310810
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1307376289
Short name T798
Test name
Test status
Simulation time 24330396506 ps
CPU time 10.68 seconds
Started Jul 14 07:01:32 PM PDT 24
Finished Jul 14 07:01:44 PM PDT 24
Peak memory 201712 kb
Host smart-268b0ec0-bdb3-48d2-827c-c8f0c4baed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307376289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1307376289
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.578396831
Short name T559
Test name
Test status
Simulation time 3297116807 ps
CPU time 7.75 seconds
Started Jul 14 07:01:20 PM PDT 24
Finished Jul 14 07:01:31 PM PDT 24
Peak memory 201728 kb
Host smart-8b35efda-a5bd-4be4-a356-5de12ef0bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578396831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.578396831
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2790210259
Short name T545
Test name
Test status
Simulation time 5561693352 ps
CPU time 14.17 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:01:35 PM PDT 24
Peak memory 201696 kb
Host smart-9e3de429-7b99-4d8e-b6c4-d315c998bae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790210259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2790210259
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1663868110
Short name T86
Test name
Test status
Simulation time 37085960867 ps
CPU time 77.09 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:02:46 PM PDT 24
Peak memory 201388 kb
Host smart-a790fb9e-6d37-4c7f-91d9-7caa58602550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663868110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1663868110
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3427112188
Short name T323
Test name
Test status
Simulation time 274511401749 ps
CPU time 303.37 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:06:32 PM PDT 24
Peak memory 210556 kb
Host smart-c86e3bdd-d206-45df-b100-540c40148b45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427112188 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3427112188
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.249611278
Short name T508
Test name
Test status
Simulation time 446653681 ps
CPU time 0.85 seconds
Started Jul 14 07:00:43 PM PDT 24
Finished Jul 14 07:00:45 PM PDT 24
Peak memory 201644 kb
Host smart-20475b3c-de40-4809-a030-b885a5d28a34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249611278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.249611278
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2883894038
Short name T741
Test name
Test status
Simulation time 175097895520 ps
CPU time 391.82 seconds
Started Jul 14 07:00:37 PM PDT 24
Finished Jul 14 07:07:11 PM PDT 24
Peak memory 201916 kb
Host smart-960aa05a-d68d-4dc6-aad7-43ae75a1f145
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883894038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2883894038
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2745751051
Short name T592
Test name
Test status
Simulation time 328999235236 ps
CPU time 704.84 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:12:28 PM PDT 24
Peak memory 201900 kb
Host smart-11967fa2-017f-4bc6-8440-f578cdcfe46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745751051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2745751051
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1498665827
Short name T779
Test name
Test status
Simulation time 165996341453 ps
CPU time 49.65 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:01:51 PM PDT 24
Peak memory 201972 kb
Host smart-71a3af47-81a5-4c94-9caf-f90b5b9cbac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498665827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1498665827
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.315344888
Short name T557
Test name
Test status
Simulation time 160486440003 ps
CPU time 93.29 seconds
Started Jul 14 07:00:43 PM PDT 24
Finished Jul 14 07:02:17 PM PDT 24
Peak memory 201844 kb
Host smart-2a2dcd83-3a9b-460d-82f8-47eb1ca4eaac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=315344888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.315344888
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2325886802
Short name T236
Test name
Test status
Simulation time 162810917958 ps
CPU time 186.41 seconds
Started Jul 14 07:00:31 PM PDT 24
Finished Jul 14 07:03:41 PM PDT 24
Peak memory 201948 kb
Host smart-d2956130-e14c-4dae-b939-9ff515513890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325886802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2325886802
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1880215593
Short name T343
Test name
Test status
Simulation time 326548942061 ps
CPU time 93.7 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:02:22 PM PDT 24
Peak memory 201940 kb
Host smart-228b737c-7b50-4822-913e-724c2fed086b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880215593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1880215593
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.253945126
Short name T278
Test name
Test status
Simulation time 351529888061 ps
CPU time 217.84 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:04:30 PM PDT 24
Peak memory 201676 kb
Host smart-3333b054-b8a9-425c-9f50-d881d8499cb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253945126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.253945126
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.897666551
Short name T472
Test name
Test status
Simulation time 605661796578 ps
CPU time 701.85 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:12:30 PM PDT 24
Peak memory 201908 kb
Host smart-a42b7418-ded1-4e7e-8770-5c66f0a4e729
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897666551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.897666551
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1114660672
Short name T567
Test name
Test status
Simulation time 90674150587 ps
CPU time 338.29 seconds
Started Jul 14 07:00:38 PM PDT 24
Finished Jul 14 07:06:18 PM PDT 24
Peak memory 202184 kb
Host smart-7a5b6cda-3cde-450f-aa4a-37b31f9bb67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114660672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1114660672
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1279018466
Short name T687
Test name
Test status
Simulation time 38935942375 ps
CPU time 72.56 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:02:05 PM PDT 24
Peak memory 201788 kb
Host smart-0c1a38a4-f0ed-4d5f-ae91-68910b75435e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279018466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1279018466
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1461043215
Short name T554
Test name
Test status
Simulation time 4716765848 ps
CPU time 11.3 seconds
Started Jul 14 07:00:41 PM PDT 24
Finished Jul 14 07:00:53 PM PDT 24
Peak memory 201592 kb
Host smart-e7a0227f-6ecd-4e1c-b466-99193209be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461043215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1461043215
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2061736158
Short name T82
Test name
Test status
Simulation time 8365069816 ps
CPU time 19.32 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:01:09 PM PDT 24
Peak memory 218200 kb
Host smart-9444597a-fb38-4200-b282-69d451e61a05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061736158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2061736158
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1800721930
Short name T636
Test name
Test status
Simulation time 5832898702 ps
CPU time 12.7 seconds
Started Jul 14 07:00:24 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 201684 kb
Host smart-6608d9f8-751c-4ff6-9975-65a196dfc86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800721930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1800721930
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.4096485527
Short name T244
Test name
Test status
Simulation time 492479523445 ps
CPU time 1267.67 seconds
Started Jul 14 07:00:39 PM PDT 24
Finished Jul 14 07:21:49 PM PDT 24
Peak memory 210312 kb
Host smart-9b3bfb5f-8bbf-4d7d-897d-9785484c4603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096485527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
4096485527
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1906736845
Short name T649
Test name
Test status
Simulation time 21919874430 ps
CPU time 48.36 seconds
Started Jul 14 07:00:37 PM PDT 24
Finished Jul 14 07:01:27 PM PDT 24
Peak memory 202092 kb
Host smart-51dc7b24-cf7a-4233-8748-7cc1c7ee0095
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906736845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1906736845
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.98949123
Short name T339
Test name
Test status
Simulation time 507473756 ps
CPU time 1.05 seconds
Started Jul 14 07:01:31 PM PDT 24
Finished Jul 14 07:01:33 PM PDT 24
Peak memory 201564 kb
Host smart-1f50f130-77a6-46c3-abff-dd2eb46be384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98949123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.98949123
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4192240902
Short name T292
Test name
Test status
Simulation time 168162305026 ps
CPU time 97.06 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:03:13 PM PDT 24
Peak memory 202040 kb
Host smart-43d98772-ae57-45ab-b546-6ee4573a80f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192240902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4192240902
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.126567690
Short name T525
Test name
Test status
Simulation time 164663060897 ps
CPU time 97.15 seconds
Started Jul 14 07:01:23 PM PDT 24
Finished Jul 14 07:03:02 PM PDT 24
Peak memory 201840 kb
Host smart-0d8a3ddc-8e66-4ac6-a174-8fde636b2f7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=126567690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.126567690
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.775442438
Short name T194
Test name
Test status
Simulation time 497589163208 ps
CPU time 285.66 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:06:14 PM PDT 24
Peak memory 201964 kb
Host smart-178d03c3-a0fc-4ae4-b442-b95a6dd641cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775442438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.775442438
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3083215822
Short name T712
Test name
Test status
Simulation time 165015223445 ps
CPU time 104.69 seconds
Started Jul 14 07:01:14 PM PDT 24
Finished Jul 14 07:03:03 PM PDT 24
Peak memory 201908 kb
Host smart-7fd78f28-4dc1-4443-b979-69d2327f2668
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083215822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3083215822
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3173567467
Short name T294
Test name
Test status
Simulation time 524459256872 ps
CPU time 250.38 seconds
Started Jul 14 07:01:16 PM PDT 24
Finished Jul 14 07:05:31 PM PDT 24
Peak memory 201912 kb
Host smart-6081b84f-8731-464b-8b34-57b489bf5747
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173567467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3173567467
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2765126073
Short name T709
Test name
Test status
Simulation time 608208574114 ps
CPU time 190.2 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:04:38 PM PDT 24
Peak memory 201868 kb
Host smart-fb8668b5-d62e-440f-adca-e1c4047c051a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765126073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2765126073
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1182264786
Short name T514
Test name
Test status
Simulation time 27938757788 ps
CPU time 17.69 seconds
Started Jul 14 07:01:26 PM PDT 24
Finished Jul 14 07:01:45 PM PDT 24
Peak memory 201732 kb
Host smart-ead15acf-a566-4790-8ae1-0c80caec5ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182264786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1182264786
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.250440583
Short name T367
Test name
Test status
Simulation time 4392323148 ps
CPU time 3.44 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:01:23 PM PDT 24
Peak memory 201684 kb
Host smart-b2c7e810-1d64-4176-9922-559dd645c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250440583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.250440583
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.925164723
Short name T349
Test name
Test status
Simulation time 5606006849 ps
CPU time 14.49 seconds
Started Jul 14 07:01:15 PM PDT 24
Finished Jul 14 07:01:34 PM PDT 24
Peak memory 201632 kb
Host smart-a86bb9f4-b0bd-4580-983a-e71173a7f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925164723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.925164723
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2293879415
Short name T288
Test name
Test status
Simulation time 519908126800 ps
CPU time 265.06 seconds
Started Jul 14 07:01:17 PM PDT 24
Finished Jul 14 07:05:46 PM PDT 24
Peak memory 201948 kb
Host smart-c8530ef3-b383-47f8-a171-722f76804f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293879415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2293879415
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1488411765
Short name T112
Test name
Test status
Simulation time 41390675292 ps
CPU time 126.1 seconds
Started Jul 14 07:01:24 PM PDT 24
Finished Jul 14 07:03:32 PM PDT 24
Peak memory 210536 kb
Host smart-e7f45ed8-9522-4cc7-b74a-f61ffe31f08e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488411765 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1488411765
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2598490116
Short name T398
Test name
Test status
Simulation time 501890085 ps
CPU time 1.71 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:01:24 PM PDT 24
Peak memory 201628 kb
Host smart-27e02cd4-b9d3-475f-a092-217cf8ca5fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598490116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2598490116
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2588791190
Short name T195
Test name
Test status
Simulation time 532093477623 ps
CPU time 297.2 seconds
Started Jul 14 07:01:40 PM PDT 24
Finished Jul 14 07:06:38 PM PDT 24
Peak memory 201904 kb
Host smart-c4ea0cde-b90e-456e-ae72-4acb761371c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588791190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2588791190
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.171902872
Short name T246
Test name
Test status
Simulation time 167633230108 ps
CPU time 344.45 seconds
Started Jul 14 07:01:36 PM PDT 24
Finished Jul 14 07:07:22 PM PDT 24
Peak memory 201892 kb
Host smart-ec7176ae-2ae3-4d44-bb21-0aa4f85cfbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171902872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.171902872
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.665179541
Short name T493
Test name
Test status
Simulation time 164843493793 ps
CPU time 369.55 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 201904 kb
Host smart-9b1ae410-a2c0-43ae-904f-f2b4dd27ed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665179541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.665179541
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3673265875
Short name T633
Test name
Test status
Simulation time 162496325790 ps
CPU time 29.57 seconds
Started Jul 14 07:01:26 PM PDT 24
Finished Jul 14 07:01:57 PM PDT 24
Peak memory 201816 kb
Host smart-a8a4b921-4cd6-4133-be59-25dafe69d3c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673265875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3673265875
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2295987918
Short name T507
Test name
Test status
Simulation time 160470073869 ps
CPU time 106.11 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:03:15 PM PDT 24
Peak memory 201644 kb
Host smart-b9aac0d8-9432-4081-bdf8-788a345d7ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295987918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2295987918
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2995394609
Short name T638
Test name
Test status
Simulation time 485036477187 ps
CPU time 312.59 seconds
Started Jul 14 07:01:38 PM PDT 24
Finished Jul 14 07:06:51 PM PDT 24
Peak memory 201900 kb
Host smart-e70c0245-e345-456b-9d12-a0f14386d2a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995394609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2995394609
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1234504433
Short name T399
Test name
Test status
Simulation time 183529252986 ps
CPU time 414.5 seconds
Started Jul 14 07:01:31 PM PDT 24
Finished Jul 14 07:08:26 PM PDT 24
Peak memory 201920 kb
Host smart-0683e252-2d9e-431f-83dd-e2afe7917b58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234504433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1234504433
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1295980050
Short name T340
Test name
Test status
Simulation time 595705966061 ps
CPU time 1182.63 seconds
Started Jul 14 07:01:36 PM PDT 24
Finished Jul 14 07:21:19 PM PDT 24
Peak memory 201872 kb
Host smart-e7427809-6149-437c-9861-12959b05b73c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295980050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1295980050
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.122974203
Short name T647
Test name
Test status
Simulation time 82030361969 ps
CPU time 458.15 seconds
Started Jul 14 07:01:26 PM PDT 24
Finished Jul 14 07:09:05 PM PDT 24
Peak memory 202200 kb
Host smart-f2e9769b-bf30-48db-8672-8e8921cc046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122974203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.122974203
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3952375147
Short name T458
Test name
Test status
Simulation time 27538695847 ps
CPU time 16.42 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:01:45 PM PDT 24
Peak memory 201688 kb
Host smart-695183a1-d5a6-4be7-b4c2-ab140f906c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952375147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3952375147
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3621172981
Short name T675
Test name
Test status
Simulation time 3641207055 ps
CPU time 8.58 seconds
Started Jul 14 07:01:20 PM PDT 24
Finished Jul 14 07:01:31 PM PDT 24
Peak memory 201676 kb
Host smart-c55f9fe6-7cd4-427a-adcd-5ee8fbf8b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621172981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3621172981
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1831846756
Short name T684
Test name
Test status
Simulation time 5882141897 ps
CPU time 3.85 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:01:32 PM PDT 24
Peak memory 201716 kb
Host smart-57a9bb59-555f-4c62-94ba-17b5ccc078e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831846756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1831846756
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3632508010
Short name T38
Test name
Test status
Simulation time 691616646839 ps
CPU time 444.19 seconds
Started Jul 14 07:01:31 PM PDT 24
Finished Jul 14 07:08:56 PM PDT 24
Peak memory 201840 kb
Host smart-510d26e8-829a-4d94-ad19-5b6ab5b0217d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632508010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3632508010
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.281953230
Short name T736
Test name
Test status
Simulation time 138676346414 ps
CPU time 138.53 seconds
Started Jul 14 07:01:34 PM PDT 24
Finished Jul 14 07:03:53 PM PDT 24
Peak memory 210224 kb
Host smart-5938c0e5-e934-4281-ac6c-93a2547c48ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281953230 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.281953230
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1180921268
Short name T528
Test name
Test status
Simulation time 525294820 ps
CPU time 1.8 seconds
Started Jul 14 07:01:33 PM PDT 24
Finished Jul 14 07:01:36 PM PDT 24
Peak memory 201672 kb
Host smart-00b75505-bcba-4a93-8cdc-31fa6b3198b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180921268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1180921268
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.64819508
Short name T670
Test name
Test status
Simulation time 494823831153 ps
CPU time 180.32 seconds
Started Jul 14 07:01:25 PM PDT 24
Finished Jul 14 07:04:27 PM PDT 24
Peak memory 201896 kb
Host smart-595ec889-0d9b-4afa-9540-ab0f6ade0faf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64819508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gatin
g.64819508
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.248222418
Short name T326
Test name
Test status
Simulation time 182136424844 ps
CPU time 53.87 seconds
Started Jul 14 07:01:39 PM PDT 24
Finished Jul 14 07:02:33 PM PDT 24
Peak memory 201928 kb
Host smart-7bcf7056-7550-4823-aaa9-d1b2db47af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248222418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.248222418
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.470164795
Short name T245
Test name
Test status
Simulation time 493114950411 ps
CPU time 1141.35 seconds
Started Jul 14 07:01:32 PM PDT 24
Finished Jul 14 07:20:34 PM PDT 24
Peak memory 201992 kb
Host smart-af6ae3f0-51d8-43b1-a5ea-232292d75478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470164795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.470164795
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4241205631
Short name T588
Test name
Test status
Simulation time 487868121537 ps
CPU time 278.52 seconds
Started Jul 14 07:01:28 PM PDT 24
Finished Jul 14 07:06:08 PM PDT 24
Peak memory 201784 kb
Host smart-0c7befdf-babc-40ec-81d8-2adb94c5027c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241205631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4241205631
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2456952597
Short name T189
Test name
Test status
Simulation time 494120773589 ps
CPU time 227.69 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:05:16 PM PDT 24
Peak memory 202096 kb
Host smart-781dd1c0-d383-4b28-87ae-0e44c18c75c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456952597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2456952597
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3459385805
Short name T697
Test name
Test status
Simulation time 161255401433 ps
CPU time 368.55 seconds
Started Jul 14 07:01:29 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 201880 kb
Host smart-250d35a6-3c10-4b03-b4bb-e2bdacc2ce0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459385805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3459385805
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.288000677
Short name T247
Test name
Test status
Simulation time 352777175403 ps
CPU time 783.29 seconds
Started Jul 14 07:01:30 PM PDT 24
Finished Jul 14 07:14:34 PM PDT 24
Peak memory 201980 kb
Host smart-5b24b981-aabc-40bd-b99a-1feacd5f3f62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288000677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.288000677
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3524435011
Short name T15
Test name
Test status
Simulation time 204026476664 ps
CPU time 84.26 seconds
Started Jul 14 07:01:27 PM PDT 24
Finished Jul 14 07:02:52 PM PDT 24
Peak memory 201856 kb
Host smart-fe19cdaa-653e-4929-9c05-e9d9408ff799
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524435011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3524435011
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3630040726
Short name T200
Test name
Test status
Simulation time 99294578108 ps
CPU time 291.4 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:06:29 PM PDT 24
Peak memory 202232 kb
Host smart-88ae1ba2-02c7-4ef2-b227-5f3bdd6982c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630040726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3630040726
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.339348602
Short name T656
Test name
Test status
Simulation time 33545903735 ps
CPU time 6.41 seconds
Started Jul 14 07:01:41 PM PDT 24
Finished Jul 14 07:01:48 PM PDT 24
Peak memory 201708 kb
Host smart-f61294b0-2ed6-443d-bd25-96fb76229c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339348602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.339348602
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.409674209
Short name T384
Test name
Test status
Simulation time 3761218893 ps
CPU time 2.65 seconds
Started Jul 14 07:01:39 PM PDT 24
Finished Jul 14 07:01:43 PM PDT 24
Peak memory 201712 kb
Host smart-2403e917-b96f-46eb-a8ab-a7d6082c2705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409674209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.409674209
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1874861414
Short name T481
Test name
Test status
Simulation time 6081381762 ps
CPU time 4.63 seconds
Started Jul 14 07:01:19 PM PDT 24
Finished Jul 14 07:01:27 PM PDT 24
Peak memory 201708 kb
Host smart-3dd9ff08-b4ac-4a83-bcbd-1be7f0b132fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874861414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1874861414
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3801258107
Short name T32
Test name
Test status
Simulation time 175128935802 ps
CPU time 364.69 seconds
Started Jul 14 07:01:34 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 201912 kb
Host smart-06492b0f-4e9d-4f6f-9ee7-9a1cf7e282e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801258107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3801258107
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.579041819
Short name T109
Test name
Test status
Simulation time 418754693 ps
CPU time 0.84 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:01:37 PM PDT 24
Peak memory 201660 kb
Host smart-4c616c46-2beb-45cd-b013-33c15142b8ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579041819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.579041819
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.410996013
Short name T220
Test name
Test status
Simulation time 341616382635 ps
CPU time 836.19 seconds
Started Jul 14 07:01:41 PM PDT 24
Finished Jul 14 07:15:38 PM PDT 24
Peak memory 201944 kb
Host smart-305d167e-5942-4ebd-ad59-4f2e2830719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410996013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.410996013
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.412188565
Short name T599
Test name
Test status
Simulation time 325903128281 ps
CPU time 69 seconds
Started Jul 14 07:01:39 PM PDT 24
Finished Jul 14 07:02:48 PM PDT 24
Peak memory 201932 kb
Host smart-3ea12b1d-0994-45c9-ba44-7d40f1b406de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412188565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.412188565
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1147893327
Short name T383
Test name
Test status
Simulation time 158332980141 ps
CPU time 90.19 seconds
Started Jul 14 07:01:32 PM PDT 24
Finished Jul 14 07:03:03 PM PDT 24
Peak memory 201868 kb
Host smart-9f6b9cfd-2c54-4b29-82e0-6a8b8e1513f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147893327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1147893327
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2022362052
Short name T252
Test name
Test status
Simulation time 504348875959 ps
CPU time 602.89 seconds
Started Jul 14 07:01:32 PM PDT 24
Finished Jul 14 07:11:36 PM PDT 24
Peak memory 201940 kb
Host smart-cdaf8751-9fc3-4021-b943-ff302a1453f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022362052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2022362052
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.512707619
Short name T347
Test name
Test status
Simulation time 164038289881 ps
CPU time 231.22 seconds
Started Jul 14 07:01:32 PM PDT 24
Finished Jul 14 07:05:24 PM PDT 24
Peak memory 201804 kb
Host smart-c8d593fc-9616-49fb-abb6-4b8337f6241d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=512707619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.512707619
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1236732636
Short name T101
Test name
Test status
Simulation time 202405344148 ps
CPU time 474.6 seconds
Started Jul 14 07:01:44 PM PDT 24
Finished Jul 14 07:09:40 PM PDT 24
Peak memory 201896 kb
Host smart-14ba19ac-12e9-4adf-9c86-17052594caed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236732636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1236732636
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3084707626
Short name T5
Test name
Test status
Simulation time 611071535702 ps
CPU time 1407.68 seconds
Started Jul 14 07:01:34 PM PDT 24
Finished Jul 14 07:25:03 PM PDT 24
Peak memory 201888 kb
Host smart-0e30f5a9-fbd2-446c-8b73-dc1c4deaf0b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084707626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3084707626
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4008980885
Short name T788
Test name
Test status
Simulation time 129073061328 ps
CPU time 391.07 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:08:09 PM PDT 24
Peak memory 202180 kb
Host smart-85774a1c-c508-40c6-8a57-dee1ba295f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008980885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4008980885
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.656308997
Short name T730
Test name
Test status
Simulation time 44796007886 ps
CPU time 10.47 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:01:47 PM PDT 24
Peak memory 201728 kb
Host smart-fd9e818d-8523-4506-8809-a9f46efa79a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656308997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.656308997
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.491114910
Short name T585
Test name
Test status
Simulation time 4081175343 ps
CPU time 1.6 seconds
Started Jul 14 07:01:39 PM PDT 24
Finished Jul 14 07:01:41 PM PDT 24
Peak memory 201712 kb
Host smart-ff4305f0-5d46-462e-89b0-3fde9f2dc7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491114910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.491114910
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.863354540
Short name T436
Test name
Test status
Simulation time 5513803896 ps
CPU time 3.86 seconds
Started Jul 14 07:01:31 PM PDT 24
Finished Jul 14 07:01:36 PM PDT 24
Peak memory 201736 kb
Host smart-7398b89a-0b65-439e-aba7-fcbbf300d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863354540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.863354540
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2941354085
Short name T751
Test name
Test status
Simulation time 262222338720 ps
CPU time 863.92 seconds
Started Jul 14 07:01:38 PM PDT 24
Finished Jul 14 07:16:03 PM PDT 24
Peak memory 218480 kb
Host smart-df446ef7-03f1-43bb-9aee-1bd02e907689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941354085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2941354085
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.622445202
Short name T268
Test name
Test status
Simulation time 163679256789 ps
CPU time 154.24 seconds
Started Jul 14 07:01:38 PM PDT 24
Finished Jul 14 07:04:13 PM PDT 24
Peak memory 210500 kb
Host smart-22ed012d-fe32-4dfa-9703-0d115bf730bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622445202 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.622445202
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.920368321
Short name T549
Test name
Test status
Simulation time 334112548 ps
CPU time 0.87 seconds
Started Jul 14 07:01:40 PM PDT 24
Finished Jul 14 07:01:41 PM PDT 24
Peak memory 201708 kb
Host smart-becd4887-af30-421c-b5f3-3ebb6f0a0175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920368321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.920368321
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2388354972
Short name T765
Test name
Test status
Simulation time 163285871028 ps
CPU time 370.45 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:07:56 PM PDT 24
Peak memory 201896 kb
Host smart-bfa4506a-679a-48f9-98f7-9400da535a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388354972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2388354972
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3404555716
Short name T237
Test name
Test status
Simulation time 163205589511 ps
CPU time 338.23 seconds
Started Jul 14 07:01:42 PM PDT 24
Finished Jul 14 07:07:21 PM PDT 24
Peak memory 201896 kb
Host smart-c0a070b9-69cb-455f-9320-827a7d437c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404555716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3404555716
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1223332012
Short name T122
Test name
Test status
Simulation time 490815016548 ps
CPU time 195.98 seconds
Started Jul 14 07:01:41 PM PDT 24
Finished Jul 14 07:04:58 PM PDT 24
Peak memory 201880 kb
Host smart-65805b27-e535-4628-9dfc-8a1975d4fa7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223332012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1223332012
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3838477744
Short name T322
Test name
Test status
Simulation time 328594141520 ps
CPU time 792.53 seconds
Started Jul 14 07:01:41 PM PDT 24
Finished Jul 14 07:14:54 PM PDT 24
Peak memory 201960 kb
Host smart-50f7daf5-0f3e-4ab6-83e7-de3bb05d0ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838477744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3838477744
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2046887307
Short name T644
Test name
Test status
Simulation time 326493500129 ps
CPU time 684.64 seconds
Started Jul 14 07:01:31 PM PDT 24
Finished Jul 14 07:12:57 PM PDT 24
Peak memory 201876 kb
Host smart-748f411a-f254-4e74-ac84-d32af19d3158
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046887307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2046887307
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3312804026
Short name T233
Test name
Test status
Simulation time 190258879828 ps
CPU time 226.33 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:05:24 PM PDT 24
Peak memory 201904 kb
Host smart-a3165b72-a826-47ce-b2e1-59b2c4e6ee3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312804026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3312804026
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1713662699
Short name T569
Test name
Test status
Simulation time 388944624927 ps
CPU time 245.93 seconds
Started Jul 14 07:01:42 PM PDT 24
Finished Jul 14 07:05:48 PM PDT 24
Peak memory 201876 kb
Host smart-ed918401-6ed6-4693-afbf-044b174102d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713662699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1713662699
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.931507689
Short name T692
Test name
Test status
Simulation time 105097063418 ps
CPU time 400.77 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:08:26 PM PDT 24
Peak memory 202156 kb
Host smart-00235655-e5b1-420e-9b18-0b261f333d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931507689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.931507689
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2893025465
Short name T359
Test name
Test status
Simulation time 32043775826 ps
CPU time 73.6 seconds
Started Jul 14 07:01:32 PM PDT 24
Finished Jul 14 07:02:47 PM PDT 24
Peak memory 201712 kb
Host smart-40d4e70d-2e99-4665-9571-e17d112b35f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893025465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2893025465
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.472471904
Short name T540
Test name
Test status
Simulation time 4732265836 ps
CPU time 2.94 seconds
Started Jul 14 07:01:38 PM PDT 24
Finished Jul 14 07:01:42 PM PDT 24
Peak memory 201724 kb
Host smart-ca009543-fc67-4d3b-bac7-3c293bf930ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472471904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.472471904
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.389885642
Short name T43
Test name
Test status
Simulation time 5796257049 ps
CPU time 4.2 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:01:42 PM PDT 24
Peak memory 201708 kb
Host smart-22c8abd8-4c61-4dc9-b2ec-8686735775a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389885642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.389885642
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.828306673
Short name T686
Test name
Test status
Simulation time 370245020 ps
CPU time 0.82 seconds
Started Jul 14 07:01:38 PM PDT 24
Finished Jul 14 07:01:40 PM PDT 24
Peak memory 201600 kb
Host smart-7c86288a-520a-453f-888f-5bcd73bbbca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828306673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.828306673
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1555677439
Short name T512
Test name
Test status
Simulation time 325888355578 ps
CPU time 190.47 seconds
Started Jul 14 07:01:48 PM PDT 24
Finished Jul 14 07:04:59 PM PDT 24
Peak memory 201876 kb
Host smart-2e1d63e7-89c3-4d80-84e5-1bad8d85ef6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555677439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1555677439
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.351995050
Short name T533
Test name
Test status
Simulation time 167633699287 ps
CPU time 93.64 seconds
Started Jul 14 07:01:35 PM PDT 24
Finished Jul 14 07:03:10 PM PDT 24
Peak memory 201912 kb
Host smart-78c30ecd-3fae-4d40-ae86-3096a4d13b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351995050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.351995050
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1016200447
Short name T578
Test name
Test status
Simulation time 328032267646 ps
CPU time 183.53 seconds
Started Jul 14 07:01:48 PM PDT 24
Finished Jul 14 07:04:52 PM PDT 24
Peak memory 201892 kb
Host smart-38986c29-4a89-43b6-b255-6c3aa90ae6ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016200447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1016200447
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.982721095
Short name T44
Test name
Test status
Simulation time 325354292946 ps
CPU time 172.18 seconds
Started Jul 14 07:01:46 PM PDT 24
Finished Jul 14 07:04:39 PM PDT 24
Peak memory 201892 kb
Host smart-2f5cc37c-3ac5-4ed5-b2ce-c5896f531949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982721095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.982721095
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.160831065
Short name T746
Test name
Test status
Simulation time 330197083878 ps
CPU time 765.19 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:14:23 PM PDT 24
Peak memory 201960 kb
Host smart-c7578b97-442e-448e-88ab-ba9189c15668
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=160831065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.160831065
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3859546864
Short name T701
Test name
Test status
Simulation time 362001244222 ps
CPU time 127.73 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:03:46 PM PDT 24
Peak memory 201892 kb
Host smart-b1348df9-6641-40aa-a3e3-4c61ad8c279e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859546864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3859546864
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3657652441
Short name T412
Test name
Test status
Simulation time 392727302932 ps
CPU time 457.2 seconds
Started Jul 14 07:01:39 PM PDT 24
Finished Jul 14 07:09:17 PM PDT 24
Peak memory 201912 kb
Host smart-5ed54e9f-e0e0-4768-a4b6-116cb74ebf56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657652441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3657652441
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2812810674
Short name T755
Test name
Test status
Simulation time 73423180131 ps
CPU time 319.64 seconds
Started Jul 14 07:01:37 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 202132 kb
Host smart-6d9a4ce8-74fb-411a-83d7-3e7206130f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812810674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2812810674
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.4159251461
Short name T582
Test name
Test status
Simulation time 32836291368 ps
CPU time 70.6 seconds
Started Jul 14 07:01:43 PM PDT 24
Finished Jul 14 07:02:54 PM PDT 24
Peak memory 201728 kb
Host smart-f75666c1-943f-4053-8b2f-36863b6e729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159251461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4159251461
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1170801227
Short name T393
Test name
Test status
Simulation time 4517003472 ps
CPU time 11.61 seconds
Started Jul 14 07:01:38 PM PDT 24
Finished Jul 14 07:01:51 PM PDT 24
Peak memory 201684 kb
Host smart-67d5fa71-b37a-45af-b98a-da990208e274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170801227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1170801227
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1384246496
Short name T623
Test name
Test status
Simulation time 5598164220 ps
CPU time 2.09 seconds
Started Jul 14 07:01:44 PM PDT 24
Finished Jul 14 07:01:47 PM PDT 24
Peak memory 201716 kb
Host smart-30d0bcef-c614-4031-b7dc-16f905b98b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384246496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1384246496
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.621598864
Short name T668
Test name
Test status
Simulation time 5287941144 ps
CPU time 11.64 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:01:58 PM PDT 24
Peak memory 201684 kb
Host smart-5367d113-5a6b-4438-b38f-ddbdcc59cffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621598864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
621598864
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.493333635
Short name T26
Test name
Test status
Simulation time 138882910074 ps
CPU time 319.77 seconds
Started Jul 14 07:01:48 PM PDT 24
Finished Jul 14 07:07:09 PM PDT 24
Peak memory 217892 kb
Host smart-cfc9e7e9-9993-4d52-8961-6105919e594b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493333635 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.493333635
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2652723653
Short name T457
Test name
Test status
Simulation time 407576954 ps
CPU time 0.88 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:01:46 PM PDT 24
Peak memory 201548 kb
Host smart-fa4a99ea-504f-4ca4-b74d-4ee632fd0da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652723653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2652723653
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1657395358
Short name T257
Test name
Test status
Simulation time 176161211974 ps
CPU time 2.23 seconds
Started Jul 14 07:01:42 PM PDT 24
Finished Jul 14 07:01:45 PM PDT 24
Peak memory 201880 kb
Host smart-811ed7d3-d42b-4200-ba51-88cca95b7e6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657395358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1657395358
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.425239923
Short name T319
Test name
Test status
Simulation time 163626543722 ps
CPU time 95.81 seconds
Started Jul 14 07:01:42 PM PDT 24
Finished Jul 14 07:03:18 PM PDT 24
Peak memory 201896 kb
Host smart-8baf427e-73c3-4a2b-8cd9-9e81cbbc15a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425239923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.425239923
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.861250235
Short name T193
Test name
Test status
Simulation time 330564222216 ps
CPU time 292.98 seconds
Started Jul 14 07:01:43 PM PDT 24
Finished Jul 14 07:06:36 PM PDT 24
Peak memory 201876 kb
Host smart-7cb7f0d6-195e-40f1-8bb9-7c857dcf24ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861250235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.861250235
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2607037959
Short name T750
Test name
Test status
Simulation time 485343644445 ps
CPU time 803.51 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:15:12 PM PDT 24
Peak memory 201876 kb
Host smart-88669918-b19e-421f-b144-7acbbb25c933
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607037959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2607037959
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1652497938
Short name T796
Test name
Test status
Simulation time 162264645630 ps
CPU time 178.06 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:04:46 PM PDT 24
Peak memory 201896 kb
Host smart-4f6fe241-3910-4bbc-8f28-97307b4bb19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652497938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1652497938
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1407742694
Short name T401
Test name
Test status
Simulation time 490787793989 ps
CPU time 510.13 seconds
Started Jul 14 07:01:44 PM PDT 24
Finished Jul 14 07:10:15 PM PDT 24
Peak memory 201876 kb
Host smart-2204cf8a-1fb4-4473-ba42-e27b8f838529
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407742694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1407742694
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2591524150
Short name T612
Test name
Test status
Simulation time 184503700008 ps
CPU time 399.31 seconds
Started Jul 14 07:01:43 PM PDT 24
Finished Jul 14 07:08:23 PM PDT 24
Peak memory 201928 kb
Host smart-d1637f24-d250-48cf-a3e7-049d45ed24d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591524150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2591524150
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2445652866
Short name T27
Test name
Test status
Simulation time 598644465893 ps
CPU time 667.81 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:12:53 PM PDT 24
Peak memory 201788 kb
Host smart-11666958-b4e5-42ba-92d1-9768199d1bec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445652866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2445652866
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2047969299
Short name T475
Test name
Test status
Simulation time 113586475816 ps
CPU time 368.07 seconds
Started Jul 14 07:01:51 PM PDT 24
Finished Jul 14 07:08:00 PM PDT 24
Peak memory 202212 kb
Host smart-07e03c0e-dcc5-4dd2-a7f5-9c6aa418297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047969299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2047969299
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3673420381
Short name T430
Test name
Test status
Simulation time 27103293240 ps
CPU time 21.04 seconds
Started Jul 14 07:01:43 PM PDT 24
Finished Jul 14 07:02:05 PM PDT 24
Peak memory 201708 kb
Host smart-fc6ee3c8-02ed-4967-95c9-ea6e889e37cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673420381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3673420381
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1355065721
Short name T763
Test name
Test status
Simulation time 3067542866 ps
CPU time 7.84 seconds
Started Jul 14 07:01:44 PM PDT 24
Finished Jul 14 07:01:52 PM PDT 24
Peak memory 201708 kb
Host smart-0c16a847-b16b-41d3-8b5c-4f1c5e8354a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355065721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1355065721
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3957178791
Short name T702
Test name
Test status
Simulation time 5843598845 ps
CPU time 1.73 seconds
Started Jul 14 07:01:42 PM PDT 24
Finished Jul 14 07:01:45 PM PDT 24
Peak memory 201608 kb
Host smart-3b2c977b-b637-4ceb-9d9f-582e4ae1fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957178791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3957178791
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3143861183
Short name T230
Test name
Test status
Simulation time 367275085138 ps
CPU time 196.66 seconds
Started Jul 14 07:01:53 PM PDT 24
Finished Jul 14 07:05:10 PM PDT 24
Peak memory 201900 kb
Host smart-570b9208-e5ea-45d1-a6df-e480a3daaf06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143861183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3143861183
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3951598234
Short name T47
Test name
Test status
Simulation time 169866228660 ps
CPU time 81.07 seconds
Started Jul 14 07:01:42 PM PDT 24
Finished Jul 14 07:03:04 PM PDT 24
Peak memory 210540 kb
Host smart-f5f682d3-2249-4695-8501-e17133bba93e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951598234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3951598234
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4208579846
Short name T391
Test name
Test status
Simulation time 415535120 ps
CPU time 1.54 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:01:49 PM PDT 24
Peak memory 201664 kb
Host smart-75b64303-d7ca-4ca6-ad81-2da837ab550a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208579846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4208579846
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2029844361
Short name T208
Test name
Test status
Simulation time 356398197269 ps
CPU time 754.29 seconds
Started Jul 14 07:01:48 PM PDT 24
Finished Jul 14 07:14:23 PM PDT 24
Peak memory 201912 kb
Host smart-45021527-bd26-4cad-b021-45a8a5b57896
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029844361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2029844361
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1659450824
Short name T453
Test name
Test status
Simulation time 167214958410 ps
CPU time 152.51 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:04:21 PM PDT 24
Peak memory 201800 kb
Host smart-53dd004a-03d5-42dd-842d-f6ca4fe93790
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659450824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1659450824
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2796997999
Short name T566
Test name
Test status
Simulation time 331999569902 ps
CPU time 762.66 seconds
Started Jul 14 07:01:44 PM PDT 24
Finished Jul 14 07:14:28 PM PDT 24
Peak memory 201900 kb
Host smart-2ea46ee1-708b-401f-9823-c8bea15569b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796997999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2796997999
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3632065415
Short name T718
Test name
Test status
Simulation time 485019460883 ps
CPU time 144.02 seconds
Started Jul 14 07:01:50 PM PDT 24
Finished Jul 14 07:04:15 PM PDT 24
Peak memory 201920 kb
Host smart-da77fbb0-14d8-4860-b32f-0eed0fe83caf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632065415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3632065415
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1894634776
Short name T754
Test name
Test status
Simulation time 208334259738 ps
CPU time 90.83 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:03:19 PM PDT 24
Peak memory 201884 kb
Host smart-ff65d532-1d09-46e2-afa8-cfa5a27949fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894634776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1894634776
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2406615979
Short name T56
Test name
Test status
Simulation time 102561739513 ps
CPU time 327.36 seconds
Started Jul 14 07:01:46 PM PDT 24
Finished Jul 14 07:07:14 PM PDT 24
Peak memory 202204 kb
Host smart-08cc2c59-aa5d-47f2-b981-399870fbfc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406615979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2406615979
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.622610043
Short name T499
Test name
Test status
Simulation time 30128010305 ps
CPU time 70.58 seconds
Started Jul 14 07:01:48 PM PDT 24
Finished Jul 14 07:02:59 PM PDT 24
Peak memory 201704 kb
Host smart-7cb2aa0d-5517-4a78-b0cd-ced3d42f254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622610043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.622610043
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4139073926
Short name T797
Test name
Test status
Simulation time 5372623374 ps
CPU time 3.9 seconds
Started Jul 14 07:01:50 PM PDT 24
Finished Jul 14 07:01:54 PM PDT 24
Peak memory 201620 kb
Host smart-d631f743-67fb-4378-b753-91f29dc99321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139073926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4139073926
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3326481498
Short name T783
Test name
Test status
Simulation time 5638100936 ps
CPU time 2.5 seconds
Started Jul 14 07:01:41 PM PDT 24
Finished Jul 14 07:01:44 PM PDT 24
Peak memory 201652 kb
Host smart-f00da6f0-6096-4217-9fde-222a365309f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326481498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3326481498
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1440271503
Short name T543
Test name
Test status
Simulation time 333244944701 ps
CPU time 85.33 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:03:13 PM PDT 24
Peak memory 210244 kb
Host smart-98b385a1-b342-45cf-84d3-a163ccf99202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440271503 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1440271503
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.413575096
Short name T29
Test name
Test status
Simulation time 439322863 ps
CPU time 0.87 seconds
Started Jul 14 07:01:52 PM PDT 24
Finished Jul 14 07:01:53 PM PDT 24
Peak memory 201660 kb
Host smart-b9c42cb8-20ac-4a06-9566-ed85e599ec06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413575096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.413575096
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.690553175
Short name T273
Test name
Test status
Simulation time 162228909150 ps
CPU time 178.35 seconds
Started Jul 14 07:01:53 PM PDT 24
Finished Jul 14 07:04:52 PM PDT 24
Peak memory 201844 kb
Host smart-6d7eedbf-7d6e-49a9-ad8e-0eddb937fafc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690553175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.690553175
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1918633206
Short name T167
Test name
Test status
Simulation time 494824211377 ps
CPU time 552.09 seconds
Started Jul 14 07:01:45 PM PDT 24
Finished Jul 14 07:10:58 PM PDT 24
Peak memory 201876 kb
Host smart-e927f784-8e4a-4d77-9361-85ee51987362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918633206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1918633206
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2045945700
Short name T634
Test name
Test status
Simulation time 160657976374 ps
CPU time 173.89 seconds
Started Jul 14 07:01:49 PM PDT 24
Finished Jul 14 07:04:44 PM PDT 24
Peak memory 201884 kb
Host smart-09e900f2-b604-478e-b654-e000192bafc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045945700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2045945700
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1219329516
Short name T734
Test name
Test status
Simulation time 164339495558 ps
CPU time 106.11 seconds
Started Jul 14 07:01:47 PM PDT 24
Finished Jul 14 07:03:34 PM PDT 24
Peak memory 201892 kb
Host smart-4a94dd1d-3c24-4a26-a0de-8cb7590b72f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219329516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1219329516
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3677662731
Short name T382
Test name
Test status
Simulation time 162950911609 ps
CPU time 182.39 seconds
Started Jul 14 07:01:48 PM PDT 24
Finished Jul 14 07:04:51 PM PDT 24
Peak memory 201872 kb
Host smart-d213519b-3402-40c8-bba9-685321611b1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677662731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3677662731
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2214770621
Short name T227
Test name
Test status
Simulation time 187735938875 ps
CPU time 99.4 seconds
Started Jul 14 07:01:46 PM PDT 24
Finished Jul 14 07:03:27 PM PDT 24
Peak memory 201980 kb
Host smart-02324d0a-4d7c-4086-ba9d-0e19b334a5c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214770621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2214770621
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1223397329
Short name T422
Test name
Test status
Simulation time 413436664286 ps
CPU time 109.87 seconds
Started Jul 14 07:01:46 PM PDT 24
Finished Jul 14 07:03:36 PM PDT 24
Peak memory 201852 kb
Host smart-2813086d-e984-472c-a6df-f70b2ed48d1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223397329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1223397329
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2833068386
Short name T510
Test name
Test status
Simulation time 83328891209 ps
CPU time 426.89 seconds
Started Jul 14 07:01:53 PM PDT 24
Finished Jul 14 07:09:00 PM PDT 24
Peak memory 202180 kb
Host smart-61680562-b5a9-43b8-9ab7-a6d314d9f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833068386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2833068386
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1991894405
Short name T441
Test name
Test status
Simulation time 30157179156 ps
CPU time 70.21 seconds
Started Jul 14 07:01:52 PM PDT 24
Finished Jul 14 07:03:03 PM PDT 24
Peak memory 201720 kb
Host smart-a7dc1a9f-8db6-471e-8cd5-538269415d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991894405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1991894405
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.285239704
Short name T522
Test name
Test status
Simulation time 5409379398 ps
CPU time 12.17 seconds
Started Jul 14 07:01:53 PM PDT 24
Finished Jul 14 07:02:06 PM PDT 24
Peak memory 201720 kb
Host smart-34a61f23-282a-451b-9708-f3adbc06e2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285239704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.285239704
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1851574215
Short name T459
Test name
Test status
Simulation time 6155702799 ps
CPU time 14.02 seconds
Started Jul 14 07:01:46 PM PDT 24
Finished Jul 14 07:02:01 PM PDT 24
Peak memory 201704 kb
Host smart-d3ab6007-2932-4934-af8f-f4f1cdab766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851574215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1851574215
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2057792824
Short name T51
Test name
Test status
Simulation time 214811084614 ps
CPU time 301.8 seconds
Started Jul 14 07:01:52 PM PDT 24
Finished Jul 14 07:06:54 PM PDT 24
Peak memory 218676 kb
Host smart-dbf5f126-4dd3-485b-a8a0-a56391350c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057792824 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2057792824
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3638230102
Short name T424
Test name
Test status
Simulation time 356201991 ps
CPU time 0.78 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:02:05 PM PDT 24
Peak memory 201640 kb
Host smart-4e04392f-5a7b-4b63-8f30-bd10212d34c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638230102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3638230102
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3209397510
Short name T256
Test name
Test status
Simulation time 500406067252 ps
CPU time 564.21 seconds
Started Jul 14 07:01:50 PM PDT 24
Finished Jul 14 07:11:15 PM PDT 24
Peak memory 201972 kb
Host smart-ce776214-8221-4e07-a93a-65b2ba4963e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209397510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3209397510
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.4172765645
Short name T428
Test name
Test status
Simulation time 326039722321 ps
CPU time 758.08 seconds
Started Jul 14 07:02:00 PM PDT 24
Finished Jul 14 07:14:38 PM PDT 24
Peak memory 201868 kb
Host smart-80f47351-f402-4ecb-aa91-d41b1e5e5c05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172765645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.4172765645
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3207043401
Short name T183
Test name
Test status
Simulation time 159785997865 ps
CPU time 191.87 seconds
Started Jul 14 07:01:52 PM PDT 24
Finished Jul 14 07:05:05 PM PDT 24
Peak memory 201880 kb
Host smart-d00c689f-0b38-441f-ab75-97124ac84882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207043401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3207043401
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2027091966
Short name T409
Test name
Test status
Simulation time 164334860800 ps
CPU time 385.99 seconds
Started Jul 14 07:01:52 PM PDT 24
Finished Jul 14 07:08:19 PM PDT 24
Peak memory 202156 kb
Host smart-6148b65e-8735-4001-84f7-7a40352aa769
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027091966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2027091966
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3583259935
Short name T640
Test name
Test status
Simulation time 609859807099 ps
CPU time 357.46 seconds
Started Jul 14 07:02:01 PM PDT 24
Finished Jul 14 07:07:58 PM PDT 24
Peak memory 201924 kb
Host smart-e05f6a00-2c62-43c4-b047-4c963d006358
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583259935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3583259935
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4053759938
Short name T759
Test name
Test status
Simulation time 116748976973 ps
CPU time 407.17 seconds
Started Jul 14 07:01:59 PM PDT 24
Finished Jul 14 07:08:47 PM PDT 24
Peak memory 202240 kb
Host smart-bad1501d-9fbb-4ad5-827a-c639f5c3f2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053759938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4053759938
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3421939322
Short name T8
Test name
Test status
Simulation time 22286949938 ps
CPU time 50.31 seconds
Started Jul 14 07:01:58 PM PDT 24
Finished Jul 14 07:02:49 PM PDT 24
Peak memory 201700 kb
Host smart-3aa67754-c205-44bd-ac28-096e026da952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421939322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3421939322
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1305352213
Short name T671
Test name
Test status
Simulation time 5036247763 ps
CPU time 6.55 seconds
Started Jul 14 07:01:57 PM PDT 24
Finished Jul 14 07:02:04 PM PDT 24
Peak memory 201720 kb
Host smart-1d9339fb-ef32-4c1b-995c-41378d833b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305352213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1305352213
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3232594102
Short name T590
Test name
Test status
Simulation time 5761682549 ps
CPU time 4.23 seconds
Started Jul 14 07:01:54 PM PDT 24
Finished Jul 14 07:01:59 PM PDT 24
Peak memory 201724 kb
Host smart-8daec607-1566-4a53-bf9d-19ebaa223f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232594102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3232594102
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2848496953
Short name T574
Test name
Test status
Simulation time 197375391213 ps
CPU time 211.36 seconds
Started Jul 14 07:02:00 PM PDT 24
Finished Jul 14 07:05:32 PM PDT 24
Peak memory 201972 kb
Host smart-53f16c5e-6f5f-481d-b6c7-cdddd5404dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848496953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2848496953
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3987780035
Short name T19
Test name
Test status
Simulation time 118551243728 ps
CPU time 205.85 seconds
Started Jul 14 07:02:00 PM PDT 24
Finished Jul 14 07:05:26 PM PDT 24
Peak memory 210512 kb
Host smart-335c2013-6a8f-41bc-ad04-125786371f12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987780035 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3987780035
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.4207351082
Short name T371
Test name
Test status
Simulation time 541616445 ps
CPU time 0.89 seconds
Started Jul 14 07:00:40 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 201668 kb
Host smart-2d5893a3-0292-4e41-80b2-3cf953db76d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207351082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.4207351082
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3899354666
Short name T732
Test name
Test status
Simulation time 184764902021 ps
CPU time 7.28 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:00:58 PM PDT 24
Peak memory 201880 kb
Host smart-a8aedad6-cfd1-44e8-9514-9cc5a7fa4252
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899354666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3899354666
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1875201475
Short name T105
Test name
Test status
Simulation time 498603976148 ps
CPU time 1132.54 seconds
Started Jul 14 07:00:41 PM PDT 24
Finished Jul 14 07:19:35 PM PDT 24
Peak memory 201916 kb
Host smart-54984f45-00c4-4003-9b82-ddb1ac7ca7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875201475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1875201475
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.891663185
Short name T1
Test name
Test status
Simulation time 161992920590 ps
CPU time 190.94 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:04:02 PM PDT 24
Peak memory 201972 kb
Host smart-aade36f0-cb3b-4eb9-a1bd-790ed4a825b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891663185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.891663185
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2836662415
Short name T760
Test name
Test status
Simulation time 164088407354 ps
CPU time 105.57 seconds
Started Jul 14 07:00:37 PM PDT 24
Finished Jul 14 07:02:24 PM PDT 24
Peak memory 201824 kb
Host smart-4661e236-4f7c-4f13-8c50-d90734a52130
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836662415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2836662415
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4286930494
Short name T426
Test name
Test status
Simulation time 160033990039 ps
CPU time 26.46 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:01:12 PM PDT 24
Peak memory 201924 kb
Host smart-5cf6ee41-1770-4f73-88d2-41c4eaa6c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286930494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4286930494
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3390507476
Short name T768
Test name
Test status
Simulation time 499253012866 ps
CPU time 280.2 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:05:31 PM PDT 24
Peak memory 201916 kb
Host smart-6bf4f992-ffff-4dea-a9c7-59a72ade2455
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390507476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3390507476
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.860044953
Short name T302
Test name
Test status
Simulation time 177840720672 ps
CPU time 400.18 seconds
Started Jul 14 07:00:36 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 201976 kb
Host smart-56406624-6498-47e3-8009-431b2ae9b266
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860044953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.860044953
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.133293897
Short name T506
Test name
Test status
Simulation time 417549805688 ps
CPU time 453.03 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:08:23 PM PDT 24
Peak memory 201892 kb
Host smart-71e8d707-2b0c-480a-b42b-c9b0b1be2db4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133293897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.133293897
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2602751121
Short name T405
Test name
Test status
Simulation time 84589922809 ps
CPU time 453.47 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:08:21 PM PDT 24
Peak memory 202232 kb
Host smart-e2f8b621-570a-4216-a305-8b43ec0bb2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602751121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2602751121
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3548538967
Short name T448
Test name
Test status
Simulation time 22487818971 ps
CPU time 53.5 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:01:41 PM PDT 24
Peak memory 201684 kb
Host smart-66acfe6b-b01f-45a8-9d4b-bec4da05c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548538967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3548538967
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.410934402
Short name T346
Test name
Test status
Simulation time 4642515478 ps
CPU time 2.04 seconds
Started Jul 14 07:00:38 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 201720 kb
Host smart-0b959c5a-e0c8-4ae3-aa1c-b1608832aec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410934402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.410934402
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.801562734
Short name T70
Test name
Test status
Simulation time 3991936252 ps
CPU time 5.54 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:00:43 PM PDT 24
Peak memory 217132 kb
Host smart-3102d298-d936-4444-91a9-2821e5a2b6de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801562734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.801562734
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1756433908
Short name T353
Test name
Test status
Simulation time 5675654832 ps
CPU time 7.03 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:00:53 PM PDT 24
Peak memory 201684 kb
Host smart-3b85646c-2beb-46c2-9ed5-8cd1fe9ae94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756433908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1756433908
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1994924986
Short name T354
Test name
Test status
Simulation time 41096220779 ps
CPU time 22.26 seconds
Started Jul 14 07:00:30 PM PDT 24
Finished Jul 14 07:00:56 PM PDT 24
Peak memory 201708 kb
Host smart-a513ec08-ff2a-48cb-8ee2-f67008232425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994924986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1994924986
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1289322966
Short name T102
Test name
Test status
Simulation time 268168332264 ps
CPU time 177.92 seconds
Started Jul 14 07:00:35 PM PDT 24
Finished Jul 14 07:03:35 PM PDT 24
Peak memory 218132 kb
Host smart-f02462be-9708-49d5-84e3-ade73fdb83cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289322966 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1289322966
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.266744623
Short name T696
Test name
Test status
Simulation time 343910327 ps
CPU time 1.42 seconds
Started Jul 14 07:02:03 PM PDT 24
Finished Jul 14 07:02:05 PM PDT 24
Peak memory 201676 kb
Host smart-ecfe563c-f4af-4450-a0e0-6120611fdebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266744623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.266744623
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3478115598
Short name T604
Test name
Test status
Simulation time 167615168967 ps
CPU time 266.06 seconds
Started Jul 14 07:02:06 PM PDT 24
Finished Jul 14 07:06:32 PM PDT 24
Peak memory 201904 kb
Host smart-b75363c2-3488-4bb1-ae0d-f376db484dc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478115598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3478115598
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2484729148
Short name T304
Test name
Test status
Simulation time 326057653818 ps
CPU time 717.89 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:14:03 PM PDT 24
Peak memory 201896 kb
Host smart-7a4903d8-5f9b-4b03-8656-a15c3ad49015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484729148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2484729148
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2959473661
Short name T531
Test name
Test status
Simulation time 326124833640 ps
CPU time 108.49 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:03:53 PM PDT 24
Peak memory 201860 kb
Host smart-028b785c-89e0-4b49-a4ff-445d6545afd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959473661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2959473661
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3972954554
Short name T106
Test name
Test status
Simulation time 490972983226 ps
CPU time 268.38 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:06:33 PM PDT 24
Peak memory 201892 kb
Host smart-bb3bc2cc-52b8-465d-b27f-5d71e6ab9bdc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972954554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3972954554
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3098152814
Short name T597
Test name
Test status
Simulation time 169935217312 ps
CPU time 388.11 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:08:33 PM PDT 24
Peak memory 201932 kb
Host smart-817b0524-d19d-4c3e-9a86-d04217eff4ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098152814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3098152814
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1860100040
Short name T494
Test name
Test status
Simulation time 409532517490 ps
CPU time 445.61 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:09:31 PM PDT 24
Peak memory 201872 kb
Host smart-45c941ca-e674-4240-9202-432c06c36e5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860100040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1860100040
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1071656456
Short name T445
Test name
Test status
Simulation time 107044174205 ps
CPU time 439.91 seconds
Started Jul 14 07:02:02 PM PDT 24
Finished Jul 14 07:09:23 PM PDT 24
Peak memory 202252 kb
Host smart-696e9f07-e455-4fb6-8076-e70f40941137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071656456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1071656456
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2011955017
Short name T467
Test name
Test status
Simulation time 28961747089 ps
CPU time 66.31 seconds
Started Jul 14 07:02:03 PM PDT 24
Finished Jul 14 07:03:10 PM PDT 24
Peak memory 201656 kb
Host smart-8e9594da-fb4f-4b0f-a9ea-89aa9da06380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011955017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2011955017
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.677029051
Short name T362
Test name
Test status
Simulation time 3225243568 ps
CPU time 7.72 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:02:12 PM PDT 24
Peak memory 201760 kb
Host smart-bd4b6e65-24a4-4926-884d-8f41c6af89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677029051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.677029051
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1358258658
Short name T470
Test name
Test status
Simulation time 5749464526 ps
CPU time 13.56 seconds
Started Jul 14 07:02:05 PM PDT 24
Finished Jul 14 07:02:19 PM PDT 24
Peak memory 201724 kb
Host smart-ff969e32-ee93-4ba6-bb26-2774e0285319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358258658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1358258658
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4127679036
Short name T74
Test name
Test status
Simulation time 194243696040 ps
CPU time 38.42 seconds
Started Jul 14 07:02:04 PM PDT 24
Finished Jul 14 07:02:44 PM PDT 24
Peak memory 201960 kb
Host smart-6ccb8254-d82e-4e3b-8a4a-e0d1b049c80a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127679036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4127679036
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.989400567
Short name T49
Test name
Test status
Simulation time 89884270837 ps
CPU time 196.39 seconds
Started Jul 14 07:02:03 PM PDT 24
Finished Jul 14 07:05:20 PM PDT 24
Peak memory 210160 kb
Host smart-5c71b86c-b4c6-4dfb-8dbc-42e16475d3ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989400567 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.989400567
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3884389828
Short name T463
Test name
Test status
Simulation time 340544958 ps
CPU time 0.98 seconds
Started Jul 14 07:02:11 PM PDT 24
Finished Jul 14 07:02:12 PM PDT 24
Peak memory 201564 kb
Host smart-68732b3b-5527-4930-adcb-6afab956606a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884389828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3884389828
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.756061814
Short name T223
Test name
Test status
Simulation time 326830181859 ps
CPU time 712.9 seconds
Started Jul 14 07:02:15 PM PDT 24
Finished Jul 14 07:14:08 PM PDT 24
Peak memory 201972 kb
Host smart-9c23526f-9d83-44e8-844d-0afd542f2e17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756061814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.756061814
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2183848305
Short name T311
Test name
Test status
Simulation time 334099434145 ps
CPU time 277.8 seconds
Started Jul 14 07:02:10 PM PDT 24
Finished Jul 14 07:06:49 PM PDT 24
Peak memory 201896 kb
Host smart-f834dbc2-a04d-4b3b-b118-4de4cc75f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183848305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2183848305
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.500176171
Short name T579
Test name
Test status
Simulation time 165899594011 ps
CPU time 352.73 seconds
Started Jul 14 07:02:12 PM PDT 24
Finished Jul 14 07:08:05 PM PDT 24
Peak memory 201844 kb
Host smart-df39ffc8-4d96-422e-9aeb-5614869e3caa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=500176171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.500176171
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.818278662
Short name T263
Test name
Test status
Simulation time 334160187916 ps
CPU time 734.39 seconds
Started Jul 14 07:02:10 PM PDT 24
Finished Jul 14 07:14:25 PM PDT 24
Peak memory 201916 kb
Host smart-c6f35203-6663-49a1-8022-7e3946e1ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818278662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.818278662
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3231519930
Short name T442
Test name
Test status
Simulation time 163491453116 ps
CPU time 100.38 seconds
Started Jul 14 07:02:09 PM PDT 24
Finished Jul 14 07:03:51 PM PDT 24
Peak memory 201756 kb
Host smart-41e934f8-b0f2-4b81-882e-b4c43c1b2f07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231519930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3231519930
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3248462019
Short name T171
Test name
Test status
Simulation time 188041165493 ps
CPU time 96.96 seconds
Started Jul 14 07:02:10 PM PDT 24
Finished Jul 14 07:03:48 PM PDT 24
Peak memory 201824 kb
Host smart-e8828256-9e3c-464a-a577-91ee6277c93f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248462019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3248462019
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1472669370
Short name T593
Test name
Test status
Simulation time 413678194892 ps
CPU time 447.12 seconds
Started Jul 14 07:02:08 PM PDT 24
Finished Jul 14 07:09:36 PM PDT 24
Peak memory 201896 kb
Host smart-5ea16e4d-9b4f-4eb3-9e6b-737253ae33a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472669370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1472669370
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1526165956
Short name T719
Test name
Test status
Simulation time 121579293189 ps
CPU time 510.97 seconds
Started Jul 14 07:02:09 PM PDT 24
Finished Jul 14 07:10:41 PM PDT 24
Peak memory 202200 kb
Host smart-1cd20049-8fdb-4c32-b247-6c4c562d0997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526165956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1526165956
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.675149116
Short name T620
Test name
Test status
Simulation time 25468006175 ps
CPU time 12.34 seconds
Started Jul 14 07:02:09 PM PDT 24
Finished Jul 14 07:02:22 PM PDT 24
Peak memory 201716 kb
Host smart-e171372b-7ee7-4e96-a8f6-d7650c91591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675149116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.675149116
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3959276756
Short name T466
Test name
Test status
Simulation time 3181723241 ps
CPU time 2.14 seconds
Started Jul 14 07:02:09 PM PDT 24
Finished Jul 14 07:02:11 PM PDT 24
Peak memory 201696 kb
Host smart-72a8b411-53f0-47ab-8081-b9b1eb31b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959276756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3959276756
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1944428394
Short name T615
Test name
Test status
Simulation time 5686282625 ps
CPU time 12.86 seconds
Started Jul 14 07:02:09 PM PDT 24
Finished Jul 14 07:02:22 PM PDT 24
Peak memory 201740 kb
Host smart-2035d88f-647a-432e-ad34-194ecc09dc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944428394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1944428394
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2522058516
Short name T786
Test name
Test status
Simulation time 436191883105 ps
CPU time 530.33 seconds
Started Jul 14 07:02:10 PM PDT 24
Finished Jul 14 07:11:01 PM PDT 24
Peak memory 210368 kb
Host smart-208cf775-73c5-465e-b5fa-b249969a5ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522058516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2522058516
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.640727036
Short name T42
Test name
Test status
Simulation time 147745156765 ps
CPU time 233.34 seconds
Started Jul 14 07:02:09 PM PDT 24
Finished Jul 14 07:06:04 PM PDT 24
Peak memory 217628 kb
Host smart-5ac16933-a36a-4560-985b-127bdb755dc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640727036 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.640727036
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2504835683
Short name T75
Test name
Test status
Simulation time 305459739 ps
CPU time 1.26 seconds
Started Jul 14 07:02:16 PM PDT 24
Finished Jul 14 07:02:18 PM PDT 24
Peak memory 201652 kb
Host smart-ce6bf936-11fd-4caa-b1b5-191b2971e130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504835683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2504835683
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2890283562
Short name T291
Test name
Test status
Simulation time 525672756582 ps
CPU time 126.18 seconds
Started Jul 14 07:02:16 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 201892 kb
Host smart-754e073e-6846-4287-baf8-bae533fa7e78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890283562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2890283562
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1505750957
Short name T121
Test name
Test status
Simulation time 326065807488 ps
CPU time 194.69 seconds
Started Jul 14 07:02:10 PM PDT 24
Finished Jul 14 07:05:25 PM PDT 24
Peak memory 201888 kb
Host smart-a420c494-3882-4e91-b35d-60d96c53e05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505750957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1505750957
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1971645730
Short name T488
Test name
Test status
Simulation time 325571445465 ps
CPU time 184.84 seconds
Started Jul 14 07:02:18 PM PDT 24
Finished Jul 14 07:05:23 PM PDT 24
Peak memory 201908 kb
Host smart-0251f431-68c4-4ba7-b420-a83d495d9685
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971645730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1971645730
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.334179293
Short name T758
Test name
Test status
Simulation time 331767050256 ps
CPU time 184.77 seconds
Started Jul 14 07:02:10 PM PDT 24
Finished Jul 14 07:05:15 PM PDT 24
Peak memory 201952 kb
Host smart-b278b4b3-9583-4ff0-9536-1eaee5584d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334179293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.334179293
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2158230534
Short name T550
Test name
Test status
Simulation time 493521897464 ps
CPU time 1017.21 seconds
Started Jul 14 07:02:08 PM PDT 24
Finished Jul 14 07:19:06 PM PDT 24
Peak memory 201960 kb
Host smart-969a040f-1c29-4d3b-a874-96f26229abb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158230534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2158230534
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.923958516
Short name T551
Test name
Test status
Simulation time 177682145288 ps
CPU time 407.13 seconds
Started Jul 14 07:02:14 PM PDT 24
Finished Jul 14 07:09:02 PM PDT 24
Peak memory 201936 kb
Host smart-4bae2afa-3232-4ede-a77f-9fcffda69c3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923958516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.923958516
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1299340876
Short name T415
Test name
Test status
Simulation time 200220573967 ps
CPU time 425.47 seconds
Started Jul 14 07:02:14 PM PDT 24
Finished Jul 14 07:09:20 PM PDT 24
Peak memory 201864 kb
Host smart-57d20c01-dfb0-41d7-88ca-a137aedffee9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299340876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1299340876
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.264557907
Short name T541
Test name
Test status
Simulation time 91315649876 ps
CPU time 388.92 seconds
Started Jul 14 07:02:19 PM PDT 24
Finished Jul 14 07:08:48 PM PDT 24
Peak memory 202300 kb
Host smart-43230881-2082-49ba-bc9e-1c0e3e2543b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264557907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.264557907
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3984472086
Short name T406
Test name
Test status
Simulation time 29737319717 ps
CPU time 64.22 seconds
Started Jul 14 07:02:15 PM PDT 24
Finished Jul 14 07:03:20 PM PDT 24
Peak memory 201616 kb
Host smart-187eb63c-5828-40c4-89d1-7a78ce1657cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984472086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3984472086
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1757116845
Short name T477
Test name
Test status
Simulation time 3419849563 ps
CPU time 1.83 seconds
Started Jul 14 07:02:18 PM PDT 24
Finished Jul 14 07:02:20 PM PDT 24
Peak memory 201728 kb
Host smart-a2511795-278e-431a-a349-60e7a536e35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757116845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1757116845
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2035718417
Short name T530
Test name
Test status
Simulation time 5859209506 ps
CPU time 14.64 seconds
Started Jul 14 07:02:09 PM PDT 24
Finished Jul 14 07:02:25 PM PDT 24
Peak memory 201732 kb
Host smart-cbb0d119-7ceb-4a49-9f91-4c171ef6d63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035718417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2035718417
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1573322603
Short name T240
Test name
Test status
Simulation time 218678306516 ps
CPU time 259.56 seconds
Started Jul 14 07:02:15 PM PDT 24
Finished Jul 14 07:06:35 PM PDT 24
Peak memory 201884 kb
Host smart-ee7e7c58-d2ae-4d11-ab0b-5e931d4323cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573322603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1573322603
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.41233595
Short name T700
Test name
Test status
Simulation time 211360428921 ps
CPU time 123.23 seconds
Started Jul 14 07:02:14 PM PDT 24
Finished Jul 14 07:04:18 PM PDT 24
Peak memory 210608 kb
Host smart-31fd5e3a-95c2-46ad-bc3f-47e91a109558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41233595 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.41233595
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4076893037
Short name T465
Test name
Test status
Simulation time 289037235 ps
CPU time 1.25 seconds
Started Jul 14 07:02:18 PM PDT 24
Finished Jul 14 07:02:20 PM PDT 24
Peak memory 201524 kb
Host smart-00f69b06-e418-48a9-8a94-9ee3ee3560d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076893037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4076893037
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1857388000
Short name T563
Test name
Test status
Simulation time 198027593131 ps
CPU time 450.45 seconds
Started Jul 14 07:02:24 PM PDT 24
Finished Jul 14 07:09:55 PM PDT 24
Peak memory 201968 kb
Host smart-6ed1bf39-5dd6-4168-9c87-16119e751bcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857388000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1857388000
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4267442165
Short name T94
Test name
Test status
Simulation time 169920209038 ps
CPU time 379.93 seconds
Started Jul 14 07:02:19 PM PDT 24
Finished Jul 14 07:08:39 PM PDT 24
Peak memory 201896 kb
Host smart-350f66ea-f71c-4461-896c-4a53bbc9c175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267442165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4267442165
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1989559661
Short name T329
Test name
Test status
Simulation time 161748454592 ps
CPU time 298.02 seconds
Started Jul 14 07:02:18 PM PDT 24
Finished Jul 14 07:07:16 PM PDT 24
Peak memory 201856 kb
Host smart-37ed6de5-0b2a-424d-ad68-4ae061356fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989559661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1989559661
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1964198833
Short name T490
Test name
Test status
Simulation time 332662267204 ps
CPU time 806.07 seconds
Started Jul 14 07:02:19 PM PDT 24
Finished Jul 14 07:15:46 PM PDT 24
Peak memory 201836 kb
Host smart-6c0ac9a2-22a4-42af-941c-f8283d115e08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964198833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1964198833
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3260298180
Short name T45
Test name
Test status
Simulation time 165813019719 ps
CPU time 182.8 seconds
Started Jul 14 07:02:20 PM PDT 24
Finished Jul 14 07:05:23 PM PDT 24
Peak memory 201980 kb
Host smart-47a6ae9f-743d-4c35-8d04-5ed04f54eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260298180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3260298180
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4032865417
Short name T546
Test name
Test status
Simulation time 499187768891 ps
CPU time 298.39 seconds
Started Jul 14 07:02:20 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 201896 kb
Host smart-169ce1b2-ae76-4cf6-8861-fbcff832a4be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032865417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4032865417
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.588946115
Short name T728
Test name
Test status
Simulation time 534954729278 ps
CPU time 124.44 seconds
Started Jul 14 07:02:19 PM PDT 24
Finished Jul 14 07:04:24 PM PDT 24
Peak memory 201992 kb
Host smart-d9f840f0-8b5f-4cc8-a944-e120608db0de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588946115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.588946115
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.362261909
Short name T451
Test name
Test status
Simulation time 615874604458 ps
CPU time 370.43 seconds
Started Jul 14 07:02:19 PM PDT 24
Finished Jul 14 07:08:31 PM PDT 24
Peak memory 201952 kb
Host smart-33ff7f64-d6d8-420f-948f-d5d81b06205b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362261909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.362261909
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.4067420081
Short name T437
Test name
Test status
Simulation time 100948539301 ps
CPU time 366.36 seconds
Started Jul 14 07:02:20 PM PDT 24
Finished Jul 14 07:08:27 PM PDT 24
Peak memory 202252 kb
Host smart-af7dc6aa-33e2-4e5d-8c46-dab3dd413d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067420081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4067420081
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4272682880
Short name T795
Test name
Test status
Simulation time 41585799952 ps
CPU time 96.31 seconds
Started Jul 14 07:02:20 PM PDT 24
Finished Jul 14 07:03:57 PM PDT 24
Peak memory 201732 kb
Host smart-74fce43b-9ba6-41ef-a696-65b220ed327f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272682880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4272682880
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.530219910
Short name T617
Test name
Test status
Simulation time 4827809296 ps
CPU time 11.89 seconds
Started Jul 14 07:02:20 PM PDT 24
Finished Jul 14 07:02:33 PM PDT 24
Peak memory 201768 kb
Host smart-5242162f-8b9b-48c7-9ede-823eed78138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530219910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.530219910
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2901460136
Short name T766
Test name
Test status
Simulation time 5547134100 ps
CPU time 12.85 seconds
Started Jul 14 07:02:16 PM PDT 24
Finished Jul 14 07:02:29 PM PDT 24
Peak memory 201724 kb
Host smart-87b849a0-86a0-4c77-a873-482398742be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901460136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2901460136
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2041776705
Short name T691
Test name
Test status
Simulation time 646338534708 ps
CPU time 538.25 seconds
Started Jul 14 07:02:20 PM PDT 24
Finished Jul 14 07:11:19 PM PDT 24
Peak memory 212948 kb
Host smart-1c237fa1-5be1-479e-a0f2-f67fe8d9e358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041776705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2041776705
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.862494234
Short name T114
Test name
Test status
Simulation time 118632477526 ps
CPU time 114.76 seconds
Started Jul 14 07:02:24 PM PDT 24
Finished Jul 14 07:04:19 PM PDT 24
Peak memory 210536 kb
Host smart-5ae41987-f9e3-444b-9a1b-770e7b684f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862494234 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.862494234
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2306219950
Short name T380
Test name
Test status
Simulation time 377629724 ps
CPU time 0.83 seconds
Started Jul 14 07:02:30 PM PDT 24
Finished Jul 14 07:02:31 PM PDT 24
Peak memory 201648 kb
Host smart-65ed4aa5-d93f-4310-95a8-480ad82d4851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306219950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2306219950
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.4106406042
Short name T242
Test name
Test status
Simulation time 187791969374 ps
CPU time 172.3 seconds
Started Jul 14 07:02:28 PM PDT 24
Finished Jul 14 07:05:21 PM PDT 24
Peak memory 201940 kb
Host smart-56326b7c-1131-4e04-b14b-80ecf7b6767a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106406042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.4106406042
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.4239319998
Short name T601
Test name
Test status
Simulation time 356605375606 ps
CPU time 188.5 seconds
Started Jul 14 07:02:27 PM PDT 24
Finished Jul 14 07:05:36 PM PDT 24
Peak memory 201892 kb
Host smart-629df947-9696-4b4d-ab76-3d5381634e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239319998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.4239319998
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1561614454
Short name T775
Test name
Test status
Simulation time 324494362815 ps
CPU time 61.57 seconds
Started Jul 14 07:02:26 PM PDT 24
Finished Jul 14 07:03:28 PM PDT 24
Peak memory 201984 kb
Host smart-b3686745-25f2-488a-a580-706e49f5d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561614454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1561614454
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3697337099
Short name T516
Test name
Test status
Simulation time 162128470154 ps
CPU time 367.27 seconds
Started Jul 14 07:02:26 PM PDT 24
Finished Jul 14 07:08:34 PM PDT 24
Peak memory 201932 kb
Host smart-6a188114-53ec-45cb-9515-96f8407c6a17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697337099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3697337099
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.894196775
Short name T293
Test name
Test status
Simulation time 490741492878 ps
CPU time 329.13 seconds
Started Jul 14 07:02:23 PM PDT 24
Finished Jul 14 07:07:53 PM PDT 24
Peak memory 201992 kb
Host smart-f31c3aa7-7b23-481c-97af-00fc39aa0156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894196775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.894196775
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.327287241
Short name T570
Test name
Test status
Simulation time 489850431622 ps
CPU time 1049.65 seconds
Started Jul 14 07:02:25 PM PDT 24
Finished Jul 14 07:19:55 PM PDT 24
Peak memory 201888 kb
Host smart-17afdf43-08db-423d-97c7-e75507d6470e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=327287241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.327287241
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2882644239
Short name T321
Test name
Test status
Simulation time 344271860179 ps
CPU time 222.75 seconds
Started Jul 14 07:02:25 PM PDT 24
Finished Jul 14 07:06:08 PM PDT 24
Peak memory 201992 kb
Host smart-79a32a60-846f-45ea-b095-b90c18c3f686
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882644239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2882644239
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1349105884
Short name T449
Test name
Test status
Simulation time 607776534387 ps
CPU time 203.85 seconds
Started Jul 14 07:02:26 PM PDT 24
Finished Jul 14 07:05:51 PM PDT 24
Peak memory 201908 kb
Host smart-581b3827-2e37-4298-946b-a15249a96a39
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349105884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1349105884
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1061816776
Short name T57
Test name
Test status
Simulation time 85909198691 ps
CPU time 471.39 seconds
Started Jul 14 07:02:31 PM PDT 24
Finished Jul 14 07:10:23 PM PDT 24
Peak memory 202208 kb
Host smart-b2b85005-2ff7-4380-8e10-5bbdee06413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061816776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1061816776
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2675284144
Short name T703
Test name
Test status
Simulation time 29906723332 ps
CPU time 19.93 seconds
Started Jul 14 07:02:31 PM PDT 24
Finished Jul 14 07:02:52 PM PDT 24
Peak memory 201692 kb
Host smart-f871f349-d26e-4e16-b1e6-6f5c4604b9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675284144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2675284144
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1878322844
Short name T799
Test name
Test status
Simulation time 4148296862 ps
CPU time 9.7 seconds
Started Jul 14 07:02:25 PM PDT 24
Finished Jul 14 07:02:35 PM PDT 24
Peak memory 201684 kb
Host smart-262a91a1-e865-4150-97bf-8ef4b75fff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878322844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1878322844
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2455240787
Short name T739
Test name
Test status
Simulation time 5916429748 ps
CPU time 14.25 seconds
Started Jul 14 07:02:29 PM PDT 24
Finished Jul 14 07:02:43 PM PDT 24
Peak memory 201720 kb
Host smart-1248d046-2be4-479f-838d-39a6117d173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455240787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2455240787
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.831399146
Short name T264
Test name
Test status
Simulation time 226284652599 ps
CPU time 368.88 seconds
Started Jul 14 07:02:31 PM PDT 24
Finished Jul 14 07:08:40 PM PDT 24
Peak memory 202268 kb
Host smart-ef30177a-4b0e-49d6-9b7f-b62a3d952de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831399146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
831399146
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2297938528
Short name T420
Test name
Test status
Simulation time 567108472 ps
CPU time 0.79 seconds
Started Jul 14 07:02:43 PM PDT 24
Finished Jul 14 07:02:44 PM PDT 24
Peak memory 201668 kb
Host smart-13971c33-00af-413b-b045-15be02899aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297938528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2297938528
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3428251241
Short name T117
Test name
Test status
Simulation time 502216504290 ps
CPU time 422.48 seconds
Started Jul 14 07:02:43 PM PDT 24
Finished Jul 14 07:09:46 PM PDT 24
Peak memory 201968 kb
Host smart-8e3b8440-d5cb-45f0-9037-244d0f8e5ec1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428251241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3428251241
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1155541285
Short name T186
Test name
Test status
Simulation time 340813583282 ps
CPU time 176.09 seconds
Started Jul 14 07:02:43 PM PDT 24
Finished Jul 14 07:05:40 PM PDT 24
Peak memory 201916 kb
Host smart-d51f88c5-fec4-49cb-ad7e-3c82ec89b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155541285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1155541285
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3140275863
Short name T190
Test name
Test status
Simulation time 332215464114 ps
CPU time 74.86 seconds
Started Jul 14 07:02:35 PM PDT 24
Finished Jul 14 07:03:51 PM PDT 24
Peak memory 202036 kb
Host smart-0277e120-7f21-4b59-8b08-f5da8b56b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140275863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3140275863
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1945676303
Short name T450
Test name
Test status
Simulation time 331772500002 ps
CPU time 154.62 seconds
Started Jul 14 07:02:42 PM PDT 24
Finished Jul 14 07:05:17 PM PDT 24
Peak memory 201880 kb
Host smart-47ed6aca-bede-457b-bab7-653b44826642
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945676303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1945676303
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1714050613
Short name T315
Test name
Test status
Simulation time 327724007724 ps
CPU time 339.69 seconds
Started Jul 14 07:02:37 PM PDT 24
Finished Jul 14 07:08:17 PM PDT 24
Peak memory 201924 kb
Host smart-7e30572b-4848-4701-aa88-bbf2e387bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714050613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1714050613
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3431375059
Short name T575
Test name
Test status
Simulation time 329619764684 ps
CPU time 402.66 seconds
Started Jul 14 07:02:36 PM PDT 24
Finished Jul 14 07:09:19 PM PDT 24
Peak memory 201880 kb
Host smart-c379548f-2dea-4a84-8365-1a52469bc019
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431375059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3431375059
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1859735737
Short name T98
Test name
Test status
Simulation time 537959434746 ps
CPU time 179.58 seconds
Started Jul 14 07:02:44 PM PDT 24
Finished Jul 14 07:05:44 PM PDT 24
Peak memory 201916 kb
Host smart-2a4c389d-42a3-4cd5-8d33-baad9717dc12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859735737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1859735737
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3240763920
Short name T733
Test name
Test status
Simulation time 601297314999 ps
CPU time 1370.57 seconds
Started Jul 14 07:02:41 PM PDT 24
Finished Jul 14 07:25:32 PM PDT 24
Peak memory 201776 kb
Host smart-081b21e4-47de-44e9-a0ae-17d9619bc75a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240763920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3240763920
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3271741653
Short name T201
Test name
Test status
Simulation time 98524350497 ps
CPU time 515.27 seconds
Started Jul 14 07:02:40 PM PDT 24
Finished Jul 14 07:11:16 PM PDT 24
Peak memory 202164 kb
Host smart-f8cce256-2356-47b8-9e95-bfb3ab49c0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271741653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3271741653
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3121401009
Short name T699
Test name
Test status
Simulation time 42344779910 ps
CPU time 6.65 seconds
Started Jul 14 07:02:42 PM PDT 24
Finished Jul 14 07:02:50 PM PDT 24
Peak memory 201696 kb
Host smart-a601217d-d70f-4664-92fa-a87d7f255c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121401009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3121401009
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.90366257
Short name T594
Test name
Test status
Simulation time 3191515252 ps
CPU time 4.38 seconds
Started Jul 14 07:02:39 PM PDT 24
Finished Jul 14 07:02:44 PM PDT 24
Peak memory 201700 kb
Host smart-59eec30a-3a48-45f4-a313-62d45e7a59ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90366257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.90366257
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3024309563
Short name T3
Test name
Test status
Simulation time 5799050148 ps
CPU time 14.97 seconds
Started Jul 14 07:02:36 PM PDT 24
Finished Jul 14 07:02:51 PM PDT 24
Peak memory 201724 kb
Host smart-9ef0cdfb-f951-4714-b0c2-1b5db6efd4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024309563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3024309563
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1323119550
Short name T410
Test name
Test status
Simulation time 409250737390 ps
CPU time 1516.56 seconds
Started Jul 14 07:02:42 PM PDT 24
Finished Jul 14 07:27:59 PM PDT 24
Peak memory 202216 kb
Host smart-1007c146-5212-47d0-b20d-4395f4ba5e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323119550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1323119550
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.788361120
Short name T548
Test name
Test status
Simulation time 417932431 ps
CPU time 1.08 seconds
Started Jul 14 07:02:54 PM PDT 24
Finished Jul 14 07:02:55 PM PDT 24
Peak memory 201664 kb
Host smart-029511af-bfd8-4a27-a30d-7cf845eaa733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788361120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.788361120
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3004841277
Short name T761
Test name
Test status
Simulation time 542651528445 ps
CPU time 327.95 seconds
Started Jul 14 07:02:48 PM PDT 24
Finished Jul 14 07:08:17 PM PDT 24
Peak memory 201976 kb
Host smart-f596ab2e-ffa0-4a03-88d6-5d6e4c4852b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004841277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3004841277
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2984823165
Short name T716
Test name
Test status
Simulation time 332788979347 ps
CPU time 209.27 seconds
Started Jul 14 07:02:47 PM PDT 24
Finished Jul 14 07:06:17 PM PDT 24
Peak memory 201844 kb
Host smart-d9158085-4a99-4a7a-aa97-a121823e9618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984823165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2984823165
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3673854694
Short name T711
Test name
Test status
Simulation time 165068742424 ps
CPU time 94.58 seconds
Started Jul 14 07:02:47 PM PDT 24
Finished Jul 14 07:04:22 PM PDT 24
Peak memory 201780 kb
Host smart-d04c0f04-e89b-4271-b18b-6434773c02eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673854694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3673854694
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3997570398
Short name T606
Test name
Test status
Simulation time 167380667241 ps
CPU time 68.84 seconds
Started Jul 14 07:02:47 PM PDT 24
Finished Jul 14 07:03:57 PM PDT 24
Peak memory 201892 kb
Host smart-4322c8ae-6132-41c8-b30a-73acc98f1a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997570398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3997570398
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2058579897
Short name T652
Test name
Test status
Simulation time 162660999540 ps
CPU time 396.78 seconds
Started Jul 14 07:02:46 PM PDT 24
Finished Jul 14 07:09:24 PM PDT 24
Peak memory 201872 kb
Host smart-475cda7e-2d38-41fc-a170-7a5dced8f38b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058579897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2058579897
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2281961080
Short name T212
Test name
Test status
Simulation time 554844440165 ps
CPU time 359.76 seconds
Started Jul 14 07:02:46 PM PDT 24
Finished Jul 14 07:08:47 PM PDT 24
Peak memory 201912 kb
Host smart-f0e5b9a4-d085-42fa-a528-3c91618df51f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281961080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2281961080
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2906937232
Short name T473
Test name
Test status
Simulation time 198334377734 ps
CPU time 115.35 seconds
Started Jul 14 07:02:48 PM PDT 24
Finished Jul 14 07:04:44 PM PDT 24
Peak memory 201880 kb
Host smart-4efc9dce-68e1-4146-9ede-62b0a1a9aff3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906937232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2906937232
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1495249478
Short name T534
Test name
Test status
Simulation time 110059769312 ps
CPU time 582.54 seconds
Started Jul 14 07:02:47 PM PDT 24
Finished Jul 14 07:12:30 PM PDT 24
Peak memory 202240 kb
Host smart-0282b239-dbfe-4c53-9473-e453c0a21df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495249478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1495249478
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.115056726
Short name T96
Test name
Test status
Simulation time 28887636598 ps
CPU time 16.97 seconds
Started Jul 14 07:02:48 PM PDT 24
Finished Jul 14 07:03:06 PM PDT 24
Peak memory 201724 kb
Host smart-698e293a-85e6-4c5a-9f42-30674419c08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115056726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.115056726
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3388462971
Short name T435
Test name
Test status
Simulation time 4103546009 ps
CPU time 9.33 seconds
Started Jul 14 07:02:46 PM PDT 24
Finished Jul 14 07:02:57 PM PDT 24
Peak memory 201692 kb
Host smart-4ac94034-f19b-4c3b-bc96-ceaade48e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388462971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3388462971
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1897630523
Short name T743
Test name
Test status
Simulation time 5847953607 ps
CPU time 14.55 seconds
Started Jul 14 07:02:47 PM PDT 24
Finished Jul 14 07:03:03 PM PDT 24
Peak memory 201612 kb
Host smart-5dbc1432-e214-4328-9813-d75dfe1bc8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897630523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1897630523
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1152512153
Short name T413
Test name
Test status
Simulation time 104944626102 ps
CPU time 343.05 seconds
Started Jul 14 07:02:54 PM PDT 24
Finished Jul 14 07:08:37 PM PDT 24
Peak memory 202172 kb
Host smart-fb5e6858-9535-4cf9-84bb-af5fd931df45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152512153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1152512153
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.987939458
Short name T36
Test name
Test status
Simulation time 98688811016 ps
CPU time 54.7 seconds
Started Jul 14 07:02:55 PM PDT 24
Finished Jul 14 07:03:51 PM PDT 24
Peak memory 209992 kb
Host smart-e2a3f5c8-289c-406f-9862-3a95c05b8fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987939458 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.987939458
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2100364831
Short name T653
Test name
Test status
Simulation time 505591484 ps
CPU time 0.81 seconds
Started Jul 14 07:03:00 PM PDT 24
Finished Jul 14 07:03:01 PM PDT 24
Peak memory 201708 kb
Host smart-031591b6-b68d-48d5-8eff-29c662e8029e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100364831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2100364831
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2765247310
Short name T782
Test name
Test status
Simulation time 376106962042 ps
CPU time 843.8 seconds
Started Jul 14 07:02:59 PM PDT 24
Finished Jul 14 07:17:03 PM PDT 24
Peak memory 201912 kb
Host smart-b36a4819-05b1-4d0c-909a-1e274dfbf412
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765247310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2765247310
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4267413539
Short name T792
Test name
Test status
Simulation time 163414160206 ps
CPU time 367.86 seconds
Started Jul 14 07:02:55 PM PDT 24
Finished Jul 14 07:09:04 PM PDT 24
Peak memory 201784 kb
Host smart-26c8a692-42b9-4f22-96dc-1b1e9a32d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267413539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4267413539
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4001608658
Short name T438
Test name
Test status
Simulation time 485848769589 ps
CPU time 1060.35 seconds
Started Jul 14 07:02:57 PM PDT 24
Finished Jul 14 07:20:38 PM PDT 24
Peak memory 201884 kb
Host smart-18364a74-f69a-42af-a3d2-4ac2436f3793
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001608658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4001608658
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2207510902
Short name T164
Test name
Test status
Simulation time 165320622197 ps
CPU time 395.58 seconds
Started Jul 14 07:02:53 PM PDT 24
Finished Jul 14 07:09:29 PM PDT 24
Peak memory 201924 kb
Host smart-5bac41a6-d663-4959-9038-384f7fe9f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207510902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2207510902
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.339074671
Short name T793
Test name
Test status
Simulation time 496982427735 ps
CPU time 264.66 seconds
Started Jul 14 07:02:53 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 201888 kb
Host smart-58e39042-4e0e-4fc2-bdfa-f52cc6f00642
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=339074671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.339074671
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.395754901
Short name T100
Test name
Test status
Simulation time 436939032256 ps
CPU time 744.94 seconds
Started Jul 14 07:02:57 PM PDT 24
Finished Jul 14 07:15:23 PM PDT 24
Peak memory 201912 kb
Host smart-fdf766b6-b3e7-4256-ba26-0360ae55e622
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395754901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.395754901
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3818584083
Short name T423
Test name
Test status
Simulation time 596221320519 ps
CPU time 758.63 seconds
Started Jul 14 07:02:58 PM PDT 24
Finished Jul 14 07:15:37 PM PDT 24
Peak memory 201892 kb
Host smart-16e2c15e-d336-4261-abd5-8d2241bb6ca6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818584083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3818584083
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4050808975
Short name T694
Test name
Test status
Simulation time 102253121389 ps
CPU time 497.76 seconds
Started Jul 14 07:02:59 PM PDT 24
Finished Jul 14 07:11:17 PM PDT 24
Peak memory 202196 kb
Host smart-9027abd6-3672-4cff-9f07-c7fb4cb2c881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050808975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4050808975
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1128775127
Short name T500
Test name
Test status
Simulation time 44926900473 ps
CPU time 26.74 seconds
Started Jul 14 07:03:00 PM PDT 24
Finished Jul 14 07:03:27 PM PDT 24
Peak memory 201656 kb
Host smart-b57b66e6-145d-499e-ae39-b979460c94b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128775127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1128775127
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3594891465
Short name T492
Test name
Test status
Simulation time 3271125255 ps
CPU time 2.59 seconds
Started Jul 14 07:02:57 PM PDT 24
Finished Jul 14 07:03:00 PM PDT 24
Peak memory 201700 kb
Host smart-e678d44d-d04b-4e72-b51c-eaf8c051b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594891465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3594891465
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.331770801
Short name T756
Test name
Test status
Simulation time 5924147686 ps
CPU time 13.07 seconds
Started Jul 14 07:02:53 PM PDT 24
Finished Jul 14 07:03:06 PM PDT 24
Peak memory 201724 kb
Host smart-78ac25c6-c682-4f4c-be76-f3d0d25b759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331770801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.331770801
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2472697217
Short name T789
Test name
Test status
Simulation time 339251656730 ps
CPU time 200.78 seconds
Started Jul 14 07:02:58 PM PDT 24
Finished Jul 14 07:06:20 PM PDT 24
Peak memory 201916 kb
Host smart-38ad6c61-ba7a-467b-9565-b902eca6f557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472697217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2472697217
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1113674231
Short name T790
Test name
Test status
Simulation time 297665397 ps
CPU time 1.33 seconds
Started Jul 14 07:03:10 PM PDT 24
Finished Jul 14 07:03:12 PM PDT 24
Peak memory 201696 kb
Host smart-5d36f3e9-33c9-457e-a453-99731b0d02b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113674231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1113674231
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2678541763
Short name T301
Test name
Test status
Simulation time 590892705418 ps
CPU time 1396.15 seconds
Started Jul 14 07:03:05 PM PDT 24
Finished Jul 14 07:26:22 PM PDT 24
Peak memory 201844 kb
Host smart-78ec3ad7-3102-4878-bd3d-bff6d83aa0ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678541763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2678541763
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.703371442
Short name T662
Test name
Test status
Simulation time 337724408735 ps
CPU time 715.67 seconds
Started Jul 14 07:03:05 PM PDT 24
Finished Jul 14 07:15:02 PM PDT 24
Peak memory 201916 kb
Host smart-3bd101d8-1770-48b4-a9b5-6e9276901e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703371442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.703371442
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.985104682
Short name T116
Test name
Test status
Simulation time 496768324937 ps
CPU time 333.04 seconds
Started Jul 14 07:03:06 PM PDT 24
Finished Jul 14 07:08:40 PM PDT 24
Peak memory 201928 kb
Host smart-c1f5edbd-f578-481a-8728-a314534e13d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985104682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.985104682
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.398886056
Short name T568
Test name
Test status
Simulation time 168096233057 ps
CPU time 368.81 seconds
Started Jul 14 07:03:05 PM PDT 24
Finished Jul 14 07:09:14 PM PDT 24
Peak memory 201852 kb
Host smart-49526caf-2191-444e-9094-6ea31328da91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=398886056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.398886056
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3267966214
Short name T211
Test name
Test status
Simulation time 158072490496 ps
CPU time 354.57 seconds
Started Jul 14 07:02:58 PM PDT 24
Finished Jul 14 07:08:53 PM PDT 24
Peak memory 201956 kb
Host smart-0c78230d-1d68-4271-8b72-70443878819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267966214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3267966214
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3289888622
Short name T785
Test name
Test status
Simulation time 493497971710 ps
CPU time 1021.63 seconds
Started Jul 14 07:03:05 PM PDT 24
Finished Jul 14 07:20:07 PM PDT 24
Peak memory 201876 kb
Host smart-ab5b4846-e0eb-4aa9-9b8b-cb720b14b024
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289888622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3289888622
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1223445200
Short name T184
Test name
Test status
Simulation time 588548141351 ps
CPU time 334.71 seconds
Started Jul 14 07:03:04 PM PDT 24
Finished Jul 14 07:08:40 PM PDT 24
Peak memory 201916 kb
Host smart-0284e7cd-6320-49fd-862c-81b2d4168916
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223445200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1223445200
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3022502759
Short name T403
Test name
Test status
Simulation time 393893416108 ps
CPU time 757.95 seconds
Started Jul 14 07:03:04 PM PDT 24
Finished Jul 14 07:15:43 PM PDT 24
Peak memory 201828 kb
Host smart-88a18838-9693-4f7d-966f-5c957f500265
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022502759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3022502759
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2665058003
Short name T447
Test name
Test status
Simulation time 100037423370 ps
CPU time 309.62 seconds
Started Jul 14 07:03:06 PM PDT 24
Finished Jul 14 07:08:16 PM PDT 24
Peak memory 202196 kb
Host smart-82f22e4b-e17c-46dc-8e01-8cc39ff1412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665058003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2665058003
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3512691424
Short name T381
Test name
Test status
Simulation time 43363325908 ps
CPU time 89.96 seconds
Started Jul 14 07:03:03 PM PDT 24
Finished Jul 14 07:04:34 PM PDT 24
Peak memory 201676 kb
Host smart-b411fc3c-da5d-420e-b736-d886855db62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512691424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3512691424
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1072930664
Short name T602
Test name
Test status
Simulation time 4233814375 ps
CPU time 9.76 seconds
Started Jul 14 07:03:04 PM PDT 24
Finished Jul 14 07:03:14 PM PDT 24
Peak memory 201712 kb
Host smart-4d1b2366-16c8-4a8a-90e6-355944f9b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072930664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1072930664
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.711970133
Short name T455
Test name
Test status
Simulation time 6010357620 ps
CPU time 13.56 seconds
Started Jul 14 07:02:58 PM PDT 24
Finished Jul 14 07:03:12 PM PDT 24
Peak memory 201744 kb
Host smart-2ac415f0-b0fd-433d-8581-39252920fbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711970133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.711970133
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1580558961
Short name T145
Test name
Test status
Simulation time 334137210025 ps
CPU time 777.54 seconds
Started Jul 14 07:03:09 PM PDT 24
Finished Jul 14 07:16:07 PM PDT 24
Peak memory 201948 kb
Host smart-5dbfec96-1a5e-4216-aa81-5da82d7bbffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580558961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1580558961
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4002133596
Short name T18
Test name
Test status
Simulation time 74417610978 ps
CPU time 154.06 seconds
Started Jul 14 07:03:11 PM PDT 24
Finished Jul 14 07:05:46 PM PDT 24
Peak memory 210560 kb
Host smart-67a0b725-ec3d-44ad-9f12-e69286a549ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002133596 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4002133596
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.916427907
Short name T76
Test name
Test status
Simulation time 349702794 ps
CPU time 1.38 seconds
Started Jul 14 07:03:22 PM PDT 24
Finished Jul 14 07:03:23 PM PDT 24
Peak memory 201636 kb
Host smart-04780d26-424a-41a3-85da-dd396f913f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916427907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.916427907
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.521473090
Short name T155
Test name
Test status
Simulation time 181980131884 ps
CPU time 107.76 seconds
Started Jul 14 07:03:14 PM PDT 24
Finished Jul 14 07:05:02 PM PDT 24
Peak memory 201908 kb
Host smart-aef0dbee-6aa4-4bee-b617-76f2004f3609
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521473090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.521473090
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1296856887
Short name T267
Test name
Test status
Simulation time 493412497123 ps
CPU time 170.82 seconds
Started Jul 14 07:03:14 PM PDT 24
Finished Jul 14 07:06:05 PM PDT 24
Peak memory 201812 kb
Host smart-b4a80641-3b27-4065-964a-59c170038059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296856887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1296856887
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1719516169
Short name T298
Test name
Test status
Simulation time 331633333249 ps
CPU time 725.96 seconds
Started Jul 14 07:03:13 PM PDT 24
Finished Jul 14 07:15:20 PM PDT 24
Peak memory 201920 kb
Host smart-19678f87-a9c9-4292-a883-5121f117f340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719516169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1719516169
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.126325003
Short name T562
Test name
Test status
Simulation time 162030721795 ps
CPU time 93.68 seconds
Started Jul 14 07:03:12 PM PDT 24
Finished Jul 14 07:04:46 PM PDT 24
Peak memory 201896 kb
Host smart-d673c2e1-8f6e-4496-969d-9f6d510c74b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=126325003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.126325003
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2803991088
Short name T33
Test name
Test status
Simulation time 482561158891 ps
CPU time 270.02 seconds
Started Jul 14 07:03:09 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 201888 kb
Host smart-d0ca2679-8dd7-42df-81f7-15ac487942a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803991088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2803991088
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4223832004
Short name T532
Test name
Test status
Simulation time 327657600195 ps
CPU time 377.49 seconds
Started Jul 14 07:03:11 PM PDT 24
Finished Jul 14 07:09:29 PM PDT 24
Peak memory 201932 kb
Host smart-2114a4c6-4c47-490a-b387-d3d2f50bbdfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223832004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4223832004
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2524968853
Short name T552
Test name
Test status
Simulation time 623079943805 ps
CPU time 735.45 seconds
Started Jul 14 07:03:15 PM PDT 24
Finished Jul 14 07:15:31 PM PDT 24
Peak memory 201924 kb
Host smart-81f21967-a3d7-499f-ac74-5e27946d3f1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524968853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2524968853
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3618785083
Short name T341
Test name
Test status
Simulation time 609037774383 ps
CPU time 1357.36 seconds
Started Jul 14 07:03:15 PM PDT 24
Finished Jul 14 07:25:52 PM PDT 24
Peak memory 201912 kb
Host smart-1a25704d-7143-4173-9267-90afbd6709a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618785083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3618785083
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.636864309
Short name T54
Test name
Test status
Simulation time 80261756557 ps
CPU time 311 seconds
Started Jul 14 07:03:22 PM PDT 24
Finished Jul 14 07:08:34 PM PDT 24
Peak memory 202216 kb
Host smart-0aeecd7c-58a8-40de-b79e-9c86bb5d25c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636864309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.636864309
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4165178887
Short name T778
Test name
Test status
Simulation time 32378843642 ps
CPU time 67.67 seconds
Started Jul 14 07:03:24 PM PDT 24
Finished Jul 14 07:04:32 PM PDT 24
Peak memory 201724 kb
Host smart-8e40b2a7-44c8-4bd6-b00e-7ee9204ee65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165178887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4165178887
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.4149782086
Short name T352
Test name
Test status
Simulation time 3872809125 ps
CPU time 9.5 seconds
Started Jul 14 07:03:14 PM PDT 24
Finished Jul 14 07:03:24 PM PDT 24
Peak memory 201708 kb
Host smart-2a115a4a-d2a4-4d8e-8fb3-51eb9c91ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149782086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.4149782086
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.522516542
Short name T11
Test name
Test status
Simulation time 5854778892 ps
CPU time 14.18 seconds
Started Jul 14 07:03:10 PM PDT 24
Finished Jul 14 07:03:25 PM PDT 24
Peak memory 201732 kb
Host smart-26fe64c0-564f-4ffb-be2b-d0337576261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522516542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.522516542
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1156894284
Short name T159
Test name
Test status
Simulation time 375386052814 ps
CPU time 1457.75 seconds
Started Jul 14 07:03:24 PM PDT 24
Finished Jul 14 07:27:43 PM PDT 24
Peak memory 218544 kb
Host smart-f3424422-5325-4adc-a05a-1e9c7fb17050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156894284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1156894284
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2115905657
Short name T25
Test name
Test status
Simulation time 90985287448 ps
CPU time 106.62 seconds
Started Jul 14 07:03:22 PM PDT 24
Finished Jul 14 07:05:10 PM PDT 24
Peak memory 218624 kb
Host smart-b22a480f-a9df-4dca-a103-ee3fefc450df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115905657 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2115905657
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4268749778
Short name T695
Test name
Test status
Simulation time 508412958 ps
CPU time 0.77 seconds
Started Jul 14 07:00:43 PM PDT 24
Finished Jul 14 07:00:45 PM PDT 24
Peak memory 201668 kb
Host smart-92380ac2-cc52-442a-944f-de755bc9e090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268749778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4268749778
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1561829813
Short name T480
Test name
Test status
Simulation time 163430045176 ps
CPU time 186.87 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:03:57 PM PDT 24
Peak memory 201900 kb
Host smart-7f30b174-2f5b-46aa-ac55-99bff0ff190c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561829813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1561829813
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.340088847
Short name T621
Test name
Test status
Simulation time 194175206569 ps
CPU time 88.14 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:02:14 PM PDT 24
Peak memory 201928 kb
Host smart-50cdbb7e-fc0a-4706-be09-8010f8cf25fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340088847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.340088847
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2249036369
Short name T558
Test name
Test status
Simulation time 167507864961 ps
CPU time 283.67 seconds
Started Jul 14 07:00:57 PM PDT 24
Finished Jul 14 07:05:46 PM PDT 24
Peak memory 201868 kb
Host smart-e774b428-525e-4f64-b396-e378a1074705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249036369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2249036369
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1431438176
Short name T771
Test name
Test status
Simulation time 167690875308 ps
CPU time 209.95 seconds
Started Jul 14 07:00:31 PM PDT 24
Finished Jul 14 07:04:05 PM PDT 24
Peak memory 201896 kb
Host smart-d71f3485-5383-4897-97ac-e028f1b757ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431438176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1431438176
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2632543838
Short name T162
Test name
Test status
Simulation time 338629289795 ps
CPU time 199.91 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:04:18 PM PDT 24
Peak memory 201968 kb
Host smart-5c09c5e7-d6cb-4a5c-8eb7-cd63ed688721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632543838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2632543838
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.169377912
Short name T616
Test name
Test status
Simulation time 498414642421 ps
CPU time 261.08 seconds
Started Jul 14 07:00:41 PM PDT 24
Finished Jul 14 07:05:04 PM PDT 24
Peak memory 201788 kb
Host smart-964adda4-2f89-4851-814d-33539f92d343
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=169377912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.169377912
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4045204265
Short name T571
Test name
Test status
Simulation time 386541487517 ps
CPU time 220.09 seconds
Started Jul 14 07:00:33 PM PDT 24
Finished Jul 14 07:04:16 PM PDT 24
Peak memory 202092 kb
Host smart-ed71ddd1-4fc8-46ec-bc1a-db214d3f2e75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045204265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4045204265
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2786115592
Short name T497
Test name
Test status
Simulation time 91511815526 ps
CPU time 390.46 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:07:20 PM PDT 24
Peak memory 202200 kb
Host smart-c0f52ff3-d962-4795-b299-7413ce93f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786115592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2786115592
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.378874495
Short name T489
Test name
Test status
Simulation time 31696629611 ps
CPU time 20.09 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:01:13 PM PDT 24
Peak memory 201704 kb
Host smart-77d460d9-de8e-4394-9e97-d74f31481754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378874495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.378874495
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4137835045
Short name T375
Test name
Test status
Simulation time 2800835749 ps
CPU time 7.25 seconds
Started Jul 14 07:00:24 PM PDT 24
Finished Jul 14 07:00:40 PM PDT 24
Peak memory 201768 kb
Host smart-b5b396b7-1296-4470-9cff-ef087e81bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137835045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4137835045
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3001098901
Short name T461
Test name
Test status
Simulation time 5832220369 ps
CPU time 2.28 seconds
Started Jul 14 07:00:36 PM PDT 24
Finished Jul 14 07:00:41 PM PDT 24
Peak memory 201708 kb
Host smart-578e4705-f963-4f5c-a2a3-3585627cb7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001098901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3001098901
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.271125527
Short name T572
Test name
Test status
Simulation time 163203449402 ps
CPU time 188.07 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:03:55 PM PDT 24
Peak memory 201896 kb
Host smart-fc4f2833-1629-48a0-a5ba-02edb53f4ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271125527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.271125527
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2552912710
Short name T40
Test name
Test status
Simulation time 47145589236 ps
CPU time 62.65 seconds
Started Jul 14 07:00:43 PM PDT 24
Finished Jul 14 07:01:47 PM PDT 24
Peak memory 211404 kb
Host smart-23e39145-ed89-4613-9d14-82f6a2a8e1c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552912710 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2552912710
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2445581528
Short name T30
Test name
Test status
Simulation time 324497851 ps
CPU time 1.02 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:00:47 PM PDT 24
Peak memory 201628 kb
Host smart-fb016261-2f5b-4bb7-88cc-aeec98f3ff77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445581528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2445581528
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.614226976
Short name T556
Test name
Test status
Simulation time 166291231427 ps
CPU time 97.16 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:02:25 PM PDT 24
Peak memory 201964 kb
Host smart-314a6f8c-8b91-4255-b58e-fe0517f8371b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614226976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.614226976
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3428585145
Short name T270
Test name
Test status
Simulation time 168945404199 ps
CPU time 44.17 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:01:34 PM PDT 24
Peak memory 201816 kb
Host smart-6572519c-5817-4935-9260-d79b59d7550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428585145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3428585145
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3836596573
Short name T274
Test name
Test status
Simulation time 496749447015 ps
CPU time 282.39 seconds
Started Jul 14 07:00:34 PM PDT 24
Finished Jul 14 07:05:19 PM PDT 24
Peak memory 201888 kb
Host smart-3ffce3ca-e887-44de-bfe2-83305577aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836596573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3836596573
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4270039812
Short name T655
Test name
Test status
Simulation time 489008611670 ps
CPU time 241.13 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:04:51 PM PDT 24
Peak memory 201788 kb
Host smart-6c61d3f3-8bf6-449f-815f-058beec70b94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270039812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4270039812
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1351399523
Short name T90
Test name
Test status
Simulation time 163981803239 ps
CPU time 353.97 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:06:58 PM PDT 24
Peak memory 201956 kb
Host smart-da97c3b0-8a18-4edd-998c-f694f41955f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351399523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1351399523
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3502195294
Short name T34
Test name
Test status
Simulation time 502942078961 ps
CPU time 600.4 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:10:44 PM PDT 24
Peak memory 201960 kb
Host smart-51e6ea65-be65-4f8d-8c13-98cafe31a12d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502195294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3502195294
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.156952773
Short name T577
Test name
Test status
Simulation time 417017970840 ps
CPU time 220.57 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:04:29 PM PDT 24
Peak memory 201868 kb
Host smart-e968095c-4cdb-45d6-855a-73bfc68f3901
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156952773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.156952773
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3744946422
Short name T338
Test name
Test status
Simulation time 105041113403 ps
CPU time 509.76 seconds
Started Jul 14 07:00:40 PM PDT 24
Finished Jul 14 07:09:11 PM PDT 24
Peak memory 202268 kb
Host smart-ffa5b54d-a4fa-4469-8855-b7ccd40fc94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744946422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3744946422
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4162483937
Short name T648
Test name
Test status
Simulation time 44600611970 ps
CPU time 84.58 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:02:12 PM PDT 24
Peak memory 201696 kb
Host smart-74333e22-cce0-4244-a8f4-34feb8650690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162483937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4162483937
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3911826756
Short name T345
Test name
Test status
Simulation time 2572649825 ps
CPU time 6.43 seconds
Started Jul 14 07:00:56 PM PDT 24
Finished Jul 14 07:01:08 PM PDT 24
Peak memory 201676 kb
Host smart-c7fc7b44-83f0-416c-90af-be1a8b59df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911826756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3911826756
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3632841235
Short name T369
Test name
Test status
Simulation time 5570129524 ps
CPU time 4.13 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:00:58 PM PDT 24
Peak memory 201588 kb
Host smart-4c267585-9f3f-447d-9d9a-57511001b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632841235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3632841235
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.477222853
Short name T538
Test name
Test status
Simulation time 170247099024 ps
CPU time 102.6 seconds
Started Jul 14 07:00:41 PM PDT 24
Finished Jul 14 07:02:25 PM PDT 24
Peak memory 201812 kb
Host smart-26730c89-af2b-4022-9563-54c585b2470e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477222853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.477222853
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2290054252
Short name T747
Test name
Test status
Simulation time 21061691732 ps
CPU time 36.02 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:01:28 PM PDT 24
Peak memory 210200 kb
Host smart-72c2475a-b8e7-43f7-9587-5cef3487ac97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290054252 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2290054252
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3979963698
Short name T614
Test name
Test status
Simulation time 464723404 ps
CPU time 0.75 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:00:56 PM PDT 24
Peak memory 201680 kb
Host smart-4a5332e6-7acf-4195-a4e2-62339a13237f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979963698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3979963698
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3134304032
Short name T591
Test name
Test status
Simulation time 519882699121 ps
CPU time 1050.55 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:18:22 PM PDT 24
Peak memory 201936 kb
Host smart-6f3e8d4c-1e02-4aaa-97e1-c45a6a31e85c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134304032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3134304032
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1830255079
Short name T225
Test name
Test status
Simulation time 165628442484 ps
CPU time 102.88 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:02:31 PM PDT 24
Peak memory 201852 kb
Host smart-406e7b01-6862-45a0-8c6a-b260f2339012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830255079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1830255079
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.93212818
Short name T439
Test name
Test status
Simulation time 495634893119 ps
CPU time 1113.22 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:19:24 PM PDT 24
Peak memory 201788 kb
Host smart-086a68c3-8d58-4920-b071-70c91a30f24f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=93212818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_
fixed.93212818
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1756795792
Short name T462
Test name
Test status
Simulation time 487520287935 ps
CPU time 1130.28 seconds
Started Jul 14 07:00:54 PM PDT 24
Finished Jul 14 07:19:50 PM PDT 24
Peak memory 201904 kb
Host smart-3155dc0d-0be9-440b-9ff1-496b1e09f90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756795792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1756795792
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.11073882
Short name T643
Test name
Test status
Simulation time 328950563593 ps
CPU time 743.54 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:13:12 PM PDT 24
Peak memory 201876 kb
Host smart-258945c9-3971-4c02-a818-fadb41634cd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=11073882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.11073882
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2755362432
Short name T180
Test name
Test status
Simulation time 173428428453 ps
CPU time 96.42 seconds
Started Jul 14 07:00:39 PM PDT 24
Finished Jul 14 07:02:17 PM PDT 24
Peak memory 201896 kb
Host smart-91a92b64-5a54-42c8-ae74-1f53863f3d02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755362432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2755362432
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1296234803
Short name T704
Test name
Test status
Simulation time 194154050700 ps
CPU time 456.14 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:08:30 PM PDT 24
Peak memory 201860 kb
Host smart-9e8c0119-81ea-4d67-b563-a6ca8487aaeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296234803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1296234803
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2933924204
Short name T396
Test name
Test status
Simulation time 99185967172 ps
CPU time 317.34 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:06:03 PM PDT 24
Peak memory 202252 kb
Host smart-5f610f0e-8ca6-463b-8536-3e0824af5e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933924204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2933924204
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2065377329
Short name T89
Test name
Test status
Simulation time 21478753138 ps
CPU time 12.24 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:01:03 PM PDT 24
Peak memory 201620 kb
Host smart-f921e288-82ac-45cc-8e44-ad7d84abc644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065377329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2065377329
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2494924097
Short name T583
Test name
Test status
Simulation time 3998718534 ps
CPU time 9.37 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:00:55 PM PDT 24
Peak memory 201720 kb
Host smart-27703273-3d1b-43ab-9dbc-d0b556f701f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494924097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2494924097
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2057694017
Short name T654
Test name
Test status
Simulation time 5844761247 ps
CPU time 4.2 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:00:54 PM PDT 24
Peak memory 201616 kb
Host smart-5f5c0b80-7db5-47ce-955e-acbc84c6af84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057694017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2057694017
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.4070578479
Short name T483
Test name
Test status
Simulation time 107414272689 ps
CPU time 477.27 seconds
Started Jul 14 07:00:49 PM PDT 24
Finished Jul 14 07:08:57 PM PDT 24
Peak memory 218120 kb
Host smart-e42229c1-6ea6-452c-b639-61bb02fe023c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070578479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
4070578479
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3249687216
Short name T20
Test name
Test status
Simulation time 103010525475 ps
CPU time 83.53 seconds
Started Jul 14 07:00:39 PM PDT 24
Finished Jul 14 07:02:04 PM PDT 24
Peak memory 210600 kb
Host smart-c4f79a42-2dc4-411a-8e40-6e5eba6ba029
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249687216 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3249687216
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2351021662
Short name T661
Test name
Test status
Simulation time 437544127 ps
CPU time 0.92 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:00:59 PM PDT 24
Peak memory 201520 kb
Host smart-3aa82e46-c914-4676-8749-720d97f95299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351021662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2351021662
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.569934759
Short name T258
Test name
Test status
Simulation time 519453717189 ps
CPU time 654.41 seconds
Started Jul 14 07:00:43 PM PDT 24
Finished Jul 14 07:11:39 PM PDT 24
Peak memory 202000 kb
Host smart-aa7aae34-da2a-483b-9e24-739895ac3b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569934759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.569934759
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3014914931
Short name T224
Test name
Test status
Simulation time 169009667178 ps
CPU time 101.51 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:02:29 PM PDT 24
Peak memory 201848 kb
Host smart-3c6a388e-c90c-40d8-ae64-9a7a379dcff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014914931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3014914931
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.805862266
Short name T217
Test name
Test status
Simulation time 503813719473 ps
CPU time 727.51 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:12:55 PM PDT 24
Peak memory 201880 kb
Host smart-ff5a553c-ebd6-4e6f-a0b1-55defb53d8e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=805862266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.805862266
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.296494718
Short name T115
Test name
Test status
Simulation time 489456247947 ps
CPU time 1049.97 seconds
Started Jul 14 07:00:44 PM PDT 24
Finished Jul 14 07:18:17 PM PDT 24
Peak memory 201928 kb
Host smart-a3ad1c2c-0c3c-470f-ab9e-6bb1c1dee54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296494718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.296494718
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3733422847
Short name T748
Test name
Test status
Simulation time 490782031260 ps
CPU time 290.03 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:05:40 PM PDT 24
Peak memory 201892 kb
Host smart-df479513-64cd-4967-bfe7-aa2218c09810
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733422847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3733422847
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3045251763
Short name T307
Test name
Test status
Simulation time 180239035463 ps
CPU time 210.05 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:04:18 PM PDT 24
Peak memory 201920 kb
Host smart-238c72b8-538f-4ab6-a546-b8c7db52296e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045251763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3045251763
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.4142297085
Short name T363
Test name
Test status
Simulation time 194181009563 ps
CPU time 241.6 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:04:56 PM PDT 24
Peak memory 201948 kb
Host smart-2dfd0aac-d346-415c-a106-cbe9ce4d3028
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142297085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.4142297085
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.694021293
Short name T632
Test name
Test status
Simulation time 102510728872 ps
CPU time 366.85 seconds
Started Jul 14 07:00:40 PM PDT 24
Finished Jul 14 07:06:48 PM PDT 24
Peak memory 202172 kb
Host smart-e633e970-27bd-431c-bd12-84560e40b8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694021293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.694021293
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3664397482
Short name T421
Test name
Test status
Simulation time 25662409439 ps
CPU time 11.26 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:01:01 PM PDT 24
Peak memory 201724 kb
Host smart-70a8db6b-fe52-45ae-907d-bf912edd71a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664397482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3664397482
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.470297304
Short name T357
Test name
Test status
Simulation time 3951653477 ps
CPU time 5.28 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:00:55 PM PDT 24
Peak memory 201716 kb
Host smart-ba94ad42-a15f-4a08-ac23-4c8f76050c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470297304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.470297304
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.179622598
Short name T119
Test name
Test status
Simulation time 6127344913 ps
CPU time 4.09 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:00:56 PM PDT 24
Peak memory 201708 kb
Host smart-a296ef03-5eed-4b7c-abb3-a71c23b8b512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179622598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.179622598
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2712141298
Short name T673
Test name
Test status
Simulation time 344503199376 ps
CPU time 799.9 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:14:09 PM PDT 24
Peak memory 201868 kb
Host smart-ce819414-788f-4e8a-b546-dd3e2d432208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712141298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2712141298
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3426458414
Short name T667
Test name
Test status
Simulation time 103535880793 ps
CPU time 67.22 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:01:51 PM PDT 24
Peak memory 218348 kb
Host smart-be8ead67-e29b-44bf-b480-245888b2ec6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426458414 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3426458414
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.4169228270
Short name T774
Test name
Test status
Simulation time 401914654 ps
CPU time 0.75 seconds
Started Jul 14 07:00:51 PM PDT 24
Finished Jul 14 07:00:57 PM PDT 24
Peak memory 201576 kb
Host smart-b1e086ab-8ef9-44ba-9b7d-cba6af80138a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169228270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.4169228270
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1129555444
Short name T320
Test name
Test status
Simulation time 543445807215 ps
CPU time 221.57 seconds
Started Jul 14 07:00:52 PM PDT 24
Finished Jul 14 07:04:39 PM PDT 24
Peak memory 201816 kb
Host smart-c9e7cde0-b76e-4e2e-bd2c-fc833fffbdcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129555444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1129555444
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2773491735
Short name T705
Test name
Test status
Simulation time 515632734659 ps
CPU time 130.6 seconds
Started Jul 14 07:00:41 PM PDT 24
Finished Jul 14 07:02:53 PM PDT 24
Peak memory 201884 kb
Host smart-f16ae3d2-156a-458e-87f5-52aa47f2bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773491735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2773491735
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3615482860
Short name T277
Test name
Test status
Simulation time 493930685117 ps
CPU time 1208.32 seconds
Started Jul 14 07:00:45 PM PDT 24
Finished Jul 14 07:20:57 PM PDT 24
Peak memory 201908 kb
Host smart-d61b6270-5eb2-47ab-b0bc-fea82823a25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615482860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3615482860
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1710488848
Short name T742
Test name
Test status
Simulation time 487599974874 ps
CPU time 556.42 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:10:11 PM PDT 24
Peak memory 201796 kb
Host smart-883031c4-d716-46ef-8c23-66f12d98934b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710488848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1710488848
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.153238984
Short name T165
Test name
Test status
Simulation time 491583798725 ps
CPU time 1061.19 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:18:31 PM PDT 24
Peak memory 201976 kb
Host smart-a4a675fb-68c2-4716-a3fa-32f9689ca35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153238984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.153238984
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2140973948
Short name T452
Test name
Test status
Simulation time 329502188383 ps
CPU time 664.93 seconds
Started Jul 14 07:00:42 PM PDT 24
Finished Jul 14 07:11:48 PM PDT 24
Peak memory 201964 kb
Host smart-5860a451-f882-4324-a7c1-5542e50bcf15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140973948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2140973948
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3236769264
Short name T708
Test name
Test status
Simulation time 174445363902 ps
CPU time 54.67 seconds
Started Jul 14 07:00:46 PM PDT 24
Finished Jul 14 07:01:43 PM PDT 24
Peak memory 201908 kb
Host smart-638fc91b-3e89-42bd-bc80-1d5a2aa75e33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236769264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3236769264
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.98201241
Short name T85
Test name
Test status
Simulation time 405327716842 ps
CPU time 987.63 seconds
Started Jul 14 07:00:48 PM PDT 24
Finished Jul 14 07:17:20 PM PDT 24
Peak memory 201968 kb
Host smart-92d4a306-ffd7-4f24-bf69-a4b672b70b51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98201241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.98201241
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4170180193
Short name T336
Test name
Test status
Simulation time 132468734253 ps
CPU time 416.74 seconds
Started Jul 14 07:00:47 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 202220 kb
Host smart-55c843ee-3eef-4b4e-b01b-c9d3dcbe0c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170180193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4170180193
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2076225389
Short name T520
Test name
Test status
Simulation time 35537337197 ps
CPU time 19.5 seconds
Started Jul 14 07:00:53 PM PDT 24
Finished Jul 14 07:01:18 PM PDT 24
Peak memory 201696 kb
Host smart-15e38dd5-e4e1-4906-8f66-d499964b6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076225389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2076225389
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3391433256
Short name T735
Test name
Test status
Simulation time 3386121353 ps
CPU time 2.66 seconds
Started Jul 14 07:00:50 PM PDT 24
Finished Jul 14 07:00:57 PM PDT 24
Peak memory 201712 kb
Host smart-efc68dc9-86c1-40d1-aac1-5784f00cee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391433256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3391433256
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.221520355
Short name T794
Test name
Test status
Simulation time 5652571668 ps
CPU time 4.1 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:01:08 PM PDT 24
Peak memory 201720 kb
Host smart-11c612cc-3f29-4145-a212-1204ab13018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221520355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.221520355
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3933989596
Short name T283
Test name
Test status
Simulation time 654697684646 ps
CPU time 1100.31 seconds
Started Jul 14 07:01:12 PM PDT 24
Finished Jul 14 07:19:35 PM PDT 24
Peak memory 201880 kb
Host smart-91beb985-6ebe-46fe-8ab1-78af37fdc14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933989596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3933989596
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2853907835
Short name T611
Test name
Test status
Simulation time 1368779958344 ps
CPU time 455.86 seconds
Started Jul 14 07:00:59 PM PDT 24
Finished Jul 14 07:08:40 PM PDT 24
Peak memory 210548 kb
Host smart-ae34379d-c933-4434-877e-7851cb712aa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853907835 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2853907835
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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