Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7060	1			T3	63		T7	53		T8	20
testmodes[AdcCtrlTestmodeNormal]	5714	1			T3	48		T5	1		T6	2
testmodes[AdcCtrlTestmodeLowpower]	5796	1			T1	2		T2	3		T3	51
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3780	1			T3	35		T7	24		T8	8
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1812	1			T3	18		T7	16		T8	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1354	1			T3	10		T7	13		T8	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1819	1			T3	13		T7	20		T8	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2100	1			T3	19		T6	1		T7	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1451	1			T3	15		T7	2		T8	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1343	1			T3	15		T7	9		T8	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1475	1			T3	11		T7	5		T8	5
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2737	1			T1	1		T2	2		T3	25