Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23119

1

T1

7

T2

11

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

4017

1

T1

14

T2

30

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20832

1

T1

21

T2

11

T3

162

auto[1]

6304

1

T2

30

T4

44

T5

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T196	5		-	-		-	-
values[0]	87	1			T197	4		T80	22		T157	15
values[1]	819	1			T13	4		T29	21		T122	4
values[2]	853	1			T29	20		T128	8		T129	5
values[3]	830	1			T1	14		T3	1		T47	10
values[4]	686	1			T2	18		T8	7		T35	9
values[5]	824	1			T48	37		T49	23		T127	12
values[6]	632	1			T8	18		T43	20		T47	26
values[7]	625	1			T1	7		T2	12		T154	5
values[8]	2944	1			T2	11		T4	19		T5	8
values[9]	1224	1			T4	50		T10	1		T127	20
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	988	1			T13	4		T29	21		T122	4
values[1]	951	1			T3	1		T47	10		T29	36
values[2]	788	1			T1	14		T8	7		T172	3
values[3]	704	1			T35	9		T49	10		T154	9
values[4]	773	1			T2	18		T47	26		T48	37
values[5]	708	1			T1	7		T2	12		T8	18
values[6]	2958	1			T4	19		T5	8		T6	2
values[7]	636	1			T2	11		T10	1		T48	20
values[8]	811	1			T4	50		T127	20		T124	1
values[9]	208	1			T10	1		T37	6		T181	1
minimum	17611	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	3		T198	1		T51	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T29	13		T122	1		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T141	1		T138	13		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	1		T47	1		T29	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	6		T172	3		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	14		T199	21		T143	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T154	9		T126	15		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T35	7		T49	5		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T47	14		T48	23		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	18		T49	12		T127	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	7		T8	9		T43	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	12		T123	1		T39	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T4	4		T5	1		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T43	5		T56	8		T126	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	11		T10	1		T48	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	2		T130	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T124	1		T51	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T4	26		T127	20		T133	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T181	1		T174	11		T200	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T10	1		T37	5		T201	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17499	1			T3	161		T7	122		T8	89
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T198	15		T51	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T29	8		T122	3		T126	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T141	12		T138	11		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T47	9		T29	17		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	1		T202	10		T81	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T32	4		T196	26		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T126	8		T204	2		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T35	2		T49	5		T140	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T47	12		T48	14		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T49	11		T205	12		T206	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	9		T43	6		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	9		T40	1		T188	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T4	15		T5	7		T7	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T43	10		T56	9		T126	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T48	15		T132	2		T175	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	2		T79	2		T207	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T141	10		T132	2		T206	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	24		T133	14		T188	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T196	4		T20	9		T208	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T37	1		T201	8		T179	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T8	2		T37	1		T131	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T196	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T209	1		T210	10		T211	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T197	4		T80	12		T157	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	3		T198	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T29	13		T122	1		T212	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T51	12		T141	1		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	10		T128	5		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	2		T40	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	14		T3	1		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	6		T154	9		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	18		T35	7		T49	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T48	23		T49	10		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T127	12		T172	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T8	9		T43	14		T47	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	12		T123	1		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	7		T154	5		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	12		T56	8		T126	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T2	11		T4	4		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	5		T130	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T124	1		T51	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	454	1			T4	26		T10	1		T127	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T196	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T209	9		T210	3		T211	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T80	10		T157	8		T213	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	1		T198	15		T131	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T29	8		T122	3		T212	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T51	7		T141	12		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	10		T128	3		T214	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T138	11		T81	11		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T47	9		T29	7		T214	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	1		T126	8		T202	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T35	2		T49	5		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T48	14		T49	13		T56	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T140	1		T206	4		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	9		T43	6		T47	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T49	11		T40	1		T188	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T147	10		T132	2		T204	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T56	9		T126	13		T39	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T4	15		T5	7		T7	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T43	10		T207	3		T18	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T141	10		T132	2		T206	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T4	24		T13	2		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	3		T198	16		T51	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T29	9		T122	4		T126	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T141	13		T138	12		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T3	1		T47	10		T29	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	5		T172	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T199	2		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T154	1		T126	9		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T35	6		T49	6		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T47	13		T48	15		T49	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	1		T49	12		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T8	12		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T123	1		T39	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T4	16		T5	8		T6	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T43	11		T56	10		T126	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T10	1		T48	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	4		T130	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T124	1		T51	1		T141	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	26		T127	1		T133	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T181	1		T174	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T10	1		T37	6		T201	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17611	1			T3	161		T7	122		T8	91
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	1		T51	11		T143	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T29	12		T126	1		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T138	12		T156	13		T203	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T29	17		T128	4		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	2		T172	2		T202	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	13		T199	19		T143	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T154	8		T126	14		T204	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T35	3		T49	4		T215	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T47	13		T48	22		T49	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	17		T49	11		T127	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	6		T8	6		T43	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	11		T39	10		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T4	3		T7	13		T154	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	4		T56	7		T126	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	10		T48	4		T135	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T144	11		T139	5		T207	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T174	4		T132	12		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T4	24		T127	19		T133	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T174	10		T200	11		T20	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T201	11		T217	17		T218	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T196	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T209	10		T210	4		T211	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T197	1		T80	11		T157	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	3		T198	16		T131	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T29	9		T122	4		T212	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T51	8		T141	13		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	11		T128	4		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	2		T40	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	1		T3	1		T47	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	5		T154	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T35	6		T49	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T48	15		T49	14		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	1		T172	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	12		T43	7		T47	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	12		T123	1		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	1		T154	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T56	10		T126	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T2	1		T4	16		T5	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T43	11		T130	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T124	1		T51	1		T141	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T4	26		T10	1		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T210	9		T211	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T197	3		T80	11		T157	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	1		T139	18		T15	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T29	12		T212	10		T51	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T51	11		T143	12		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	9		T128	4		T129	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	12		T81	8		T219	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	13		T29	8		T199	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	2		T154	8		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	17		T35	3		T49	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T48	22		T49	9		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T127	11		T85	2		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T8	6		T43	13		T47	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	11		T188	11		T204	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	6		T154	4		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	11		T56	7		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T2	10		T4	3		T7	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	4		T144	11		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T174	14		T132	12		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T4	24		T127	19		T133	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23016

1

T2

30

T3

162

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

4120

1

T1

21

T2

11

T4

50

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20470

1

T1

21

T2

11

T3

161

auto[1]

6666

1

T2

30

T3

1

T4

69

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	55	1			T214	32		T221	23		-	-
values[0]	71	1			T168	33		T152	10		T222	1
values[1]	813	1			T1	21		T2	12		T4	19
values[2]	864	1			T4	25		T48	37		T30	1
values[3]	947	1			T43	15		T13	4		T123	1
values[4]	658	1			T4	25		T8	18		T49	23
values[5]	2893	1			T5	8		T6	2		T11	8
values[6]	605	1			T7	34		T35	9		T47	10
values[7]	714	1			T2	11		T43	20		T125	19
values[8]	699	1			T2	18		T10	2		T172	1
values[9]	1210	1			T3	1		T47	26		T154	9
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1092	1			T1	21		T4	19		T8	7
values[1]	898	1			T4	25		T43	15		T48	37
values[2]	916	1			T8	18		T172	1		T128	8
values[3]	2771	1			T4	25		T5	8		T6	2
values[4]	684	1			T7	34		T47	10		T49	23
values[5]	662	1			T43	20		T35	9		T49	23
values[6]	617	1			T2	11		T10	1		T172	1
values[7]	762	1			T2	18		T10	1		T125	20
values[8]	820	1			T3	1		T47	26		T154	9
values[9]	275	1			T129	5		T131	4		T39	1
minimum	17639	1			T2	12		T3	161		T7	122

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T4	4		T127	12		T154	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T1	21		T8	6		T49	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	23		T212	11		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T4	12		T43	5		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T8	9		T172	1		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T129	1		T130	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T5	1		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	14		T13	3		T29	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T47	1		T49	10		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	14		T126	2		T132	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	7		T49	12		T127	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	14		T126	14		T141	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T51	1		T202	3		T175	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	11		T10	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	18		T125	1		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	1		T125	1		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T56	4		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	14		T154	9		T199	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T131	1		T39	1		T220	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T129	5		T137	14		T223	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17515	1			T2	12		T3	161		T7	122
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	15		T27	11		T29	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T49	5		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	14		T212	10		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	13		T43	10		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	9		T128	3		T39	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T205	12		T188	10		T204	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T5	7		T11	7		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	11		T13	1		T29	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T47	9		T49	13		T122	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	20		T126	8		T132	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T35	2		T49	11		T224	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T43	6		T126	13		T141	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T202	10		T175	7		T81	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T198	15		T225	10		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T125	18		T126	8		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T226	2		T224	8		T81	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T56	4		T141	3		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	12		T156	21		T79	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T131	3		T227	10		T228	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T223	10		T196	11		T229	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	2		T48	15		T37	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T214	16		T221	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T161	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T168	16		T152	10		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	12		T4	4		T48	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	21		T8	6		T49	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T48	23		T128	5		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	12		T30	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	2		T172	1		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T43	5		T123	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	9		T49	10		T39	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	14		T29	9		T56	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T5	1		T6	2		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	3		T29	13		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T35	7		T47	1		T127	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	14		T198	1		T126	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T125	1		T51	1		T202	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	11		T43	14		T141	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	18		T126	15		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	2		T172	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T3	1		T56	4		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T47	14		T154	9		T129	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T214	16		T221	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T168	17		T230	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	15		T48	15		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	1		T49	5		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	14		T128	3		T14	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	13		T132	2		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	2		T212	10		T231	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T43	10		T51	3		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	9		T49	13		T39	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	11		T29	7		T56	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T5	7		T11	7		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T29	8		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T35	2		T47	9		T232	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	20		T198	15		T126	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T125	18		T202	10		T175	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	6		T141	22		T147	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T126	8		T157	8		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T226	2		T81	8		T86	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T56	4		T131	3		T141	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T47	12		T156	21		T224	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1