Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23380

1

T1

7

T2

23

T3

162

auto[ADC_CTRL_FILTER_COND_OUT]

3756

1

T1

14

T2

18

T4

69

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21119

1

T2

41

T3

161

T4

25

auto[1]

6017

1

T1

21

T3

1

T4

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	42	1			T51	6		T188	21		T281	8
values[0]	45	1			T56	17		T37	6		T238	13
values[1]	897	1			T4	50		T49	10		T128	8
values[2]	843	1			T3	1		T35	9		T154	3
values[3]	689	1			T8	18		T49	23		T127	20
values[4]	678	1			T10	1		T124	1		T130	1
values[5]	2810	1			T5	8		T6	2		T7	34
values[6]	809	1			T1	7		T2	29		T8	7
values[7]	575	1			T129	1		T126	23		T147	11
values[8]	656	1			T1	14		T43	35		T48	37
values[9]	1485	1			T2	12		T4	19		T10	1
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1245	1			T3	1		T4	50		T49	10
values[1]	792	1			T35	9		T49	23		T127	20
values[2]	553	1			T8	18		T154	9		T30	1
values[3]	2883	1			T5	8		T6	2		T10	1
values[4]	743	1			T7	34		T48	20		T29	20
values[5]	608	1			T2	11		T8	7		T13	4
values[6]	657	1			T1	7		T2	18		T43	20
values[7]	637	1			T1	14		T43	15		T47	10
values[8]	1106	1			T2	12		T10	1		T49	23
values[9]	290	1			T4	19		T47	26		T141	11
minimum	17622	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T3	1		T154	3		T27	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T4	26		T49	5		T128	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T49	12		T122	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	7		T127	20		T29	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	9		T56	4		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T154	9		T30	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T5	1		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	1		T172	3		T126	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T172	1		T125	1		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	14		T48	5		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	11		T8	6		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	2		T126	15		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	7		T147	2		T225	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	18		T43	14		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T43	5		T48	23		T127	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	14		T47	1		T205	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	12		T10	1		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T49	10		T13	3		T29	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T141	1		T188	11		T81	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T4	4		T47	14		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17499	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T143	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T27	11		T56	9		T51	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T4	24		T49	5		T128	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T49	11		T122	3		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T35	2		T29	8		T141	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	9		T56	4		T131	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T216	10		T149	10		T269	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T5	7		T11	7		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T126	8		T39	9		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T125	18		T40	1		T214	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	20		T48	15		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	1		T198	15		T232	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T13	2		T126	8		T202	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T147	10		T225	10		T80	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T43	6		T175	5		T81	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T43	10		T48	14		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T47	9		T205	12		T275	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T51	3		T132	2		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T49	13		T13	1		T29	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T141	10		T188	10		T81	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T4	15		T47	12		T147	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T51	3		T188	11		T281	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T282	1		T97	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T56	8		T238	13		T283	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T37	5		T162	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T51	12		T126	14		T204	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	26		T49	5		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T3	1		T154	3		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	7		T29	13		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	9		T49	12		T56	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T127	20		T154	9		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T124	1		T130	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	1		T126	2		T39	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1479	1			T5	1		T6	2		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	14		T48	5		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	7		T2	11		T8	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	18		T13	2		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T147	1		T225	8		T143	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T129	1		T126	15		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	5		T48	23		T154	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	14		T43	14		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T2	12		T10	1		T127	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	462	1			T4	4		T47	15		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T51	3		T188	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T282	3		T97	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T56	9		T283	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T37	1		T162	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T51	7		T126	13		T204	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T4	24		T49	5		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T27	11		T122	3		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T35	2		T29	8		T141	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	9		T49	11		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T132	2		T216	10		T196	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T225	10		T206	3		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T126	8		T39	9		T84	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T5	7		T11	7		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	20		T48	15		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	1		T198	15		T80	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	2		T202	2		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T147	10		T225	10		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T126	8		T81	11		T284	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	10		T48	14		T197	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	6		T205	12		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T141	10		T132	2		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T4	15		T47	21		T49	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T3	1		T154	1		T27	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	435	1			T4	26		T49	6		T128	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T49	12		T122	4		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T35	6		T127	1		T29	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	12		T56	5		T131	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T154	1		T30	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T5	8		T6	2		T11	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	1		T172	1		T126	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T172	1		T125	19		T40	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T7	21		T48	16		T29	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T8	5		T198	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	4		T126	9		T202	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T147	12		T225	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	1		T43	7		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	11		T48	15		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T47	10		T205	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T10	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T49	14		T13	3		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T141	11		T188	11		T81	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T4	16		T47	13		T147	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17608	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T143	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T154	2		T27	11		T56	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T4	24		T49	4		T128	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T49	11		T212	10		T197	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T35	3		T127	19		T29	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	6		T56	3		T214	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T154	8		T268	14		T235	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T24	30		T25	34		T234	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T172	2		T126	1		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T214	7		T207	3		T285	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	13		T48	4		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	10		T8	2		T143	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T126	14		T85	2		T18	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	6		T225	7		T80	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	17		T43	13		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	4		T48	22		T127	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	13		T205	9		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	11		T129	4		T51	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T49	9		T13	1		T29	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T188	10		T81	9		T263	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T4	3		T47	13		T257	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T143	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T51	4		T188	11		T281	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T282	4		T97	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T56	10		T238	1		T283	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T37	6		T162	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T51	8		T126	14		T204	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T4	26		T49	6		T128	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T3	1		T154	1		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	6		T29	9		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	12		T49	12		T56	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	1		T154	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T124	1		T130	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	1		T126	9		T39	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T5	8		T6	2		T11	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	21		T48	16		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T2	1		T8	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	1		T13	4		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T147	11		T225	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T129	1		T126	9		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T43	11		T48	15		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T43	7		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T2	1		T10	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	456	1			T4	16		T47	23		T49	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T51	2		T188	10		T281	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T97	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T56	7		T238	12		T283	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T51	11		T126	13		T204	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	24		T49	4		T128	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T154	2		T27	11		T197	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	3		T29	12		T138	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	6		T49	11		T56	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T127	19		T154	8		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T225	10		T80	11		T149	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T126	1		T39	10		T199	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T24	30		T25	34		T234	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	13		T48	4		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	6		T2	10		T8	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	17		T156	7		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T225	7		T143	19		T247	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T126	14		T199	11		T137	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	4		T48	22		T154	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	13		T43	13		T205	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T2	11		T127	11		T129	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T4	3		T47	13		T49	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27