Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23388

1

T1

21

T2

12

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3748

1

T2

29

T3

1

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20701

1

T1

21

T2

12

T3

160

auto[1]

6435

1

T2

29

T3

2

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	632	1			T3	2		T7	1		T8	1
values[0]	53	1			T269	2		T229	11		T256	12
values[1]	743	1			T4	25		T47	10		T48	20
values[2]	2884	1			T1	14		T2	12		T5	8
values[3]	745	1			T35	9		T49	23		T154	9
values[4]	558	1			T7	34		T43	20		T37	6
values[5]	814	1			T29	16		T129	5		T126	10
values[6]	634	1			T3	1		T27	23		T122	4
values[7]	691	1			T1	7		T4	19		T13	8
values[8]	804	1			T4	25		T8	18		T10	1
values[9]	1368	1			T2	29		T8	7		T10	1
minimum	17210	1			T3	159		T7	121		T8	90

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	683	1			T2	12		T4	25		T47	10
values[1]	2980	1			T1	14		T5	8		T6	2
values[2]	710	1			T35	9		T56	17		T38	2
values[3]	547	1			T7	34		T43	20		T29	16
values[4]	799	1			T126	10		T131	14		T147	9
values[5]	589	1			T1	7		T3	1		T27	23
values[6]	813	1			T4	19		T8	18		T13	8
values[7]	911	1			T2	11		T4	25		T10	1
values[8]	1142	1			T2	18		T8	7		T10	1
values[9]	142	1			T124	1		T155	1		T137	14
minimum	17820	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	12		T4	12		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	1		T123	1		T172	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T1	14		T5	1		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	13		T130	1		T174	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T182	1		T197	16		T226	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T35	7		T56	8		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	14		T37	5		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	14		T29	9		T139	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T126	2		T131	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T147	1		T155	1		T202	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	7		T27	12		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T134	1		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	4		T8	9		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	5		T39	1		T197	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	1		T154	5		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	11		T4	14		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	6		T49	5		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T2	18		T10	1		T47	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T124	1		T139	6		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T155	1		T137	14		T196	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17549	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T56	4		T225	8		T138	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	13		T48	15		T125	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T47	9		T214	7		T196	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T5	7		T11	7		T43	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	8		T216	10		T81	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T197	15		T226	2		T82	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	2		T56	9		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	20		T37	1		T198	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T43	6		T29	7		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T126	8		T131	13		T202	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T147	8		T202	10		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T27	11		T122	3		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T197	16		T224	8		T203	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	15		T8	9		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	3		T175	5		T82	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T126	8		T131	3		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	11		T49	13		T212	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T49	5		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T47	12		T48	14		T214	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T276	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T196	11		T203	2		T233	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	2		T29	10		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T56	4		T225	10		T138	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	513	1			T3	2		T7	1		T8	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T155	1		T286	11		T167	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T229	4		T256	12		T258	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	12		T48	5		T127	32
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T47	1		T123	1		T172	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T1	14		T2	12		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	13		T130	1		T139	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T49	12		T154	9		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T35	7		T56	8		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	14		T37	5		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T43	14		T141	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T129	5		T126	2		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T29	9		T147	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T27	12		T122	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T145	1		T197	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	7		T4	4		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	5		T134	1		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	9		T10	1		T154	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	14		T124	1		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T8	6		T124	2		T51	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	436	1			T2	29		T10	1		T47	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17101	1			T3	159		T7	121		T8	88
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T49	5		T275	8		T192	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T286	10		T167	9		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T229	7		T258	4		T287	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	13		T48	15		T29	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	9		T56	4		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T5	7		T11	7		T43	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	8		T196	4		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T49	11		T197	15		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	2		T56	9		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T7	20		T37	1		T198	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	6		T141	12		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T126	8		T188	10		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	7		T147	8		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T27	11		T122	3		T131	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T145	10		T197	16		T224	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	15		T141	3		T39	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	3		T175	5		T82	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	9		T131	3		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	11		T212	10		T51	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T8	1		T51	3		T126	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T47	12		T48	14		T49	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	1		T4	14		T48	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	10		T123	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T1	1		T5	8		T6	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T29	9		T130	1		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T182	1		T197	16		T226	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T35	6		T56	10		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	21		T37	6		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T43	7		T29	8		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T126	9		T131	14		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T147	9		T155	1		T202	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T27	12		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	1		T134	1		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T4	16		T8	12		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	7		T39	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T10	1		T154	1		T126	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	1		T4	12		T49	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	5		T49	6		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T2	1		T10	1		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T124	1		T139	1		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T155	1		T137	1		T196	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17653	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T56	5		T225	11		T138	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	11		T4	11		T48	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T172	2		T135	6		T214	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T1	13		T43	4		T49	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	12		T174	10		T139	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T197	15		T226	10		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T35	3		T56	7		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	13		T129	4		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T43	13		T29	8		T139	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T126	1		T188	11		T175	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T202	2		T253	11		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	6		T27	11		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T197	10		T224	3		T203	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	3		T8	6		T39	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	1		T197	3		T175	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T154	4		T126	14		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	10		T4	13		T49	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	2		T49	4		T51	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	17		T47	13		T48	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T139	5		T288	26		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T137	13		T203	13		T251	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T127	30		T29	9		T229	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T56	3		T225	7		T138	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	451	1			T3	2		T7	1		T8	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T155	1		T286	11		T167	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T229	9		T256	1		T258	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	14		T48	16		T127	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	10		T123	1		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	1		T2	1		T5	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T29	9		T130	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	12		T154	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T35	6		T56	10		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	21		T37	6		T198	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	7		T141	13		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T129	1		T126	9		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T29	8		T147	9		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T27	12		T122	4		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	1		T145	11		T197	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T4	16		T141	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	7		T134	1		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	12		T10	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	12		T124	1		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T8	5		T124	2		T51	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	444	1			T2	2		T10	1		T47	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T3	159		T7	121		T8	90
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T49	4		T174	4		T139	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T286	10		T251	8		T289	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T229	2		T256	11		T258	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	11		T48	4		T127	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T172	2		T56	3		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T1	13		T2	11		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	12		T139	14		T200	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	11		T154	8		T197	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T35	3		T56	7		T174	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T7	13		T224	4		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T43	13		T143	13		T139	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	4		T126	1		T188	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	8		T202	2		T253	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T27	11		T132	12		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T197	10		T224	3		T203	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	6		T4	3		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T197	3		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	6		T154	4		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	13		T212	10		T51	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	2		T51	2		T126	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T2	27		T47	13		T48	22

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27