Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23286

1

T1

21

T2

23

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3850

1

T2

18

T3

1

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20815

1

T2

11

T3

162

T7

156

auto[1]

6321

1

T1

21

T2

30

T4

69

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	295	1			T49	10		T27	23		T51	1
values[0]	31	1			T129	5		T242	5		T241	1
values[1]	606	1			T10	1		T47	10		T13	4
values[2]	1000	1			T7	34		T8	18		T43	20
values[3]	804	1			T1	14		T43	15		T35	9
values[4]	2700	1			T2	18		T4	19		T5	8
values[5]	662	1			T2	12		T4	25		T127	20
values[6]	776	1			T4	25		T10	1		T48	20
values[7]	972	1			T1	7		T3	1		T8	7
values[8]	757	1			T51	19		T126	23		T147	9
values[9]	926	1			T2	11		T47	26		T154	5
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	746	1			T7	34		T10	1		T43	20
values[1]	827	1			T123	1		T172	1		T125	20
values[2]	780	1			T1	14		T4	19		T8	18
values[3]	2697	1			T2	18		T5	8		T6	2
values[4]	788	1			T2	12		T4	25		T48	20
values[5]	657	1			T1	7		T4	25		T10	1
values[6]	1074	1			T3	1		T8	7		T48	37
values[7]	702	1			T212	21		T51	25		T126	23
values[8]	884	1			T47	26		T49	10		T154	5
values[9]	141	1			T2	11		T130	1		T156	16
minimum	17840	1			T3	161		T7	122		T8	91

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	14		T10	1		T43	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T47	1		T13	3		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T172	1		T125	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T123	1		T125	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	14		T4	4		T8	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T49	10		T155	1		T143	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T5	1		T6	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	18		T29	9		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	12		T154	3		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	14		T48	5		T29	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	7		T4	12		T174	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	1		T128	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T8	6		T49	12		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T3	1		T48	23		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T212	11		T51	3		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T51	12		T199	12		T214	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	5		T198	1		T126	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T47	14		T154	5		T27	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T2	11		T130	1		T18	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T156	8		T196	1		T221	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T231	18		T144	12		T209	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	20		T43	6		T224	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	9		T13	1		T140	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T147	10		T133	14		T202	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T125	18		T141	10		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	15		T8	9		T43	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	13		T175	12		T240	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T5	7		T11	7		T35	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T29	7		T122	3		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	2		T29	10		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	11		T48	15		T29	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	13		T216	10		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T128	3		T131	13		T132	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T49	11		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T48	14		T197	16		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T212	10		T51	3		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T51	7		T214	17		T206	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	5		T198	15		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T47	12		T27	11		T56	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T18	4		T235	6		T290	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T156	8		T196	11		T221	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	2		T37	1		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T231	15		T209	10		T242	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T49	5		T81	10		T207	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T27	12		T51	1		T204	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T129	5		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T242	1		T243	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	1		T188	11		T199	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T47	1		T13	3		T231	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	14		T8	9		T43	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T123	1		T125	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	14		T43	5		T35	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T49	10		T155	1		T137	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T4	4		T5	1		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	18		T122	1		T172	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	12		T127	20		T154	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	14		T29	22		T135	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	12		T13	2		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	1		T48	5		T128	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	7		T8	6		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T3	1		T48	23		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T126	15		T147	1		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	12		T155	1		T199	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	11		T130	1		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T47	14		T154	5		T56	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T49	5		T81	8		T207	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T27	11		T204	2		T221	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T242	4		T243	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T188	10		T223	10		T168	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	9		T13	1		T231	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	20		T8	9		T43	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T125	18		T141	10		T81	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T43	10		T35	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T49	13		T145	11		T175	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T4	15		T5	7		T11	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T122	3		T56	4		T202	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T204	10		T80	10		T86	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T4	11		T29	15		T141	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	13		T13	2		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	15		T128	3		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	1		T49	11		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	14		T225	10		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T126	8		T147	8		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T51	7		T214	10		T206	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T212	10		T198	15		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T47	12		T56	9		T126	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	21		T10	1		T43	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T47	10		T13	3		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T172	1		T125	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T123	1		T125	19		T141	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	1		T4	16		T8	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	14		T155	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T5	8		T6	2		T11	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T2	1		T29	8		T122	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	1		T154	1		T13	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	12		T48	16		T29	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T4	14		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T128	4		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	5		T49	12		T141	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	1		T48	15		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T212	11		T51	4		T126	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	8		T199	1		T214	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T49	6		T198	16		T126	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T47	13		T154	1		T27	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T2	1		T130	1		T18	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T156	9		T196	12		T221	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17644	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T231	16		T144	1		T209	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	13		T43	13		T154	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	1		T175	8		T201	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T174	10		T133	13		T197	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T139	18		T81	8		T85	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	13		T4	3		T8	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T49	9		T143	19		T137	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T35	3		T127	19		T24	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	17		T29	8		T172	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	11		T154	2		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	13		T48	4		T29	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	6		T4	11		T174	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T128	4		T132	12		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T8	2		T49	11		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T48	22		T197	10		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T212	10		T51	2		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T51	11		T199	11		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T49	4		T126	13		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T47	13		T154	4		T27	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T2	10		T18	6		T235	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T156	7		T221	8		T157	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T129	4		T188	10		T220	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T231	17		T144	11		T291	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T49	6		T81	9		T207	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T27	12		T51	1		T204	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T129	1		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T242	5		T243	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T10	1		T188	11		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T47	10		T13	3		T231	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	21		T8	12		T43	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T123	1		T125	19		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T43	11		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T49	14		T155	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T4	16		T5	8		T6	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T2	1		T122	4		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T127	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	12		T29	17		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	14		T13	4		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	1		T48	16		T128	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T8	5		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T3	1		T48	15		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T126	9		T147	9		T132	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T51	8		T155	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	1		T130	1		T212	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T47	13		T154	1		T56	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T49	4		T81	9		T207	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T27	11		T204	13		T221	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T129	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T243	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T188	10		T199	8		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	1		T231	17		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	13		T8	6		T43	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T139	18		T81	8		T85	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	13		T43	4		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T49	9		T137	13		T175	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T4	3		T24	30		T25	34
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	17		T172	2		T56	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	11		T127	19		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	13		T29	20		T135	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	11		T29	9		T174	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T48	4		T128	4		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	6		T8	2		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T48	22		T225	7		T197	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T126	14		T132	10		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T51	11		T199	11		T214	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	10		T212	10		T51	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T47	13		T154	4		T56	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27