Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27136

1

T1

21

T2

41

T3

162

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23293

1

T2

23

T3

161

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

3843

1

T1

21

T2

18

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21100

1

T2

41

T3

161

T4

19

auto[1]

6036

1

T1

21

T3

1

T4

50

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22942

1

T1

21

T2

41

T3

162

auto[1]

4194

1

T4

39

T5

7

T7

20

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	320	1			T2	11		T125	19		T126	23
values[0]	45	1			T144	12		T253	12		T236	10
values[1]	807	1			T1	14		T3	1		T43	15
values[2]	2875	1			T5	8		T6	2		T10	1
values[3]	689	1			T4	25		T29	16		T172	1
values[4]	813	1			T4	25		T8	18		T154	3
values[5]	593	1			T1	7		T127	12		T13	4
values[6]	658	1			T123	1		T124	2		T198	16
values[7]	904	1			T2	18		T4	19		T10	1
values[8]	732	1			T43	20		T48	57		T29	20
values[9]	1093	1			T2	12		T7	34		T8	7
minimum	17607	1			T3	161		T7	122		T8	91

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	602	1			T3	1		T10	1		T43	15
values[1]	2901	1			T5	8		T6	2		T11	8
values[2]	787	1			T4	50		T29	16		T172	1
values[3]	630	1			T8	18		T154	3		T128	8
values[4]	660	1			T1	7		T127	12		T13	4
values[5]	699	1			T4	19		T122	4		T123	1
values[6]	934	1			T2	18		T10	1		T48	37
values[7]	685	1			T43	20		T48	20		T29	20
values[8]	1091	1			T2	23		T7	34		T49	10
values[9]	152	1			T8	7		T125	19		T126	10
minimum	17995	1			T1	14		T3	161		T7	122

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

4372

1

T1

19

T2

38

T4

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	1		T47	14		T49	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T43	5		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T5	1		T6	2		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T172	3		T147	1		T214	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	14		T172	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	12		T29	9		T126	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	9		T154	3		T128	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T37	5		T129	5		T212	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T124	1		T51	3		T174	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	7		T127	12		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T122	1		T172	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	4		T123	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T225	8		T249	1		T226	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T2	18		T10	1		T48	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	14		T48	5		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T155	1		T132	1		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	23		T7	14		T49	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T130	1		T126	15		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T8	6		T125	1		T126	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T79	1		T207	8		T251	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17612	1			T3	161		T7	122		T8	89
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	14		T27	12		T56	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T47	12		T49	13		T141	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	10		T47	9		T29	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T5	7		T11	7		T35	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T147	10		T214	23		T206	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	11		T39	9		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	13		T29	7		T126	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	9		T128	3		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	1		T212	10		T175	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T51	3		T205	12		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	2		T51	7		T141	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T122	3		T141	12		T14	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	15		T198	15		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T225	10		T226	2		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T48	14		T138	11		T197	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T43	6		T48	15		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	1		T204	1		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	20		T49	5		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T126	8		T131	13		T132	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T8	1		T125	18		T126	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T207	11		T251	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	2		T37	1		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T27	11		T56	13		T232	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T2	11		T125	1		T80	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T126	15		T131	1		T139	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T144	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T253	12		T236	10		T254	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T47	14		T49	10		T127	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	14		T3	1		T43	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T5	1		T6	2		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T172	3		T147	1		T214	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	14		T172	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T29	9		T126	14		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	9		T154	3		T128	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	12		T37	5		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T142	15		T41	2		T81	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	7		T127	12		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T124	1		T51	3		T174	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T123	1		T124	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T122	1		T172	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T2	18		T4	4		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T43	14		T48	5		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	23		T155	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T2	12		T7	14		T8	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T130	1		T147	1		T174	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17498	1			T3	161		T7	122		T8	89
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T125	18		T80	10		T179	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T126	8		T131	13		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T254	2		T255	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	12		T49	13		T147	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T43	10		T47	9		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T5	7		T11	7		T35	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	10		T214	23		T206	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	11		T39	9		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T29	7		T126	13		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	9		T128	3		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	13		T37	1		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T41	1		T81	11		T157	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	2		T141	3		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T51	3		T205	12		T14	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T198	15		T51	7		T80	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T122	3		T141	12		T225	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	15		T133	14		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	6		T48	15		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	14		T204	1		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	20		T8	1		T49	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T132	2		T40	1		T226	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	2		T37	1		T39	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	1		T47	13		T49	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T43	11		T47	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T5	8		T6	2		T11	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T172	1		T147	11		T214	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	12		T172	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	14		T29	8		T126	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	12		T154	1		T128	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	6		T129	1		T212	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T124	1		T51	4		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T127	1		T13	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T122	4		T172	1		T141	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	16		T123	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T225	11		T249	1		T226	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	1		T10	1		T48	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T43	7		T48	16		T29	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T155	1		T132	1		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T2	2		T7	21		T49	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T130	1		T126	9		T131	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T8	5		T125	19		T126	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T79	1		T207	12		T251	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17668	1			T3	161		T7	122		T8	91
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	1		T27	12		T56	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	13		T49	9		T132	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T43	4		T29	12		T188	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T35	3		T49	11		T24	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T172	2		T214	22		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	13		T39	10		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	11		T29	8		T126	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	6		T154	2		T128	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T129	4		T212	10		T175	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T51	2		T174	4		T205	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	6		T127	11		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	1		T197	3		T223	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	3		T133	13		T199	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T225	7		T226	8		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	17		T48	22		T143	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T43	13		T48	4		T29	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T144	6		T175	11		T15	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	21		T7	13		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T126	14		T174	10		T132	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T8	2		T126	1		T256	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T207	7		T251	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T127	19		T154	12		T137	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	13		T27	11		T56	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T2	1		T125	19		T80	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T126	9		T131	14		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T144	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T253	1		T236	1		T254	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	13		T49	14		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T3	1		T43	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T5	8		T6	2		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T172	1		T147	11		T214	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	12		T172	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	8		T126	14		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	12		T154	1		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	14		T37	6		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T142	1		T41	3		T81	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T127	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T124	1		T51	4		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T123	1		T124	1		T198	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T122	4		T172	1		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	1		T4	16		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T43	7		T48	16		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T48	15		T155	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T2	1		T7	21		T8	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T130	1		T147	1		T174	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17607	1			T3	161		T7	122		T8	91
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T2	10		T80	11		T267	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T126	14		T139	14		T81	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T144	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T253	11		T236	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	13		T49	9		T127	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	13		T43	4		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T35	3		T49	11		T24	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T172	2		T214	22		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	13		T39	10		T203	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	8		T126	13		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	6		T154	2		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	11		T129	4		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T142	14		T81	8		T220	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	6		T127	11		T202	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T51	2		T174	4		T205	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T51	11		T199	8		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T225	7		T16	1		T203	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	17		T4	3		T133	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	13		T48	4		T29	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	22		T144	6		T175	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	11		T7	13		T8	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T174	10		T132	10		T226	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22764

1

T1

2

T2

3

T3

162

auto[1]

auto[0]

4372

1

T1

19

T2

38

T4

27